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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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//
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// Filename: DECODER.v
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// Version: 3.0
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// History: 2.0 of 11 August 2016
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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//
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// Copyright (C) 2018 Udo Moeller
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// Modules contained in this file:
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// DECODER Instruction Decoding and Flow Control
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,
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PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,
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GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,
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INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP,
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PHOUT );
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input BCLK,BRESET;
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input INT_N,NMI_N; // external inputs
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input [2:0] ANZ_VAL;
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input [55:0] OPREG; // the OPREG contains the bytes to decode, OPREG[55:32] are don't care
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input [8:0] CFG; // CONFIG : many bits are don't-care
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input [11:0] PSR;
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input ACC_DONE;
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input DC_ABORT,IC_ABORT;
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input ACB_ZERO;
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input DONE;
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input [31:0] PC_SAVE;
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input [4:0] STRING;
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input INIT_DONE;
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input ILL,UNDEF;
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input [5:0] TRAPS;
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input IC_READ;
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input STOP_CINV; // not to mix it up with STOP_IC
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output [2:0] GENSTAT;
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output [31:0] DISP,IMME_Q,DISP_BR; // three main data busses : Displacement, Immediate and Displacement for Branch
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output [2:0] USED;
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output NEW;
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output LOAD_PC;
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output NEXT_PCA;
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output [7:0] RDAA,RDAB;
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output [10:0] OPER;
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output [1:0] START,LD_OUT;
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output LD_DIN,LD_IMME;
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output [6:0] INFO_AU;
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output [14:0] ACC_FELD;
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output WREN;
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output [5:0] WRADR;
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output [1:0] WMASKE;
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output reg WR_REG;
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output [12:0] DETOIP;
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output [1:0] MMU_UPDATE;
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output RESTART;
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output STOP_IC;
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output [2:0] RWVAL;
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output ENA_HK;
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output reg ILO;
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output [23:0] COP_OP;
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output [7:0] PHOUT; // for Debug purposes, phase_reg output
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reg [31:0] DISP,disp_val;
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reg [10:0] oper_i;
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reg [2:0] USED;
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reg [14:0] ACC_FELD;
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reg [1:0] ldoreg;
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reg wren_i;
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reg [5:0] wradr_i;
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reg [1:0] wmaske_i;
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reg [1:0] start_i;
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reg [23:0] COP_OP;
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reg spupd_i;
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reg [3:0] disp_sel;
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reg [52:0] op1_feld;
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reg [47:0] op2_feld;
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reg [47:0] op3_feld;
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reg [47:0] op_feld_reg;
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reg [31:0] imme_i;
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reg [2:0] valid;
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reg [7:0] phase_reg;
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reg [3:0] di_stat; // Displacement Status
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reg [3:0] cc_feld;
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reg [1:0] ex_br_op;
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reg acb_reg;
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reg jsr_flag;
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reg [8:0] waitop,wait_reg;
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reg branch;
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reg [3:0] dim_feld;
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reg [66:0] new_op;
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reg short_op_reg;
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reg [15:0] idx_reg;
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reg [35:0] gen_src1;
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reg [33:0] gen_src2;
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reg qw_flag;
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reg long_reg;
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reg new_spsel;
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reg s_user,old_su;
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reg [1:0] stack_sel; // Stack select for USER and SUPERVISOR
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reg [1:0] s_mod; // Modifier for Stack select
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reg upd_info,dw_info;
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reg [2:0] rpointer;
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reg [5:0] resto; // for RESTORE
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reg init_rlist;
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reg new_fp;
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reg format1;
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reg ldpc_phase;
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reg reti_flag;
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reg no_t2p;
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reg iabort,ia_save;
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reg mmu_sel;
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reg [1:0] nmi_reg;
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reg nmi_flag,int_flag;
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reg type_nmi;
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reg [3:0] exc_vector;
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reg phase_exc;
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reg [3:0] ovf_pipe;
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reg dbg_s,dbg_trap,dbg_en,addr_cmp;
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reg ssrc_flag,sdest_flag;
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reg op_setcfg,setcfg_lsb;
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reg inss_op;
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reg exin_cmd,extract; // EXT/INS
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reg bit_reg; // Flag for Bit opcodes : Source2 = Reg
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reg kurz_st; // Flag for MOVM/CMPM
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reg kill_opt; // Flag for optimized MOVS
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reg cmps_flag; // Flag for CMPS
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reg skps_flag; // Flag for SKPS
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reg mt_flag; // Flag for Match and Translate
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reg spu_block; // block of SP update at Long operation
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reg dia_op,dia_flag; // Flag for DIA
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reg m_ussu,m_usel,dc_user; // MOVUS/SU
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reg rwval_flag,wrval_flag; // RDVAL/WRVAL
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reg cinv_flag; // Flag for CINV
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reg [5:0] lmrreg;
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reg no_init,a_ivar;
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reg index_cmd;
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reg stop_d;
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reg dc_ilo;
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wire PHASE_0;
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wire [7:0] phase_ein; // Phase after ABORT has changed the content to 0
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wire de_flag,ivec_flag;
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wire next;
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wire [18:0] new_addr,pop_fp,save_pc;
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wire [13:0] new_regs;
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wire [7:0] new_ph,ppfp;
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wire [7:0] new_nx;
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wire op_1byte,op_12byte,op_2byte,op_3byte;
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wire jump;
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wire short_op,short_def;
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wire opt_imme;
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wire [7:0] opti_byte;
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wire acb_op,acb_flag;
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wire zero,carry_psr,negativ,larger,flag;
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wire valid_size;
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wire op_ok;
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wire stop;
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wire [47:0] opc_bits;
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wire [47:0] op_feld;
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wire [2:0] atys,atyd;
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wire [3:0] auop_s,auop_d;
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wire long,src2_flag,dest_flag;
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wire [6:0] src_1,src_2,src_1l,src_2l;
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wire [1:0] src1_le,src2_le;
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wire acc1,acc2;
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wire spupd;
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wire [6:0] saver; // for SAVE
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wire [2:0] reg_nr;
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wire save_reg;
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wire ld_disp,disp_ok;
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wire store_pc;
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wire do_xor;
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wire do_long;
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wire [1:0] idx_n,n_idx;
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wire idx;
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wire [1:0] otype;
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wire [10:0] opera,op_str,op_sho;
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wire [5:0] dest_r,dest_rl;
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wire phase_idx;
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wire [15:0] idx_bytes,idx_feld;
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wire [3:0] idx_1,idx_2;
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wire [4:0] src1_addr,src2_addr;
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wire [6:0] usp_1,usp_2;
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wire [33:0] tos_oper;
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wire [18:0] adrd1,exr11,exr12,adrd2,adwr2,exr22,exw22,re_wr,st_src,st_src2,st_dest,st_len,st_trde,st_trs2;
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wire [7:0] phrd1,phrd2,phwr2;
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wire [6:0] rega1,irrw1,rega2,irrw2;
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wire [3:0] nxrd1,nxrw2;
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wire rmw;
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wire [6:0] quei1,quet1; // Registeradr
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wire [7:0] endea,goacb,dowait; // Phase
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wire [3:0] diacb; // DIMM access
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wire qword;
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wire [6:0] stack,no_modul,ttstak;
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wire [12:0] pop_1;
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wire mpoi_1,mpoi_2;
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wire [1:0] src1_tos; // the code for REUSE is 2'b11
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wire svc_flag,bpt_flag,flag_flag,trac_flag;
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wire [3:0] misc_vectors;
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wire [2:0] psr_code;
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wire exception;
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wire interrupt;
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wire abort; // DC_ABORT | iabort;
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wire abo_int;
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wire iabo_fall;
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wire abbruch,fpu_trap,dvz_trap;
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wire abbruch2;
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wire dbg_flag;
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wire ovf_op,ovf2_op,ovf_flag;
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wire pc_match;
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wire no_trap;
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wire [10:0] op_psr,op_scp;
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wire [30:0] ai_next;
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wire set_src,set_dest,clr_sflag;
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wire [7:0] rrepa; // Repair Phase of Abort for String opcodes
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wire [7:0] ph_str; // working phase String
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wire ph_match;
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wire t2p;
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wire rw_bit,op_ilo;
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wire setcfg;
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wire string_ende;
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wire wlor; // Flag to generate WR_REG signal
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wire [5:0] wstr0,wstr1,wstr2;
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wire [6:0] rstr0,rstr1,rstr2;
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wire rett_exc;
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wire chk_rmw;
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// Variables for 2- and 3-Byte Dekoder :
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reg [5:0] hzr_c; // CASE Statement
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wire [1:0] hzl_a;
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wire [2:0] hzl_b;
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wire [5:0] hzr_a,hzr_b,hzr_s;
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wire hdx_a;
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wire [3:0] hdo_a,hdo_c,hdo_e;
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wire [7:0] hdo_d;
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wire [1:0] hdl_b,hdl_d,hdl_f,hdl_g,hdl_h;
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wire [2:0] hdl_a,hdl_c,hdl_e;
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wire [5:0] hdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;
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wire [66:0] state_0,state_group_50,state_group_60; // for the Gruppe 2 opcodes
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// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
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parameter addr_nop = 19'b10_0000_0000_0_0000_0000; // all parameter to 0
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parameter push_op = 19'b10_0111_0000_1_1010_0000; // i.e. for BSR, ENTER ...
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parameter push_ea = 19'b10_0111_0000_1_1010_0011; // SAVE middle
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parameter pop_op = 19'b10_1011_0010_1_0000_1000; // RET/RESTORE
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parameter adddisp = 19'b10_0010_0000_0_0000_0011; // for RET : reuse of EA
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parameter adddispn = 19'b10_0010_0000_0_0000_0000; // for RETT : add Disp to Stack
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parameter save_sp = 19'b10_0000_0000_1_0000_0000; // u.a. RET : update of Stack
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parameter next_po = 19'b10_1011_0010_1_0000_1011; // RESTORE middle
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parameter dispmin = 19'b10_0010_0000_0_0100_0011; // Reuse for ENTER
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parameter rmod_rxp = 19'b10_1001_0000_1_0000_0100; // MODUL+0 read : SB , SP Update , therefore no LDEA
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parameter rmod_rtt = 19'b10_1001_0000_0_0000_0100; // MODUL+0 read : SB , no LDEA
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284 |
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parameter rmod_4 = 19'b10_1011_0000_0_0001_0100; // MODUL+4 read : Link Table Base
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285 |
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parameter rmod_8 = 19'b10_1011_0000_0_0010_0100; // MODUL+8 read : Program Base
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parameter rdltab = 19'b10_1010_0000_0_1000_0000; // Link table read - EA Phase
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parameter ea_push = 19'b10_0110_0000_0_1010_0011; // CXP : 2. Push EA Phase
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parameter ea_min8 = 19'b10_1010_0000_0_1011_0011; // CXP : reuse of MOD+8
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parameter pop_ru = 19'b10_1010_0010_0_0000_1011; // RXP : EA Phase MOD POP
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parameter rd_icu = 19'b00_1001_0000_0_1100_0010; // Read ICU : Byte of fix address
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parameter get_vec = 19'b10_1001_0000_0_01xx_0000; // Read Exception-Vector : Index Exception No.
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parameter get_veci = 19'b10_1001_0110_0_0000_0000; // Read Exception-Vector : Index external Interrupt
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parameter load_ea = 19'b10_0010_0000_0_0000_0000; // used for store of TEAR and MSR
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294 |
|
|
parameter save_msr = 19'b10_0010_0001_0_0000_0000; // used for store of TEAR and MSR
|
295 |
|
|
parameter ivar_adr = 19'b10_0000_0100_0_0000_0010; // only pass SRC1
|
296 |
|
|
parameter st_trans = 19'b00_1001_0100_0_0000_0000; // Translate at String : SRC1 + SRC2 , Byte
|
297 |
|
|
parameter src_x = 7'hxx;
|
298 |
|
|
parameter dest_x = 6'hxx;
|
299 |
|
|
parameter imme = {1'b1,6'hxx};
|
300 |
|
|
parameter frame = 7'h18;
|
301 |
|
|
parameter ibase = 7'h1E;
|
302 |
|
|
parameter modul = 7'h1F;
|
303 |
|
|
parameter w_msr = 6'h0A;
|
304 |
|
|
parameter w_tear = 6'h0B;
|
305 |
|
|
parameter fsr_r = 6'h17; // not defined register for FSR for opcodes LFSR and SFSR
|
306 |
|
|
parameter temp_l = 6'h3C;
|
307 |
|
|
parameter temp_h = 6'h3D; // second last space for 8B TEMP register
|
308 |
|
|
parameter temp_1 = 6'h3E; // Backup for register at String operations
|
309 |
|
|
parameter temp_2 = 6'h3F;
|
310 |
|
|
parameter rtmpl = 7'h3C;
|
311 |
|
|
parameter rtmph = 7'h3D;
|
312 |
|
|
parameter rtmp1 = 7'h3E;
|
313 |
|
|
parameter rtmp2 = 7'h3F;
|
314 |
14 |
ns32kum |
parameter op_mov = 11'h345;
|
315 |
|
|
parameter op_adr = 11'h349;
|
316 |
9 |
ns32kum |
parameter op_add = 11'h340; // for CXP
|
317 |
|
|
parameter op_flip = 11'h364; // for CXP : LSHD -16,Ri
|
318 |
|
|
parameter op_lmr = 11'h36A; // for LPR CFG, LMR and CINV
|
319 |
|
|
parameter op_wrp = 11'h387; // for CXP : write PSR , used also for Exception processing
|
320 |
|
|
parameter op_ldp = 11'h388; // for RETT and RETI : load of PSR from Stack
|
321 |
|
|
parameter op_zex = 11'h076; // Zero Extension for ICU Vector - is also used at String Option "T"
|
322 |
|
|
parameter op_cop = 8'hDD; // Coprozessor Opcode
|
323 |
|
|
|
324 |
11 |
ns32kum |
// ++++++++++++++++++++++++++ The switch logic for the state machine +++++++++++++++++++++++++++++
|
325 |
9 |
ns32kum |
|
326 |
|
|
always @(ANZ_VAL)
|
327 |
|
|
case (ANZ_VAL)
|
328 |
|
|
3'd0 : valid = 3'b000;
|
329 |
|
|
3'd1 : valid = 3'b001;
|
330 |
|
|
3'd2 : valid = 3'b011;
|
331 |
|
|
default : valid = 3'b111;
|
332 |
|
|
endcase
|
333 |
|
|
|
334 |
|
|
assign next = ( PHASE_0 ? op_ok : // Opcode decoded or Exception processed
|
335 |
|
|
// Displacement or Immediate operand and external memory access can happen in parallel
|
336 |
|
|
// i.e. addressing mode Memory Relative
|
337 |
|
|
( ((~dim_feld[0] | ACC_DONE) & (~dim_feld[3] | di_stat[0])) // ACC_DONE resets dim_feld
|
338 |
|
|
// long operation
|
339 |
|
|
& ~(long_reg & ~DONE) ) )
|
340 |
|
|
// hard break : abort or fpu_trap or dvz_trap or ovf_flag
|
341 |
|
|
| abbruch ;
|
342 |
|
|
|
343 |
|
|
always @(posedge BCLK or negedge BRESET)
|
344 |
|
|
if (!BRESET) long_reg <= 1'b0;
|
345 |
|
|
else
|
346 |
|
|
long_reg <= next ? do_long : long_reg; // START[1]
|
347 |
|
|
|
348 |
|
|
always @(posedge BCLK or negedge BRESET) // the central phase register
|
349 |
|
|
if (!BRESET) phase_reg <= 8'h0;
|
350 |
|
|
else
|
351 |
|
|
if (next) phase_reg <= new_op[47:40];
|
352 |
|
|
|
353 |
23 |
ns32kum |
assign PHOUT = phase_reg; // only to debug
|
354 |
|
|
|
355 |
9 |
ns32kum |
always @(*) // next switch of micro program counter
|
356 |
|
|
casex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})
|
357 |
23 |
ns32kum |
4'b11_xx : USED = {1'b0,~op_1byte,(op_1byte | op_3byte)} + {2'd0,opt_imme};
|
358 |
9 |
ns32kum |
4'b0x_11 : USED = di_stat[3:1];
|
359 |
|
|
default : USED = 3'd0;
|
360 |
|
|
endcase
|
361 |
|
|
|
362 |
|
|
// Special phases
|
363 |
|
|
|
364 |
|
|
assign PHASE_0 = (phase_reg == 8'h00); // During Phase 0 the opcode is decoded
|
365 |
|
|
|
366 |
|
|
assign NEXT_PCA = PHASE_0 & ~ovf_flag & ~dbg_flag;
|
367 |
|
|
|
368 |
|
|
// Pulse to transfer from Trace Bit to Pending Trace Bit, only once in the beginning of phase 0
|
369 |
|
|
// The priority is such that a TRACE exception is served before an UNDEFINED/ILLEGAL exception
|
370 |
|
|
always @(posedge BCLK) no_t2p <= PHASE_0 & ~op_ok;
|
371 |
|
|
assign t2p = PHASE_0 & ~no_t2p; // signal to I_PFAD
|
372 |
|
|
|
373 |
|
|
// ++++++++++++++++++++++++++ global control signals ++++++++++++++++
|
374 |
|
|
|
375 |
|
|
assign de_flag = CFG[8];
|
376 |
|
|
assign ivec_flag = CFG[0];
|
377 |
|
|
assign dvz_trap = TRAPS[1];
|
378 |
|
|
assign fpu_trap = TRAPS[0];
|
379 |
|
|
|
380 |
11 |
ns32kum |
always @(posedge BCLK) nmi_reg <= {nmi_reg[0],NMI_N}; // one clock sync and than falling edge detection
|
381 |
9 |
ns32kum |
|
382 |
|
|
always @(posedge BCLK or negedge BRESET)
|
383 |
|
|
if (!BRESET) nmi_flag <= 1'b0;
|
384 |
|
|
else nmi_flag <= (nmi_reg == 2'b10) | (nmi_flag & ~(phase_reg == 8'h82));
|
385 |
|
|
|
386 |
|
|
always @(posedge BCLK) int_flag <= PSR[11] & ~INT_N; // one clock to synchronise
|
387 |
|
|
|
388 |
11 |
ns32kum |
assign stop = (int_flag | nmi_flag) & PHASE_0 & ~stop_d; // neccesary if FPU_TRAP and INT at the same time
|
389 |
9 |
ns32kum |
assign interrupt = (int_flag | nmi_flag) & (~PHASE_0 | stop_d);
|
390 |
|
|
|
391 |
|
|
always @(posedge BCLK or negedge BRESET)
|
392 |
|
|
if (!BRESET) stop_d <= 1'd0;
|
393 |
|
|
else stop_d <= stop;
|
394 |
|
|
|
395 |
|
|
// ++++++++++++++++++++++++++ Exception processing +++++++++++++++
|
396 |
|
|
|
397 |
|
|
// IC_ABORT is valid if Opcode Decoder cannot continue
|
398 |
|
|
assign iabo_fall = IC_ABORT & (PHASE_0 ? ~op_ok : (~di_stat[0] & dim_feld[3]));
|
399 |
|
|
|
400 |
|
|
always @(posedge BCLK) iabort <= iabo_fall & ~ia_save; // DC_ABORT ist a pulse
|
401 |
|
|
always @(posedge BCLK) ia_save <= iabo_fall;
|
402 |
|
|
|
403 |
|
|
// mmu_sel is used in ADDR_UNIT
|
404 |
|
|
always @(posedge BCLK) mmu_sel <= DC_ABORT | (mmu_sel & ~iabort); // 1 = DCACHE , 0 = ICACHE
|
405 |
|
|
assign MMU_UPDATE[0] = mmu_sel;
|
406 |
|
|
|
407 |
|
|
assign abort = DC_ABORT | iabort;
|
408 |
|
|
|
409 |
|
|
// that is the end of String loops where interrupts are checked : 8'hC7 & 8'hCF
|
410 |
11 |
ns32kum |
assign string_ende = (phase_reg[7:4] == 4'hC) & (phase_reg[2:0] == 3'b111); // attention : 8'hCF does not exist
|
411 |
9 |
ns32kum |
|
412 |
11 |
ns32kum |
always @(posedge BCLK) if (PHASE_0 || string_ende) type_nmi <= nmi_flag; // during processing kept stable
|
413 |
9 |
ns32kum |
|
414 |
|
|
assign svc_flag = (OPREG[7:0] == 8'hE2) & valid[0]; // Vector 5 : 0101 , Illegal Vector 4 : 0100
|
415 |
|
|
assign bpt_flag = (OPREG[7:0] == 8'hF2) & valid[0]; // Vector 8 : 1000 , Undefined Vec. 10 : 1010
|
416 |
|
|
assign flag_flag = (phase_reg == 8'h89) & flag; // Vector 7 - has an own state
|
417 |
|
|
assign trac_flag = t2p & PSR[10]; // Vector 9 : 1001 , PSR[10] = P Bit , Pending Trace
|
418 |
|
|
assign ovf_flag = (ovf_pipe[3] & flag) | (ovf_pipe[1] & TRAPS[2]); // Vector 13 : 1101
|
419 |
|
|
assign dbg_flag = dbg_trap | (dbg_s & PHASE_0); // Vector 14 : 1110
|
420 |
|
|
|
421 |
|
|
// abort + dvz_trap during a opcode, fpu_trap + ovf_flag + dbg_flag later
|
422 |
|
|
assign abbruch = abort | fpu_trap | dvz_trap | ovf_flag | dbg_flag; // this 5 stop everything
|
423 |
|
|
assign abbruch2 = abort | fpu_trap | dvz_trap | ovf_flag; // for exc_vector generation
|
424 |
|
|
|
425 |
|
|
// forces the next step of state machine (op_ok), generates otype="11" for Trap Service
|
426 |
|
|
assign exception = interrupt | svc_flag | bpt_flag | ILL | UNDEF | trac_flag | abbruch;
|
427 |
|
|
|
428 |
|
|
// a TRACE Exception is done before the opcode execution
|
429 |
11 |
ns32kum |
assign misc_vectors = trac_flag ? 4'h9 : {(bpt_flag | UNDEF),(svc_flag | ILL),UNDEF,svc_flag}; // the vectors are exclusiv
|
430 |
9 |
ns32kum |
|
431 |
|
|
always @(posedge BCLK)
|
432 |
|
|
if (PHASE_0 || abbruch) // ABORTs, fpu_trap, dvz_trap + ovf_flag can happen every time
|
433 |
|
|
begin
|
434 |
11 |
ns32kum |
exc_vector <= abbruch ? (abbruch2 ? {ovf_flag,(dvz_trap | ovf_flag),~ovf_flag,(fpu_trap | ovf_flag)} : 4'hE)
|
435 |
9 |
ns32kum |
: (interrupt ? {3'b0,nmi_flag} : misc_vectors); // misc_vectors is default
|
436 |
|
|
end
|
437 |
|
|
else
|
438 |
|
|
if (flag_flag) exc_vector <= 4'h7; // FLAG-Trap
|
439 |
|
|
else
|
440 |
|
|
if (interrupt && string_ende) exc_vector <= {3'b0,nmi_flag};
|
441 |
|
|
|
442 |
11 |
ns32kum |
assign psr_code[2] = ~psr_code[1]; // Absicht : codiert das Sichern des PSR bei Exception-Entry
|
443 |
|
|
assign psr_code[1] = abort | ILL | UNDEF | trac_flag; // enable for reseting the P-Bit during write of PSR to stack
|
444 |
9 |
ns32kum |
assign psr_code[0] = (interrupt & ~fpu_trap) | abort; // enable for reseting the I-Bit of new PSR
|
445 |
|
|
|
446 |
|
|
// valid codes are x'89 to x'8F
|
447 |
11 |
ns32kum |
assign op_psr = {8'b0_00_1000_1,psr_code}; // is used during first clock cylce after exception, is transfered as OPCODE to I_PFAD
|
448 |
9 |
ns32kum |
|
449 |
11 |
ns32kum |
// Specialitiies : ABORT stores address & flags , the Interrrupts read vectors : all is used in big CASE
|
450 |
9 |
ns32kum |
assign abo_int = (exc_vector == 4'h2) | (exc_vector[3:1] == 3'b000);
|
451 |
|
|
assign ai_next = (exc_vector == 4'h2) ? {load_ea,8'h84,4'h0} : {rd_icu,8'h82,4'h1};
|
452 |
|
|
|
453 |
11 |
ns32kum |
assign save_pc = {7'b10_0010_0,dia_flag,7'b00_0_0000,dia_flag,3'b001}; // Exception : PC_ARCHI => EA, special case DIA
|
454 |
|
|
assign no_trap = ~fpu_trap & ~ovf_flag & ~dbg_flag; // suppresion of WREN and LD_OUT[1] and ADDR_UNIT operation
|
455 |
9 |
ns32kum |
|
456 |
|
|
// ++++++++++++++++++++++++++ Overflow Trap ++++++++++++++
|
457 |
|
|
|
458 |
|
|
always @(posedge BCLK)
|
459 |
|
|
if (ovf_flag || !PSR[4]) ovf_pipe <= 4'd0;
|
460 |
|
|
else
|
461 |
11 |
ns32kum |
if (PHASE_0) ovf_pipe <= {ovf_pipe[2],(ovf_op & op_ok),ovf_pipe[0],(ovf2_op & op_ok)}; // V-Bit switches on
|
462 |
9 |
ns32kum |
|
463 |
|
|
assign ovf_op = ( ((OPREG[6:2] == 5'b000_11) // ADDQi
|
464 |
|
|
| (OPREG[3:2] == 2'b00)) & (OPREG[1:0] != 2'b10)) // ADDi,ADDCi,SUBi,SUBCi
|
465 |
|
|
| ((OPREG[7:0] == 8'h4E) & OPREG[13] & (OPREG[11:10] == 2'b00)) // NEGi,ABSi
|
466 |
|
|
| ((OPREG[7:0] == 8'hEE) & ~OPREG[10]); // CHECKi
|
467 |
|
|
|
468 |
11 |
ns32kum |
assign ovf2_op = ((OPREG[6:2] == 5'b100_11) & (OPREG[1:0] != 2'b10)) // ACBi, these overflows have no FLAG
|
469 |
9 |
ns32kum |
| ((OPREG[13:10] == 4'h1) & (OPREG[7:0] == 8'h4E)) // ASHi
|
470 |
|
|
| ( OPREG[13] & (OPREG[11] == OPREG[10]) & (OPREG[7:0] == 8'hCE)); // MULi,DEIi,QUOi,DIVi
|
471 |
|
|
|
472 |
|
|
// ++++++++++++++++++++++++++ Debug Trap ++++++++++++++
|
473 |
|
|
|
474 |
|
|
always @(posedge BCLK or negedge BRESET)
|
475 |
|
|
if (!BRESET) dbg_s <= 1'b0;
|
476 |
|
|
else dbg_s <= dbg_trap | (dbg_s & ~((exc_vector == 4'hE) & (phase_reg == 8'h81)));
|
477 |
|
|
|
478 |
|
|
always @(posedge BCLK) dbg_en <= op_ok | ~PHASE_0;
|
479 |
|
|
|
480 |
|
|
assign pc_match = dbg_en & TRAPS[3] & PHASE_0 & ~exception; // TRAPS[3] is only combinatorical
|
481 |
|
|
|
482 |
11 |
ns32kum |
always @(posedge BCLK) dbg_trap <= (pc_match | (addr_cmp & PHASE_0)) & TRAPS[5]; // TRAPS[5] = Enable Trap
|
483 |
9 |
ns32kum |
|
484 |
|
|
always @(posedge BCLK) addr_cmp <= TRAPS[4] | (addr_cmp & ~PHASE_0); // TRAPS[4] = CAR HIT
|
485 |
|
|
|
486 |
|
|
// ++++++++++++++++++++++++++ Special case String Abort ++++++++++++++
|
487 |
|
|
|
488 |
11 |
ns32kum |
// Flags cleared if entry and exit of string operation and during Abort sequence, not valid for MOVM/CMPM
|
489 |
9 |
ns32kum |
// special case UNTIL/WHILE : reset if exit (op_feld_reg[17] = 1 = UNTIL)
|
490 |
11 |
ns32kum |
assign clr_sflag = (phase_reg == 8'hC0) | (phase_reg == 8'hC7) | (phase_reg == 8'hC8) | (phase_reg == 8'h81)
|
491 |
9 |
ns32kum |
| (((phase_reg == 8'hD7) | (phase_reg == 8'hDF)) & ~(STRING[3] ^ op_feld_reg[17])) ;
|
492 |
|
|
assign set_src = (phase_reg == 8'hC1) | (phase_reg == 8'hC9);
|
493 |
|
|
assign set_dest = (phase_reg == 8'hC4) | (phase_reg == 8'hCC);
|
494 |
|
|
|
495 |
|
|
always @(posedge BCLK or negedge BRESET) // R1 is modified
|
496 |
|
|
if (!BRESET) ssrc_flag <= 1'b0;
|
497 |
|
|
else ssrc_flag <= (set_src & ~kurz_st) | (ssrc_flag & ~clr_sflag);
|
498 |
|
|
|
499 |
|
|
always @(posedge BCLK or negedge BRESET) // R2 is modified
|
500 |
|
|
if (!BRESET) sdest_flag <= 1'b0;
|
501 |
|
|
else sdest_flag <= (set_dest & ~kurz_st) | (sdest_flag & ~clr_sflag);
|
502 |
|
|
|
503 |
|
|
assign rrepa = {7'b1000_011,~sdest_flag}; // R1 and if necessary R2 restore
|
504 |
|
|
|
505 |
|
|
// ++++++++++++++++++++++++++ The one byte opcodes +++++++++++++++++++
|
506 |
|
|
|
507 |
11 |
ns32kum |
// The one byte opcodes have a special case : one byte opcode but the second byte should be valid too
|
508 |
9 |
ns32kum |
// Used with SAVE, RESTORE, ENTER and EXIT with their reg list.
|
509 |
|
|
// The advantage is that the reg list is store in op_feld_reg.
|
510 |
|
|
|
511 |
|
|
// [52:34] addressing
|
512 |
|
|
// [33:20] register
|
513 |
|
|
// [19:18] 1 or 2 Byte opcode
|
514 |
|
|
// [17:16] BSR/BR
|
515 |
|
|
// [15:8] next phase
|
516 |
|
|
// [7:4] START + LD_OUT
|
517 |
|
|
// [3:0] operand access : Displacement or Speicher
|
518 |
|
|
|
519 |
|
|
always @(*) // SVC (E2) and BPT (F2) decode as exception
|
520 |
|
|
casex (OPREG[7:0])
|
521 |
|
|
8'hxA : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b01,8'h01,4'h0,4'hE}; // Bcc , DISP read
|
522 |
|
|
8'h02 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b10,8'h01,4'h0,4'hE}; // BSR , DISP read
|
523 |
|
|
8'h12 : op1_feld = {pop_op , src_x, stack, 2'b01,2'b00,8'h2A,4'h0,4'h1}; // RET , DISP later
|
524 |
|
|
8'h22 : op1_feld = {rmod_4 , src_x, modul, 2'b01,2'b00,8'h35,4'h0,4'h1}; // CXP
|
525 |
|
|
8'h32 : op1_feld = {pop_op, src_x, stack, 2'b01,2'b00,8'h40,4'h0,4'h1}; // RXP
|
526 |
|
|
8'h42 : op1_feld = {pop_op, src_x, stack, 2'b01,2'b00,8'h46,4'h0,4'h1}; // RETT
|
527 |
|
|
8'h52 : op1_feld = {rd_icu, src_x, src_x, 2'b01,2'b00,8'h45,4'h0,4'h1}; // RETI
|
528 |
|
|
8'h62 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h30,4'h0,4'h0}; // SAVE
|
529 |
|
|
8'h72 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h32,4'h0,4'h0}; // RESTORE
|
530 |
|
|
8'h82 : op1_feld = {push_op , frame, stack, 2'b10,2'b00,8'h2D,4'h2,4'h1}; // ENTER : PUSH FP
|
531 |
|
|
8'h92 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h32,4'h0,4'h0}; // EXIT : POP FP
|
532 |
|
|
8'hA2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h00,4'h0,4'h0}; // NOP
|
533 |
|
|
8'hB2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h88,4'h0,4'h0}; // WAIT
|
534 |
|
|
8'hC2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h88,4'h0,4'h0}; // DIA
|
535 |
|
|
8'hD2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h89,4'h0,4'h0}; // FLAG
|
536 |
|
|
default : op1_feld = {19'hxxxxx,14'hxxxx, 2'b00,2'b00,16'hxxxx};
|
537 |
|
|
endcase
|
538 |
|
|
|
539 |
23 |
ns32kum |
assign op_1byte = op1_feld[18] & valid[0];
|
540 |
|
|
assign op_12byte = op1_feld[19] & valid[1];
|
541 |
9 |
ns32kum |
|
542 |
|
|
assign new_addr = op1_feld[52:34];
|
543 |
|
|
assign new_regs = op1_feld[33:20];
|
544 |
|
|
assign new_ph = op1_feld[15:8];
|
545 |
|
|
assign new_nx = op1_feld[7:0]; // at Bcond DISP read
|
546 |
|
|
|
547 |
|
|
assign pop_fp = new_fp ? pop_op : addr_nop;
|
548 |
|
|
assign ppfp = new_fp ? 8'h34 : 8'h00;
|
549 |
|
|
|
550 |
|
|
always @(posedge BCLK)
|
551 |
|
|
if (PHASE_0)
|
552 |
|
|
begin
|
553 |
|
|
ex_br_op <= op1_feld[17:16]; // BSR/BR
|
554 |
|
|
cc_feld <= OPREG[7:4];
|
555 |
|
|
new_fp <= (OPREG[7:6] == 2'b10); // not decoded complete but is sufficient
|
556 |
|
|
reti_flag <= OPREG[4]; // only difference between RETI and RETT is important
|
557 |
|
|
dia_op <= OPREG[6]; // only difference between DIA and WAIT is important
|
558 |
|
|
end
|
559 |
|
|
|
560 |
11 |
ns32kum |
always @(posedge BCLK) dia_flag <= dia_op & (phase_reg == 8'h88); // special case DIA compared to WAIT : Addr DIA to Stack
|
561 |
9 |
ns32kum |
|
562 |
11 |
ns32kum |
always @(posedge BCLK) // Format 1 opcodes write always DWord to reg, the same is true for Exceptions
|
563 |
9 |
ns32kum |
if (PHASE_0 || abbruch) format1 <= (valid[0] & (OPREG[3:0] == 4'h2)) | exception;
|
564 |
|
|
else
|
565 |
|
|
if (flag_flag || (interrupt && string_ende)) format1 <= 1'b1;
|
566 |
|
|
|
567 |
|
|
// Branch etc. CXP CXPD
|
568 |
11 |
ns32kum |
assign store_pc = (phase_reg == 8'd1) | (phase_reg == 8'h37) | (phase_reg == 8'h6B); // only save in DIN Reg of DATENPFAD
|
569 |
9 |
ns32kum |
assign jump = (ex_br_op[0] & branch) | (acb_reg & ~ACB_ZERO) | ex_br_op[1];
|
570 |
|
|
|
571 |
11 |
ns32kum |
always @(posedge BCLK) ldpc_phase <= (phase_reg == 8'h3E) // PC load at CXP/Traps , all one clock cycle guaranted
|
572 |
9 |
ns32kum |
| (phase_reg == 8'h43) // PC load at RXP
|
573 |
|
|
| ((phase_reg == 8'h49) & reti_flag) // PC load at RETI
|
574 |
|
|
| (phase_reg == 8'h4E) // PC load at RETT
|
575 |
|
|
| (phase_reg == 8'h66) // PC load at JUMP/JSR/CASE
|
576 |
|
|
| (phase_reg == 8'h7B); // PC load at DE = Direct Exception
|
577 |
|
|
|
578 |
|
|
assign NEW = ((phase_reg == 8'd1) & jump & di_stat[0]) | LOAD_PC;
|
579 |
11 |
ns32kum |
assign LOAD_PC = ((phase_reg == 8'h2B) & di_stat[0]) // only one pulse, but DISP must be ok => di_stat[0] (RET)
|
580 |
9 |
ns32kum |
| ldpc_phase;
|
581 |
|
|
|
582 |
|
|
assign no_modul = de_flag ? {1'b0,dest_x} : {1'b1,modul[5:0]};
|
583 |
|
|
|
584 |
|
|
assign negativ = PSR[7];
|
585 |
|
|
assign zero = PSR[6];
|
586 |
|
|
assign flag = PSR[5];
|
587 |
|
|
assign larger = PSR[2];
|
588 |
|
|
assign carry_psr = PSR[0];
|
589 |
|
|
|
590 |
11 |
ns32kum |
assign rett_exc = ~reti_flag & (phase_reg == 8'h4B); // special case RETT : Stack can change during opcode
|
591 |
9 |
ns32kum |
always @(posedge BCLK) phase_exc <= (phase_reg == 8'h80); // 1. Exception phase
|
592 |
11 |
ns32kum |
always @(negedge BCLK) if (PHASE_0 || phase_exc || rett_exc) s_user <= PSR[9]; // Select Bit for Stack, delayed update
|
593 |
9 |
ns32kum |
always @(negedge BCLK)
|
594 |
|
|
if (PHASE_0 || phase_exc) s_mod <= {PSR[9],~PSR[9]};
|
595 |
|
|
else
|
596 |
|
|
if (rett_exc) s_mod <= s_mod | {PSR[9],~PSR[9]}; // Both can be updated
|
597 |
|
|
|
598 |
|
|
always @(cc_feld or zero or carry_psr or larger or negativ or flag)
|
599 |
|
|
case (cc_feld)
|
600 |
|
|
4'h0 : branch = zero; // EQual
|
601 |
|
|
4'h1 : branch = ~zero; // Not Equal
|
602 |
|
|
4'h2 : branch = carry_psr; // Carry Set
|
603 |
|
|
4'h3 : branch = ~carry_psr; // Carry Clear
|
604 |
|
|
4'h4 : branch = larger; // Higher
|
605 |
|
|
4'h5 : branch = ~larger; // Lower or Same
|
606 |
|
|
4'h6 : branch = negativ; // Greater Than
|
607 |
|
|
4'h7 : branch = ~negativ; // Less or Equal
|
608 |
|
|
4'h8 : branch = flag; // Flag Set
|
609 |
|
|
4'h9 : branch = ~flag; // Flag Clear
|
610 |
|
|
4'hA : branch = ~larger & ~zero; // LOwer
|
611 |
|
|
4'hB : branch = larger | zero; // Higher or Same
|
612 |
|
|
4'hC : branch = ~negativ & ~zero; // Less Than
|
613 |
|
|
4'hD : branch = negativ | zero; // Greater or Equal
|
614 |
|
|
4'hE : branch = 1'b1; // True
|
615 |
|
|
4'hF : branch = 1'b0; // False
|
616 |
|
|
endcase
|
617 |
|
|
|
618 |
|
|
// +++++++++++++++++++++++ Register List Processing ++++++++++++++++++++++++++++
|
619 |
|
|
|
620 |
|
|
always @(posedge BCLK) init_rlist <= PHASE_0 | (phase_reg == 8'h2E);
|
621 |
|
|
|
622 |
|
|
always @(posedge BCLK)
|
623 |
|
|
if (PHASE_0) rpointer <= 3'b000;
|
624 |
|
|
else
|
625 |
|
|
if (ACC_DONE || init_rlist) rpointer <= reg_nr;
|
626 |
|
|
|
627 |
11 |
ns32kum |
REG_LIST scanner ( .DIN(op_feld_reg[22:15]), .INIT(init_rlist), .IPOS(rpointer), .VALID(save_reg), .OPOS(reg_nr) );
|
628 |
9 |
ns32kum |
|
629 |
|
|
assign saver = {4'h0,reg_nr};
|
630 |
|
|
|
631 |
11 |
ns32kum |
always @(posedge BCLK) if (ACC_DONE || init_rlist) resto <= {3'h0,~reg_nr}; // EXIT and RESTORE have the list mirrored : R0...R7
|
632 |
9 |
ns32kum |
|
633 |
11 |
ns32kum |
// ++++++++++++++++++++++++++ Processing of Displacement and Immediate Operand +++++++++++++++++++
|
634 |
9 |
ns32kum |
|
635 |
|
|
always @(posedge BCLK or negedge BRESET) // Flag for DISP and IMME access
|
636 |
|
|
if (!BRESET) dim_feld[3] <= 1'b0;
|
637 |
|
|
else dim_feld[3] <= next ? new_op[3] : ~di_stat[0] & dim_feld[3];
|
638 |
|
|
|
639 |
|
|
always @(posedge BCLK) if (next) dim_feld[2:1] <= new_op[2:1];
|
640 |
|
|
|
641 |
|
|
always @(posedge BCLK or negedge BRESET) // Flag for external access
|
642 |
|
|
if (!BRESET) dim_feld[0] <= 1'b0;
|
643 |
|
|
else dim_feld[0] <= next ? new_op[0] : ~ACC_DONE & dim_feld[0];
|
644 |
|
|
|
645 |
|
|
// special case QWORD, last term for security
|
646 |
|
|
always @(posedge BCLK) qw_flag <= dim_feld[0] & ACC_DONE & (ACC_FELD[13:12] == 2'b11) & ~qw_flag;
|
647 |
|
|
|
648 |
11 |
ns32kum |
assign LD_IMME = (dim_feld[3] & (dim_feld[2:1] != 2'b11)) | short_op | store_pc; // Data multiplexer
|
649 |
|
|
assign LD_DIN = (di_stat[0] & dim_feld[3] & (dim_feld[2:1] != 2'b11)) // Enable for DIN Register
|
650 |
|
|
| (ACC_DONE & dim_feld[0]) | qw_flag | short_op | store_pc; // next not possible : i.e. immediate and disp parallel
|
651 |
9 |
ns32kum |
assign ld_disp = (dim_feld[3:1] == 3'b111); // Enable for DISP Register
|
652 |
|
|
|
653 |
|
|
// Signal to ADDR_UNIT , only Displacement critical
|
654 |
|
|
assign disp_ok = ld_disp ? di_stat[0] : 1'b1;
|
655 |
|
|
|
656 |
11 |
ns32kum |
always @(dim_feld or OPREG or valid or ANZ_VAL) // Bit 0 is "Data ok", the upper 3 bits are for USED
|
657 |
9 |
ns32kum |
casex ({dim_feld[2:1],OPREG[7:6]})
|
658 |
|
|
4'b00_xx : di_stat = {3'b001,valid[0]};
|
659 |
23 |
ns32kum |
4'b01_xx : di_stat = {3'b010,valid[1]};
|
660 |
9 |
ns32kum |
4'b10_xx : di_stat = {3'b100,ANZ_VAL[2]};
|
661 |
|
|
4'b11_0x : di_stat = {3'b001,valid[0]};
|
662 |
23 |
ns32kum |
4'b11_10 : di_stat = {3'b010,valid[1]};
|
663 |
9 |
ns32kum |
4'b11_11 : di_stat = {3'b100,ANZ_VAL[2]};
|
664 |
|
|
endcase
|
665 |
|
|
|
666 |
|
|
always @(OPREG)
|
667 |
|
|
casex (OPREG[7:6])
|
668 |
|
|
2'b0x : disp_val = {{26{OPREG[6]}},OPREG[5:0]};
|
669 |
|
|
2'b10 : disp_val = {{19{OPREG[5]}},OPREG[4:0],OPREG[15:8]};
|
670 |
|
|
2'b11 : disp_val = {{3{OPREG[5]}},OPREG[4:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
|
671 |
|
|
endcase
|
672 |
|
|
|
673 |
|
|
assign DISP_BR = disp_val; // DISP is also used for Bcc opcode
|
674 |
|
|
|
675 |
|
|
// The generator for DISP : data is used in ADDR_UNIT
|
676 |
|
|
always @(*)
|
677 |
|
|
casex ({ld_disp,disp_sel}) // disp_sel from new_op
|
678 |
|
|
5'b1_00xx : DISP = disp_val;
|
679 |
|
|
5'b1_01xx : DISP = 32'h0 - disp_val; // special case for ENTER
|
680 |
|
|
5'b1_1xxx : DISP = {disp_val[29:0],2'b00}; // DISP*4 for External Address Mode
|
681 |
|
|
5'b0_11xx : DISP = {20'hFFFFF,3'h7,type_nmi,8'h00}; // Interrupt Service Address
|
682 |
|
|
5'b0_1000 : DISP = 32'hFFFF_FFFF; // PUSH Byte
|
683 |
|
|
5'b0_1001 : DISP = 32'hFFFF_FFFE; // PUSH Word
|
684 |
|
|
5'b0_1010 : DISP = 32'hFFFF_FFFC; // PUSH DWord
|
685 |
|
|
5'b0_1011 : DISP = 32'hFFFF_FFF8; // PUSH QWord
|
686 |
|
|
5'b0_01xx : DISP = {26'h0,exc_vector,2'b00}; // the exception vector as Offset for INTBASE
|
687 |
|
|
5'b0_00xx : DISP = {28'h0,disp_sel[1:0],2'b00}; // 0,+4,+8,+12 used with MOD, default is 0
|
688 |
|
|
endcase
|
689 |
|
|
|
690 |
23 |
ns32kum |
always @(*)
|
691 |
9 |
ns32kum |
casex ({short_op,dim_feld[2:1]})
|
692 |
|
|
3'b000 : imme_i = op_setcfg ? {28'h0000_00F,OPREG[2:0],setcfg_lsb} : {24'hxx_xxxx,OPREG[7:0]};
|
693 |
|
|
3'b001 : imme_i = {16'hxxxx,OPREG[7:0],OPREG[15:8]};
|
694 |
|
|
3'b01x : imme_i = {OPREG[7:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
|
695 |
23 |
ns32kum |
3'b1xx : imme_i = opt_imme ? {24'hxxxx_xx,opti_byte} : {{29{OPREG[10]}},OPREG[9:7]}; // for MOVQ etc. only OPREG can be used
|
696 |
9 |
ns32kum |
endcase
|
697 |
|
|
|
698 |
|
|
assign IMME_Q = store_pc ? PC_SAVE : imme_i;
|
699 |
|
|
|
700 |
|
|
// ++++++++++++++ Stack Control +++++++++++++++++
|
701 |
|
|
|
702 |
|
|
always @(posedge BCLK or negedge BRESET)
|
703 |
|
|
if (!BRESET) new_spsel <= 1'b0;
|
704 |
|
|
else new_spsel <= spupd | (new_spsel & ~PHASE_0 & ~fpu_trap & ~dvz_trap);
|
705 |
|
|
|
706 |
11 |
ns32kum |
always @(posedge BCLK) upd_info <= PHASE_0 & new_spsel; // one clock cycle earlier a change occurs, i.e. ADDF TOS,F0 => fpu_trap
|
707 |
9 |
ns32kum |
|
708 |
|
|
assign do_xor = fpu_trap ? upd_info : (PHASE_0 & new_spsel);
|
709 |
|
|
|
710 |
|
|
always @(negedge BCLK or negedge BRESET)
|
711 |
|
|
if (!BRESET) stack_sel <= 2'b00;
|
712 |
|
|
else
|
713 |
|
|
if (do_xor) stack_sel <= stack_sel ^ s_mod;
|
714 |
|
|
|
715 |
|
|
// Special case RETT
|
716 |
11 |
ns32kum |
always @(posedge BCLK) if (!phase_reg[1]) old_su <= s_user; // is tested in state x'49 and used in x'4B
|
717 |
9 |
ns32kum |
assign ttstak = {1'b0,((old_su == PSR[9]) ^ stack_sel[PSR[9]]),3'b110,PSR[9],1'b1};
|
718 |
|
|
|
719 |
|
|
// ++++++++++++++ 2 byte opcodes +++++++++++++++++
|
720 |
|
|
|
721 |
|
|
// Hint : short_op is decoded separatly
|
722 |
|
|
|
723 |
|
|
// [47:45] Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
|
724 |
|
|
// [44:42] Destination : like [47:45]
|
725 |
|
|
// [41] long opcode [41:39] only for standard sequenz - not Gruppe 2
|
726 |
|
|
// [40] src2_flag - Source 2 is read
|
727 |
|
|
// [39] dest_flag - a target operand exists
|
728 |
|
|
// [38:33] src1_r Register field, no message about Immediate
|
729 |
|
|
// [32:27] src2_r Register field
|
730 |
|
|
// [26:25] src1_le Length of Source1 - this is used for qword
|
731 |
|
|
// [24:23] src2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE
|
732 |
|
|
// [22:18] src1 field
|
733 |
|
|
// [17:13] src2 field
|
734 |
|
|
// [12:11] op_type 2 Bit for sort of opcode
|
735 |
|
|
// [10] FL : F=1/L=0
|
736 |
|
|
// [9:8] original BWD : B=00/W=01/D=11
|
737 |
|
|
// [7:0] opcode: operation code
|
738 |
|
|
|
739 |
23 |
ns32kum |
assign valid_size = (OPREG[1:0] != 2'b10) & valid[1]; // valid size + valid OPREG-Bytes
|
740 |
9 |
ns32kum |
|
741 |
|
|
assign hzl_a = (OPREG[1:0] == 2'b11) ? 2'b10 : OPREG[1:0]; // length field recoded
|
742 |
|
|
assign hzl_b = {1'b0,OPREG[1:0]}; // standard Length field
|
743 |
|
|
assign hzr_a = {3'b000,OPREG[13:11]}; // SRC2 or SRC1 regfield
|
744 |
|
|
assign hzr_b = {3'b000,OPREG[8:6]}; // SRC2 regfield
|
745 |
11 |
ns32kum |
assign hzr_s = {((OPREG[15:11] == 5'h17) ^ stack_sel[s_user]),3'b110,s_user,1'b1}; // USER or SUPERVISOR Stack, TOS special case
|
746 |
9 |
ns32kum |
// Special case LPR & SPR regfield:
|
747 |
|
|
always @(OPREG or stack_sel or s_user)
|
748 |
|
|
casex ({OPREG[10:7]})
|
749 |
|
|
4'b1001 : hzr_c = {stack_sel[s_user],3'b110,s_user,1'b1}; // USER or SUPERVISOR Stack
|
750 |
|
|
4'b1011 : hzr_c = {stack_sel[1] ,3'b110,1'b1, 1'b1}; // USER Stack
|
751 |
|
|
4'b1100 : hzr_c = OPREG[6] ? temp_h : 6'h1C; // CFG special case : LPR : SPR
|
752 |
|
|
default : hzr_c = {2'b01,OPREG[10:7]};
|
753 |
|
|
endcase
|
754 |
|
|
|
755 |
11 |
ns32kum |
// Unfortunately SETCFG must be implemented : it is transformed to a two byte opcode with one byte IMM operand
|
756 |
23 |
ns32kum |
assign setcfg = (OPREG[13:0] == 14'h0B0E) & valid[1];
|
757 |
9 |
ns32kum |
|
758 |
|
|
always @(*)
|
759 |
|
|
casex ({setcfg,OPREG[10:2]})
|
760 |
|
|
// Short-Op Codes , ACB is an ADD with following jump
|
761 |
11 |
ns32kum |
10'b0xxxx_x0011 : op2_feld = {6'o11,3'o3,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h40}; // ADDQ ACB
|
762 |
|
|
10'b0xxxx_00111 : op2_feld = {6'o11,3'o2,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h41}; // CMPQ
|
763 |
|
|
10'b0xxxx_01011 : op2_feld = {6'o11,3'o1,hzr_c,hzr_a,hzl_a,hzl_a,5'h00,OPREG[15:11],2'b00,hzl_b,8'h45}; // SPR
|
764 |
9 |
ns32kum |
// Scond is moving the SHORT operand in the Integer area as condition field
|
765 |
11 |
ns32kum |
10'b0xxxx_01111 : op2_feld = {6'o11,3'o1,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h7A}; // Format 7, A=(UNDEF)
|
766 |
|
|
10'b0xxxx_10111 : op2_feld = {6'o11,3'o1,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h45}; // MOVQ
|
767 |
|
|
10'b0xxxx_11011 : op2_feld = {6'o11,3'o1,hzr_a,hzr_c,hzl_a,2'b10,OPREG[15:11],5'h00,2'b00,hzl_b,8'h76}; // LPR => MOVZiD
|
768 |
9 |
ns32kum |
// Format 3 opcodes :
|
769 |
11 |
ns32kum |
10'b00x10_11111 : op2_feld = {6'o11,3'o1,hzr_a,6'h1D,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b00,hzl_b,4'h3,OPREG[10:7]}; // BIC/SPSR
|
770 |
|
|
10'b0x100_11111 : op2_feld = {6'o61,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // JUMP/JSR
|
771 |
|
|
10'b01110_11111 : op2_feld = {6'o11,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // CASE
|
772 |
9 |
ns32kum |
// Format 4 opcodes : main group
|
773 |
11 |
ns32kum |
10'b0xxxx_xxxx0 : op2_feld = {6'o11,3'o3,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6], 2'b00,hzl_b,4'h4,OPREG[5:2]};
|
774 |
|
|
10'b0xxxx_x0001 : op2_feld = {6'o11,3'o2,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6], 2'b00,hzl_b,4'h4,OPREG[5:2]}; //CMP no WR
|
775 |
|
|
10'b0xxxx_x0101 : op2_feld = {6'o11,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6], 2'b00,hzl_b,4'h4,OPREG[5:2]}; //MOV no 2.Op
|
776 |
9 |
ns32kum |
10'b0xxxx_x1101 : op2_feld = (OPREG[10:9] == 2'b00) ? // target is Register => standard flow
|
777 |
|
|
{6'o11,3'o2,hzr_a,hzr_b,hzl_a,2'bxx,OPREG[15:6], 2'b00,hzl_b,4'h4,OPREG[5:2]} // TBIT
|
778 |
|
|
: {6'o14,3'o2,hzr_a,hzr_b,hzl_a,2'b00,OPREG[15:6], 2'b10,hzl_b,4'h4,OPREG[5:2]};
|
779 |
|
|
// ADJSPi
|
780 |
11 |
ns32kum |
10'b01010_11111 : op2_feld = {6'o11,3'o3,hzr_a,hzr_s,hzl_a,2'b10,OPREG[15:11],5'h00,2'b00,hzl_b,8'h48}; // is a SUBD
|
781 |
9 |
ns32kum |
// ADDR, length field not valid
|
782 |
|
|
10'b0xxxx_x1001 : op2_feld = {6'o61,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6], 2'b00,hzl_b,8'h49};
|
783 |
11 |
ns32kum |
10'b00000_11111 : op2_feld = {6'o71,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // CXPD no Opcode
|
784 |
9 |
ns32kum |
// SETCFG => MOV Befehl , SRC1 is genrated for 32 bit , target is Register temp_h
|
785 |
|
|
10'b1xxxx_xxxxx : op2_feld = {40'b001001_001_000000_111101_00_10_10100_00000_00_011, 8'h76};
|
786 |
|
|
default : op2_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
|
787 |
|
|
endcase
|
788 |
|
|
|
789 |
11 |
ns32kum |
assign op_2byte = (valid_size | setcfg) & ~op2_feld[7]; // it must be for sure shown "Invalid Opcode"
|
790 |
9 |
ns32kum |
|
791 |
|
|
// Special case : the quick opcodes with the exception SPR and LPR
|
792 |
23 |
ns32kum |
assign short_op = ((((~OPREG[5]) | (OPREG[6:4] == 3'b011)) & (OPREG[3:2] == 2'b11) & valid_size) | opt_imme) & PHASE_0;
|
793 |
9 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) short_op_reg <= short_op;
|
794 |
|
|
assign short_def = PHASE_0 ? short_op : short_op_reg; // for the big state machine
|
795 |
11 |
ns32kum |
assign op_sho = (OPREG[6:4] == 3'b011) ? 11'h07A : op_mov; // Special case Scond at Index as Dest. , used only in Phase 0
|
796 |
9 |
ns32kum |
|
797 |
|
|
// 2. special case ACB
|
798 |
|
|
assign acb_op = (OPREG[6:2] == 5'h13) & valid_size;
|
799 |
|
|
always @(posedge BCLK) if (PHASE_0) acb_reg <= acb_op;
|
800 |
|
|
assign acb_flag = PHASE_0 ? acb_op : acb_reg;
|
801 |
11 |
ns32kum |
assign goacb = acb_flag ? 8'h28 : 8'h00; // x'28 = 40 , wait jump at REG operation - short-op special case
|
802 |
9 |
ns32kum |
|
803 |
11 |
ns32kum |
// 3. special case load of PSR and Init-Done opcodes : because of U bit in PSR a restart must follow,
|
804 |
9 |
ns32kum |
// CINV and LMR PTB must wait until Init-Done and than Restart.
|
805 |
|
|
// All variants of LPR and BIC/S have an extra cycle due to TRACE operation
|
806 |
|
|
always @(OPREG)
|
807 |
|
|
casex (OPREG[18:0])
|
808 |
|
|
19'bxxx_xxxxx_1101_110_11_xx : waitop = 9'h14C; // LPRi PSR,...
|
809 |
|
|
19'bxxx_xxxxx_1100_110_11_xx : waitop = 9'h174; // LPRi CFG,...
|
810 |
|
|
19'bxxx_xxxxx_0x10_111_11_xx : waitop = 9'h14C; // BICPSRi/BISPSRi ...
|
811 |
|
|
19'bxxxx_x_0010_xx_0000_1110 : waitop = 9'h174; // SETCFG []
|
812 |
|
|
19'bxxxx_0_0010_xx_0001_1110 : waitop = 9'h174; // LMR - at the end Restart
|
813 |
|
|
19'bxxxx_0_1001_xx_0001_1110 : waitop = 9'h174; // CINV - at the end Restart
|
814 |
|
|
default : waitop = 9'h000;
|
815 |
|
|
endcase
|
816 |
|
|
|
817 |
|
|
assign dowait = waitop[7:0]; // is used in Phase 0 if PSR is loaded from Register
|
818 |
|
|
always @(posedge BCLK) if (PHASE_0) wait_reg <= waitop;
|
819 |
|
|
|
820 |
|
|
// Here 2. and 3. special case are coming together:
|
821 |
|
|
// Phase definition, end over jump for ACB , not used in Phase 0
|
822 |
|
|
assign endea = acb_reg ? 8'h01 : (wait_reg[8] ? wait_reg[7:0] : 8'h00);
|
823 |
|
|
assign diacb = acb_reg ? 4'hE : 4'h0; // load Disp ?
|
824 |
|
|
|
825 |
|
|
// special case ADJSPi : SP=SRC2 always 32 Bit
|
826 |
|
|
always @(posedge BCLK)
|
827 |
|
|
if (PHASE_0) dw_info <= (OPREG[10:2] == 9'b1010_11111);
|
828 |
|
|
else dw_info <= dw_info & ~phase_reg[7]; // for security at ABORT
|
829 |
|
|
|
830 |
|
|
// SETCFG : Flag to transform the Byte Immeadiate operand
|
831 |
|
|
always @(posedge BCLK) if (PHASE_0) op_setcfg <= setcfg;
|
832 |
|
|
always @(posedge BCLK) if (PHASE_0) setcfg_lsb <= OPREG[15];
|
833 |
|
|
|
834 |
|
|
always @(posedge BCLK) if (PHASE_0) jsr_flag <= (OPREG[10:2] == 9'b1100_11111); // JSR : for PUSH
|
835 |
|
|
always @(posedge BCLK) // Bit opcodes to Register and EXT:SRC1 / INS:SRC2
|
836 |
11 |
ns32kum |
if (PHASE_0) bit_reg <= ((OPREG[3] ? ((OPREG[7:6] == 2'd0) ? OPREG[23:22] : OPREG[18:17]) : OPREG[10:9]) == 2'b00);
|
837 |
23 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) exin_cmd <= (~OPREG[10] & (OPREG[6:0] == 7'h2E)) & valid[2];
|
838 |
9 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) extract <= ~OPREG[7];
|
839 |
23 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) inss_op <= (OPREG[13:10] == 4'h2) & (OPREG[7:0] == 8'hCE) & valid[2]; // INSS
|
840 |
9 |
ns32kum |
|
841 |
|
|
// ++++++++++++++ 3 byte opcodes +++++++++++++++++
|
842 |
|
|
|
843 |
|
|
// [47:45] Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
|
844 |
|
|
// [44:42] Destination : like [47:45]
|
845 |
|
|
// [41] long opcode [41:39] only for standard sequenz - not Gruppe 2
|
846 |
|
|
// [40] src2_flag - Source 2 is read
|
847 |
|
|
// [39] dest_flag - a target operand exists
|
848 |
|
|
// [38:33] src1_r Register field, no message about Immediate
|
849 |
|
|
// [32:27] src2_r Register field
|
850 |
|
|
// [26:25] src1_le Length of Source1 - this is used for qword
|
851 |
|
|
// [24:23] src2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE
|
852 |
|
|
// [22:18] src1 field
|
853 |
|
|
// [17:13] src2 field
|
854 |
|
|
// [12:11] op_type 2 Bit for sort of opcode
|
855 |
|
|
// [10] FL : F=1/L=0
|
856 |
|
|
// [9:8] original BWD : B=00/W=01/D=11
|
857 |
|
|
// [7:0] opcode: operation code
|
858 |
|
|
|
859 |
|
|
assign hdx_a = OPREG[7] ? OPREG[8] : OPREG[10];
|
860 |
|
|
assign hdo_a = OPREG[13:10];
|
861 |
|
|
assign hdo_c = {1'b0,OPREG[10],OPREG[7:6]}; // Format 8 opcodes
|
862 |
|
|
assign hdo_d = {6'b0101_00,OPREG[10],1'b0}; // CMPM/S or MOVM/S : 8'h52 or 8'h50
|
863 |
|
|
assign hdo_e = {3'b011,OPREG[10]}; // Special codes for LOGB and SCALB due to DP_OUT datapath
|
864 |
|
|
// Definitions of length
|
865 |
|
|
assign hdl_a = {1'b0,OPREG[9:8]}; // i size, is used in OPER
|
866 |
11 |
ns32kum |
assign hdl_b = (OPREG[9:8] == 2'b11) ? 2'b10 : OPREG[9:8]; // recode length field, is used in ACC field
|
867 |
9 |
ns32kum |
assign hdl_c = OPREG[10:8]; // FL + BWD
|
868 |
|
|
assign hdl_d = {1'b1,~hdx_a}; // length FP
|
869 |
|
|
assign hdl_e = {OPREG[8],2'bxx}; // BWD don't care
|
870 |
11 |
ns32kum |
assign hdl_f = (OPREG[18:17] == 2'b00) ? OPREG[9:8] : {OPREG[8],~(OPREG[9] ^ OPREG[8])}; // exclusiv for DEI
|
871 |
9 |
ns32kum |
assign hdl_g = {(OPREG[9:8] != 2'b00),(OPREG[9:8] == 2'b00)}; // exclusiv for EXT/EXTS base operand
|
872 |
|
|
assign hdl_h = {(OPREG[9:8] != 2'b00),(OPREG[9:8] != 2'b01)}; // exclusiv for CHECK bound operand
|
873 |
|
|
// Register definitions
|
874 |
|
|
assign hdr_a = {3'b000,OPREG[21:19]}; // SRC1 Integer Register
|
875 |
|
|
assign hdr_b = {3'b000,OPREG[16:14]}; // SRC2 Integer Register
|
876 |
|
|
assign hdr_c = hdx_a ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
|
877 |
|
|
assign hdr_d = hdx_a ? {2'b10,OPREG[16:15],1'b0,OPREG[14]} : {2'b10,OPREG[16:14],1'b1};
|
878 |
|
|
assign hdr_e = OPREG[11] ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
|
879 |
|
|
assign hdr_f = OPREG[11] ? {2'b10,OPREG[16:14],1'b1} : {2'b10,OPREG[16:15],1'b0,OPREG[14]};
|
880 |
23 |
ns32kum |
assign hdr_g = {3'b000,OPREG[16:15],~OPREG[14]}; // exclusiv for DEI and MEI
|
881 |
9 |
ns32kum |
assign hdr_m = {3'b001,OPREG[17:15]}; // MMU Register Index 8-15
|
882 |
|
|
|
883 |
|
|
always @(*)
|
884 |
|
|
casex (OPREG[13:3])
|
885 |
11 |
ns32kum |
11'b1000_xx_1100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MULi
|
886 |
|
|
11'b000x_xx_0100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, 2'b00,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // ROTi,ASHi
|
887 |
|
|
11'b0101_xx_0100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, 2'b00,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // LSHi
|
888 |
|
|
11'b1x0x_xx_0100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // NEGi,NOTi,ABSi,COMi
|
889 |
|
|
11'b010x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b01,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiW
|
890 |
|
|
11'b011x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiD
|
891 |
|
|
11'b0001_xx_0110x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b00,hdl_a,4'h8,hdo_c}; // FFSi
|
892 |
9 |
ns32kum |
// Floating Point opcodes
|
893 |
23 |
ns32kum |
11'b000x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_a,hdr_d, hdl_b,hdl_d,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVif
|
894 |
|
|
11'b010x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_e,hdr_f, 2'b11,2'b10,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVLF
|
895 |
|
|
11'b011x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_e,hdr_f, 2'b10,2'b11,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVFL
|
896 |
|
|
11'b10xx_xx_0011x : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // ROUNDi,TRUNCi
|
897 |
|
|
11'b111x_xx_00111 : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // FLOORi
|
898 |
|
|
11'b111x_xx_00110 : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,op_cop}; // SEARCH
|
899 |
|
|
11'b0x00_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // ADDf,SUBf
|
900 |
|
|
11'bxx00_0x_10110 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop}; // Coprocessor
|
901 |
|
|
11'b1000_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // DIVf
|
902 |
|
|
11'b1100_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MULf
|
903 |
|
|
11'b0010_0x_1011x : op3_feld = {6'o11,3'o6,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // CMPf
|
904 |
|
|
11'b0001_0x_10111 : op3_feld = {6'o11,3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MOVf
|
905 |
|
|
11'bx101_0x_10111 : op3_feld = {6'o11,3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // NEGf,ABSf
|
906 |
|
|
11'b001x_11_00111 : op3_feld = {6'o11,3'o1,hdr_a,fsr_r, 2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h92}; // LFSR
|
907 |
|
|
11'b110x_11_00111 : op3_feld = {6'o11,3'o1,fsr_r,hdr_b, 2'b10,2'b10,5'b0,OPREG[18:14],2'b00,3'o3,8'h9C}; // SFSR
|
908 |
9 |
ns32kum |
// MMU opcodes
|
909 |
11 |
ns32kum |
11'b0010_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00, 3'o3,8'h45}; // LMR
|
910 |
|
|
11'b0011_11_0001x : op3_feld = {6'o11,3'o1,hdr_m,hdr_a, 2'b10,2'b10,5'b0,OPREG[23:19],2'b00, 3'o3,8'h45}; // SMR
|
911 |
9 |
ns32kum |
// String opcodes
|
912 |
11 |
ns32kum |
11'b000x_xx_0000x : op3_feld = {6'o11,3'o0,6'hxx,6'hxx, 2'bxx,2'b10,OPREG[23:14], 2'b10,hdl_c,hdo_d}; // MOVS,CMPS
|
913 |
|
|
11'b0011_xx_0000x : op3_feld = {6'o11,3'o0,6'hxx,6'hxx, 2'bxx,2'b10,OPREG[23:14], 2'b10,hdl_c,hdo_d}; // SKPS
|
914 |
9 |
ns32kum |
// Custom opcodes
|
915 |
23 |
ns32kum |
11'bxx01_0x_10110 : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop};
|
916 |
9 |
ns32kum |
// Integer Divisionen : QUOi REMi DIVi MODi and DEIi + MEIi
|
917 |
11 |
ns32kum |
11'b11xx_xx_1100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a};
|
918 |
|
|
11'b10x1_xx_1100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_g, hdl_b,hdl_f,OPREG[23:14],2'b10,hdl_a,4'h7,hdo_a}; // DEI/MEI
|
919 |
9 |
ns32kum |
// Gruppe 2 opcodes
|
920 |
11 |
ns32kum |
11'b0x11_xx_1010x : op3_feld = {6'o77,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,8'h45}; // MOVUS,MOVSU
|
921 |
|
|
11'b000x_xx_1100x : op3_feld = {6'o66,3'o0,hdr_a,hdr_b, 2'bxx,2'b10,OPREG[23:14],2'b10,hdl_c, hdo_d}; // MOVM/CMPM
|
922 |
14 |
ns32kum |
11'b001x_0x_1111x : op3_feld = {6'o11,3'o2,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b10,hdl_e,4'hC,hdo_a}; // DOTf,POLYf
|
923 |
11 |
ns32kum |
11'b0101_0x_1111x : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e}; // LOGB
|
924 |
23 |
ns32kum |
11'b0100_0x_1111x : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e}; // SCALB
|
925 |
11 |
ns32kum |
11'b0011_xx_1100x : op3_feld = {6'o50,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h7,hdo_a}; // EXTS
|
926 |
14 |
ns32kum |
11'bxxx0_xx_1110x : op3_feld = {6'o71,3'o2,hdr_a,hdr_b, hdl_h,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // CHECK
|
927 |
9 |
ns32kum |
11'b0x1x_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
|
928 |
|
|
{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // SBIT/CBIT
|
929 |
|
|
: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
|
930 |
|
|
11'b1110_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
|
931 |
|
|
{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // IBIT
|
932 |
|
|
: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
|
933 |
23 |
ns32kum |
11'b1x11_xx_0100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,3'd0,OPREG[12]}; // ADDP,SUBP
|
934 |
11 |
ns32kum |
11'bxxx0_xx_0010x : op3_feld = {6'o40,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // EXT
|
935 |
|
|
11'bxxx0_xx_1010x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // INS
|
936 |
|
|
11'b0010_xx_1100x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_a}; // INSS
|
937 |
|
|
11'bxxx0_xx_0110x : op3_feld = {6'o61,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // CVTP no Opcode
|
938 |
14 |
ns32kum |
11'bxxx1_xx_0010x : op3_feld = {6'o11,3'o2,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b10, 3'o3,8'h84}; // INDEX
|
939 |
11 |
ns32kum |
// Gruppe 2 opcodes can have dedicated operation codes. Therefore the operation code definition here is "don't care"
|
940 |
|
|
11'b000x_xx_0001x : op3_feld = {6'o70,3'o0,hdr_a,hdr_b, 2'b00,2'b10,OPREG[23:19],5'b0,2'b10,3'o0,8'h45}; // RDVAL+WRVAL
|
941 |
|
|
11'b1001_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h45}; // CINV
|
942 |
9 |
ns32kum |
|
943 |
|
|
default : op3_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
|
944 |
|
|
endcase
|
945 |
|
|
|
946 |
23 |
ns32kum |
assign op_3byte = valid[2] & (OPREG[2:0] == 3'b110) & (op3_feld[7:4] != 4'hA); // valid for all incl. CUSTOM
|
947 |
9 |
ns32kum |
|
948 |
|
|
// +++++++++++++ Evaluation for 2 and 3 byte opcodes ++++++++++++++++++
|
949 |
|
|
|
950 |
|
|
// for one byte opcodes special treatmant neccessary
|
951 |
|
|
assign opc_bits = op_3byte ? op3_feld : op2_feld;
|
952 |
|
|
|
953 |
11 |
ns32kum |
assign op_ok = (op_1byte | op_12byte | op_2byte | op_3byte | exception) & ~stop; // used for computation of USED
|
954 |
9 |
ns32kum |
|
955 |
|
|
always @(posedge BCLK) if (PHASE_0) op_feld_reg <= opc_bits;
|
956 |
|
|
assign op_feld = PHASE_0 ? opc_bits : op_feld_reg; // constant for all following cycles
|
957 |
|
|
|
958 |
|
|
// Evaluation of op_feld :
|
959 |
|
|
|
960 |
|
|
assign atys = op_feld[47:45]; // [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory
|
961 |
|
|
assign atyd = op_feld[44:42]; // [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory
|
962 |
|
|
assign long = op_feld[41];
|
963 |
|
|
assign src2_flag = op_feld[40];
|
964 |
|
|
assign dest_flag = op_feld[39];
|
965 |
|
|
|
966 |
|
|
assign src_1 = {1'b0,op_feld[38:33]};
|
967 |
|
|
assign src_2 = {1'b0,op_feld[32:27]};
|
968 |
|
|
assign src1_le = op_feld[26:25];
|
969 |
|
|
assign src2_le = op_feld[24:23];
|
970 |
11 |
ns32kum |
assign acc1 = (op_feld[22:21] != 2'b00) | atys[1]; // external access Source1 or "addr" : Reg => (Reg)
|
971 |
|
|
assign acc2 = (op_feld[17:16] != 2'b00) | atyd[1]; // external access Source2 or "addr" : Reg => (Reg)
|
972 |
9 |
ns32kum |
assign wlor = dest_flag & ~acc2;
|
973 |
11 |
ns32kum |
assign idx_n = {1'b0,(op_feld[22:20] == 3'b111)} + {1'b0,(op_feld[17:15] == 3'b111)}; // Index : 0,1 or 2
|
974 |
9 |
ns32kum |
assign idx = (idx_n != 2'b00); // Index is active
|
975 |
|
|
assign n_idx = idx_n - 2'b01;
|
976 |
|
|
|
977 |
|
|
// The field otype is used only in Phase 0
|
978 |
11 |
ns32kum |
assign otype = exception ? 2'b11 : ((op_1byte | op_12byte) ? 2'b01 : opc_bits[12:11]); // string opcodes use code 2'b10
|
979 |
9 |
ns32kum |
|
980 |
|
|
assign opera = op_feld[10:0];
|
981 |
|
|
|
982 |
|
|
assign dest_r = src_2[5:0];
|
983 |
|
|
assign dest_rl = {dest_r[5:1],1'b0};
|
984 |
|
|
|
985 |
23 |
ns32kum |
// ++++++++++++++++++++++++++++ Immediate Optimization +++++++++++++++++++++++++++++++++++
|
986 |
|
|
|
987 |
|
|
// 3 Byte Immediate
|
988 |
|
|
assign opt_imme = (valid[2] & (OPREG[1:0] == 2'd0) & (OPREG[15:11] == 5'b10100) &
|
989 |
|
|
// ADD,ADDC,SUB,SUBC,BIC,OR,AND,XOR CMP MOV
|
990 |
|
|
( ((OPREG[10:8] != 3'b111) & (~OPREG[2] | (OPREG[5:2] == 4'h1) | (OPREG[5:2] == 4'h5))) // not ADDR und TBIT
|
991 |
|
|
|((OPREG[6:2] == 5'b11111) & (OPREG[8:7] == 2'b10) & (OPREG[10:9] != 2'b11)))) // BICPSR,BISPSR,ADJSP and ~CASE
|
992 |
|
|
// 4 not Scaled Index Immediate
|
993 |
|
|
| (ANZ_VAL[2] & (OPREG[18:16] != 3'b111) & (OPREG[23:19] == 5'b10100) &
|
994 |
|
|
( ((OPREG[7:0] == 8'h4E) & ~OPREG[13] & ~OPREG[11]) // ROT,ASH,LSH but not NEG,NOT,ABS,COM
|
995 |
|
|
|((OPREG[7:0] == 8'hCE) & (OPREG[13:12] == 2'b01) & (OPREG[9:8] == 2'd0)))); // MOVX/ZBi
|
996 |
|
|
|
997 |
|
|
assign opti_byte = (OPREG[1:0] == 2'b10) ? OPREG[31:24] : OPREG[23:16];
|
998 |
|
|
|
999 |
9 |
ns32kum |
// +++++++++++++++++++++++++ Coprocessor operations field ++++++++++++++++++++++++++++++
|
1000 |
|
|
|
1001 |
|
|
always @(posedge BCLK) if (PHASE_0) COP_OP <= OPREG[23:0];
|
1002 |
|
|
|
1003 |
|
|
// +++++++++++++++++++++++++ Special signals for LMR and CINV ++++++++++++++++++++++++++
|
1004 |
|
|
// op_lmr is constant = parameter
|
1005 |
|
|
|
1006 |
|
|
assign STOP_IC = (phase_reg == 8'h74) | (phase_reg == 8'h75);
|
1007 |
|
|
|
1008 |
|
|
// CINV uses Register x'30 - x'37 : CINV = 110... , LMR = 001... otherwise CFG
|
1009 |
11 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) lmrreg <= op_3byte ? {{2{OPREG[13]}},~OPREG[13],OPREG[17:15]} : 6'h1C;
|
1010 |
9 |
ns32kum |
|
1011 |
11 |
ns32kum |
always @(posedge BCLK) no_init <= (lmrreg[5:4] == 2'b00) & (lmrreg[3:1] != 3'b110); // LMR waits for INIT at PTB0/1
|
1012 |
9 |
ns32kum |
// a_ivar = "Addresse IVAR0/1"
|
1013 |
11 |
ns32kum |
always @(posedge BCLK) a_ivar <= STOP_IC; // Phase 74 & 75, is used at INFO_AU together with IC_READ
|
1014 |
9 |
ns32kum |
|
1015 |
|
|
// CINV detection for IC_CACHE
|
1016 |
|
|
always @(posedge BCLK)
|
1017 |
|
|
if (PHASE_0) cinv_flag <= OPREG[13] & (OPREG[7:0] == 8'h1E);
|
1018 |
|
|
else cinv_flag <= cinv_flag & ~phase_reg[7]; // reset at exception
|
1019 |
|
|
|
1020 |
|
|
assign ENA_HK = ~(cinv_flag & STOP_IC); // always "1", if CINV then "0"
|
1021 |
|
|
|
1022 |
|
|
// +++++++++++++++++++++++++ USER flag for MOVUS & MOVSU ++++++++++++++++++++++++
|
1023 |
|
|
|
1024 |
|
|
always @(posedge BCLK)
|
1025 |
|
|
if (PHASE_0) m_ussu <= (~OPREG[13] & (OPREG[11:10] == 2'b11) & (OPREG[7:0] == 8'hAE));
|
1026 |
|
|
else m_ussu <= m_ussu & ~phase_reg[7]; // reset at exception
|
1027 |
|
|
|
1028 |
|
|
always @(posedge BCLK) if (PHASE_0) m_usel <= OPREG[12];
|
1029 |
|
|
|
1030 |
|
|
// +++++++++++++++++++++++++ USER flag for RDVAL & WRVAL ++++++++++++++++++++++++
|
1031 |
|
|
|
1032 |
|
|
always @(posedge BCLK)
|
1033 |
|
|
if (PHASE_0) rwval_flag <= (OPREG[13:11] == 3'd0) & (OPREG[7:0] == 8'h1E);
|
1034 |
|
|
else rwval_flag <= rwval_flag & ~phase_reg[7]; // reset at exception
|
1035 |
|
|
|
1036 |
|
|
always @(posedge BCLK) if (PHASE_0) wrval_flag <= OPREG[10]; // Difference RDVAL=0 and WRVAL=1
|
1037 |
|
|
|
1038 |
|
|
// +++++++++++++++++++++++++ Flags for CBIT/I+SBIT/I+IBIT +++++++++++++++++++++++
|
1039 |
|
|
|
1040 |
11 |
ns32kum |
assign rw_bit = (op_feld_reg[7:4] == 4'd6) & ((~op_feld_reg[3] & op_feld_reg[1]) | (op_feld_reg[3:0] == 4'hE));
|
1041 |
9 |
ns32kum |
assign op_ilo = rw_bit & op_feld_reg[0]; // Interlocked : CBITI and SBITI
|
1042 |
|
|
|
1043 |
|
|
// +++++++++++++++++++++++++++++ Operations for String processing +++++++++++++++++
|
1044 |
|
|
// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
|
1045 |
|
|
|
1046 |
11 |
ns32kum |
assign st_src = {STRING[1:0],5'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1000}; // [15] = BACKWARD
|
1047 |
|
|
assign st_src2 = {STRING[1:0],5'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1011}; // Reuse EA
|
1048 |
|
|
assign st_dest = {STRING[1:0],5'b0110_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1011}; // Reuse EA
|
1049 |
|
|
assign st_trde = {2'b00, 5'b0110_0, op_feld_reg[15], 2'b00, 9'b0_0000_1000}; // after Translate to Dest
|
1050 |
|
|
assign st_trs2 = {STRING[1:0],5'b1010_0, op_feld_reg[15], STRING[1:0],9'b0_0000_1000}; // after Match to SRC2
|
1051 |
9 |
ns32kum |
assign st_len = {STRING[1:0],17'b0000_0000_0_0000_0000}; // length important for qw_flag
|
1052 |
|
|
|
1053 |
|
|
// Signals of DETOIP go to I_PFAD
|
1054 |
11 |
ns32kum |
always @(posedge BCLK) if (PHASE_0) kill_opt <= ~OPREG[7] & (OPREG[17:15] != 3'b000); // watch difference of MOVM and MOVS
|
1055 |
9 |
ns32kum |
assign ph_match = (phase_reg[7:4] == 4'hD) & (phase_reg[2:0] == 3'd7); // Phase D7 and DF
|
1056 |
|
|
|
1057 |
|
|
assign op_str = {op_feld_reg[10:8],6'b0101_00,op_feld_reg[1],1'b1}; // Opcode 8'h51 or 8'h53;
|
1058 |
|
|
assign op_scp = {op_feld_reg[10:8],8'h41}; // normal CMPi
|
1059 |
|
|
assign ph_str = {4'hC,op_feld_reg[1],3'b001}; // Phase 8'hC1 (MOVS/M) or 8'hC9 (CMPS/M)
|
1060 |
|
|
|
1061 |
11 |
ns32kum |
always @(posedge BCLK) kurz_st <= (phase_reg == 8'h65) | (kurz_st & ~PHASE_0); // Flag for MOVM/CMPM
|
1062 |
|
|
always @(posedge BCLK) if (PHASE_0) cmps_flag <= ~OPREG[7] & (OPREG[11:10] == 2'b01); // Flag for CMPS
|
1063 |
|
|
always @(posedge BCLK) if (PHASE_0) skps_flag <= ~OPREG[7] & (OPREG[11:10] == 2'b11); // Flag for SKPS
|
1064 |
|
|
always @(posedge BCLK) if (PHASE_0) mt_flag <= ~OPREG[7] & (OPREG[17] | OPREG[15]); // Flag for Match and Translate
|
1065 |
9 |
ns32kum |
|
1066 |
|
|
assign wstr0 = {{4{kurz_st}},2'b00};
|
1067 |
|
|
assign wstr1 = {{4{kurz_st}},2'b01};
|
1068 |
|
|
assign wstr2 = {{4{kurz_st}},2'b10};
|
1069 |
|
|
assign rstr0 = {1'b0,wstr0};
|
1070 |
|
|
assign rstr1 = {1'b0,wstr1};
|
1071 |
|
|
assign rstr2 = {1'b0,wstr2};
|
1072 |
|
|
|
1073 |
|
|
// +++++++++++++++++++++++++++++++++++ Index processing +++++++++++++++++++++++++++++++++++++++++
|
1074 |
|
|
|
1075 |
|
|
assign phase_idx = (phase_reg == 8'h02) | (phase_reg == 8'h50);
|
1076 |
|
|
|
1077 |
|
|
assign idx_bytes = idx_1[2] ? OPREG[15:0] : {OPREG[7:0],OPREG[7:0]}; // here last access of OPREG
|
1078 |
|
|
always @(posedge BCLK) if (phase_idx) idx_reg <= idx_bytes;
|
1079 |
|
|
assign idx_feld = (phase_idx) ? idx_bytes : idx_reg;
|
1080 |
|
|
|
1081 |
|
|
// +++++++++++++++++++++++++++++++++++ The big state machine ++++++++++++++++++++++++++++++++++++
|
1082 |
|
|
|
1083 |
|
|
// Hints :
|
1084 |
|
|
// 1. At short-op SRC1 is out of memory to use TEMP
|
1085 |
|
|
// 2. At SRC2 rmw suppresed TOS and changed it to (SP)
|
1086 |
|
|
// 3. The Long-operation path takes the dest_r address to write if WR_REG activ
|
1087 |
11 |
ns32kum |
// 4. It is ok, that an extra cycle for the read of the index registers is needed - then data could be written ins Out register
|
1088 |
9 |
ns32kum |
|
1089 |
|
|
// Source 1
|
1090 |
|
|
|
1091 |
|
|
assign idx_1 = {1'b0,(op_feld[22:20] == 3'b111),op_feld[19:18]};
|
1092 |
|
|
assign src1_addr = idx_1[2] ? idx_feld[7:3] : op_feld[22:18];
|
1093 |
|
|
assign stack = {1'b0,stack_sel[s_user],3'b110,s_user,1'b1};
|
1094 |
|
|
assign usp_1 = src1_addr[0] ? stack : {5'b0_0110,src1_addr[1:0]};
|
1095 |
|
|
assign src_1l = {src_1[6:1],1'b0};
|
1096 |
|
|
assign pop_1 = {2'b00,src1_le,9'h108}; // SP update, DISP=0 and POST
|
1097 |
11 |
ns32kum |
assign mpoi_1 = (src1_addr[4:2] == 3'b100) | (src1_addr == 5'h16); // Pointer in memory always DWord
|
1098 |
9 |
ns32kum |
assign auop_s = atys[0] ? 4'b1011 : 4'b0010; // Only make effective address ?
|
1099 |
14 |
ns32kum |
assign src1_tos = (op_feld[22:18] == 5'h17) & ~atys[2] ? 2'b11 : 2'b00; // Source 1 is true TOS
|
1100 |
9 |
ns32kum |
|
1101 |
|
|
// Nextfield : 11=DISP read
|
1102 |
|
|
// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
|
1103 |
|
|
always @(*)
|
1104 |
|
|
casex (src1_addr) // RWLF IDX ADDR_F NEUP SRC_REG NEXT
|
1105 |
11 |
ns32kum |
// Special case which is only valid at INDEX or "addr" : REG -> ADDR , DISP=0 : starts immediate at read
|
1106 |
9 |
ns32kum |
5'b00xxx : gen_src1 = {auop_s, idx_1,9'h000,8'h07,4'h0,src1_addr[2:0],3'b000,atys[0]};
|
1107 |
|
|
// Register relativ : 0(R0)
|
1108 |
|
|
5'b01xxx : gen_src1 = {auop_s, idx_1,9'h000,8'h07,4'h0,src1_addr[2:0],3'b111,atys[0]};
|
1109 |
|
|
// Memory relativ : 0(0(SB))
|
1110 |
11 |
ns32kum |
5'b100xx : gen_src1 = {4'b1011,4'h0, 9'h000,8'h06,usp_1, 4'b1111}; // 1. access always full
|
1111 |
9 |
ns32kum |
// Immediate
|
1112 |
|
|
5'b10100 : gen_src1 = (src1_le == 2'b11) ?
|
1113 |
|
|
{4'h0, 4'h0, 9'h000,8'h0B,src_x, 1'b1,2'b10,1'b0} // load in DWord pieces
|
1114 |
|
|
: {4'h0, 4'h0, 9'h000,8'h07,src_x, 1'b1,src1_le,1'b0};
|
1115 |
11 |
ns32kum |
5'b10101 : gen_src1 = {auop_s, idx_1,9'h002,8'h07,src_x, 3'b111,atys[0]}; // Absolut Addressing
|
1116 |
|
|
5'b10110 : gen_src1 = {4'b1011,4'h0, 9'h014,8'h05,7'h1F, 4'b0001}; // External with MOD Register +4
|
1117 |
9 |
ns32kum |
5'b10111 : gen_src1 = (idx_1[2] | atys[2]) ? // Access class "addr" ?
|
1118 |
|
|
{auop_s, idx_1,9'h000,8'h07,stack, 3'b000,atys[0]} // 0(SP) : no TOS flag
|
1119 |
|
|
: {4'b1011,pop_1, 8'h07,stack, 4'b0001}; // TOS
|
1120 |
|
|
// Memory Space : 0(SB)
|
1121 |
11 |
ns32kum |
5'b110x0 : gen_src1 = {auop_s, idx_1,9'h000,8'h07,5'b0_0110,src1_addr[1:0],3'b111,atys[0]}; // SB+FP
|
1122 |
9 |
ns32kum |
5'b11001 : gen_src1 = {auop_s, idx_1,9'h000,8'h07,stack, 3'b111,atys[0]}; // SP
|
1123 |
|
|
5'b11011 : gen_src1 = {auop_s, idx_1,9'h001,8'h07,src_x, 3'b111,atys[0]}; // PC relativ
|
1124 |
|
|
default : gen_src1 = 36'hx_xxxx_xxxx; // don't care
|
1125 |
|
|
endcase
|
1126 |
|
|
|
1127 |
|
|
assign adrd1 = {(mpoi_1 ? 2'b10 : src1_le),gen_src1[35:19]}; // Addressfield : 19 Bits
|
1128 |
|
|
assign phrd1 = gen_src1[18:11]; // next phase
|
1129 |
|
|
assign rega1 = gen_src1[10:4]; // Source 1 Register
|
1130 |
|
|
assign irrw1 = {4'b0,idx_feld[2:0]}; // Index-Register
|
1131 |
|
|
assign nxrd1 = gen_src1[3:0]; // Memory/Disp/Immediate operation
|
1132 |
|
|
assign exr11 = {2'b10 ,4'b1011,4'h0 ,9'h080}; // 2. access external with Mem.-Pointer + 4* Disp
|
1133 |
|
|
assign exr12 = {src1_le,auop_s,idx_1,9'h000}; // for Memory Relative and EXT in last step
|
1134 |
|
|
|
1135 |
|
|
// Source 2 resp. Destination
|
1136 |
|
|
|
1137 |
|
|
assign rmw = src2_flag & dest_flag;
|
1138 |
|
|
assign idx_2 = {1'b0,(op_feld[17:15] == 3'b111),op_feld[14:13]}; // 4 bits
|
1139 |
|
|
assign src2_addr = idx_2[2] ? idx_feld[15:11] : op_feld[17:13];
|
1140 |
|
|
assign usp_2 = src2_addr[0] ? stack : {5'b0_0110,src2_addr[1:0]};
|
1141 |
|
|
assign src_2l = {src_2[6:1],1'b0};
|
1142 |
11 |
ns32kum |
assign mpoi_2 = (src2_addr[4:2] == 3'b100) | (src2_addr == 5'h16); // Pointer in memory always DWord
|
1143 |
9 |
ns32kum |
assign auop_d = atyd[0] ? 4'b1011 : 4'b0010; // Only make effective address ?
|
1144 |
|
|
|
1145 |
|
|
// The next assessment processes TOS separated for PUSH and POP
|
1146 |
|
|
assign tos_oper = src2_flag ?
|
1147 |
11 |
ns32kum |
{2'b00,atyd[0],2'b01,atyd[0],2'b00,src2_le,7'b1_0000_10, src1_tos,4'h7,stack,3'b0,atyd[0]} // POP
|
1148 |
|
|
: {1'b0,atyd[0],3'b001,atyd[0],4'h0, 1'b1,2'b10,src2_le,2'b0,src1_tos,4'h7,stack,3'b0,atyd[0]}; // PUSH
|
1149 |
9 |
ns32kum |
|
1150 |
|
|
// Nextfield : 11=DISP read
|
1151 |
|
|
// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
|
1152 |
|
|
always @(*)
|
1153 |
|
|
casex (src2_addr) // RW:W RW:R LF IDX ADDR_F NEUP SRC_REG NEXT
|
1154 |
11 |
ns32kum |
// Special case which is only valid at INDEX or "addr" : REG -> ADDR , DISP=0 : starts immediate at read
|
1155 |
|
|
5'b00xxx : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h000,4'h7,4'h0,src2_addr[2:0],3'b000,atyd[0]};
|
1156 |
9 |
ns32kum |
// Register relativ : 0(R0)
|
1157 |
11 |
ns32kum |
5'b01xxx : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h000,4'h7,4'h0,src2_addr[2:0],3'b111,atyd[0]};
|
1158 |
9 |
ns32kum |
// Memory relativ : 0(0(SB))
|
1159 |
11 |
ns32kum |
5'b100xx : gen_src2 = {2'b10,2'b10,2'b11,4'h0, 9'h000,4'h6,usp_2, 4'b1111}; // 1. access always full
|
1160 |
9 |
ns32kum |
// Immediate
|
1161 |
|
|
5'b10100 : gen_src2 = (src2_le == 2'b11) ?
|
1162 |
|
|
{2'b00,2'b00,2'b00,4'h0, 9'h000,4'hB,src_x, 1'b1,2'b10,1'b0} // load in DWord pieces
|
1163 |
|
|
: {2'b00,2'b00,2'b00,4'h0, 9'h000,4'h7,src_x, 1'b1,src2_le,1'b0};
|
1164 |
11 |
ns32kum |
5'b10101 : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h002,4'h7,src_x, 3'b111,atyd[0]}; // Absolut with special coding
|
1165 |
|
|
5'b10110 : gen_src2 = {2'b10,2'b10,2'b11,4'h0, 9'h014,4'h5,7'h1F, 4'b0001}; // External with MOD Register +4
|
1166 |
9 |
ns32kum |
5'b10111 : gen_src2 = (idx_2[2] | rmw | atyd[2]) ?
|
1167 |
11 |
ns32kum |
{1'b0,atyd[0],auop_d, idx_2,7'b0_0000_00,src1_tos,4'h7,stack, 3'b000,atyd[0]} // 0(SP) : TOS + DISP=0
|
1168 |
9 |
ns32kum |
: tos_oper; // TOS : 2 cases for PUSH and POP
|
1169 |
|
|
// Memory Space
|
1170 |
11 |
ns32kum |
5'b110x0 : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h000,4'h7,5'b0_0110,src2_addr[1:0],3'b111,atyd[0]};
|
1171 |
9 |
ns32kum |
5'b11001 : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h000,4'h7,stack, 3'b111,atyd[0]};
|
1172 |
11 |
ns32kum |
5'b11011 : gen_src2 = {1'b0,atyd[0],auop_d, idx_2,9'h001,4'h7,src_x, 3'b111,atyd[0]}; // PC relativ
|
1173 |
9 |
ns32kum |
default : gen_src2 = 34'hx_xxxx_xxxx; // don't care
|
1174 |
|
|
endcase
|
1175 |
|
|
|
1176 |
|
|
assign adrd2 = {(mpoi_2 ? 2'b10 : src2_le),gen_src2[31:15]};
|
1177 |
|
|
assign adwr2 = {(mpoi_2 ? 2'b10 : src2_le),gen_src2[33:32],gen_src2[29:15]};
|
1178 |
|
|
assign phrd2 = {4'h1,gen_src2[14:11]}; // Phase for Read Source 2
|
1179 |
|
|
assign phwr2 = {4'h2,gen_src2[14:11]}; // Phase for Write Destination
|
1180 |
|
|
assign rega2 = gen_src2[10:4];
|
1181 |
|
|
assign nxrw2 = gen_src2[3:0];
|
1182 |
|
|
assign irrw2 = {4'b0,idx_feld[10:8]};
|
1183 |
|
|
assign re_wr = {src2_le,4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw
|
1184 |
11 |
ns32kum |
assign exr22 = {src2_le,atyd[0],1'b0,1'b1,atyd[0],idx_2,9'h000}; // for Memory Relative and EXT in last step
|
1185 |
|
|
assign exw22 = {src2_le,1'b0,atyd[0],1'b1,atyd[0],idx_2,9'h000}; // for Memory Relative and EXT in last step
|
1186 |
9 |
ns32kum |
|
1187 |
|
|
// Special case :
|
1188 |
|
|
|
1189 |
|
|
assign quei1 = acc1 ? imme : src_1l; // 8B passing either from register or from extern
|
1190 |
|
|
// 8B is requested from both operands but only to certain times
|
1191 |
|
|
assign qword = (phase_reg[7:4] != 4'h0) ? (src2_le == 2'b11) : (src1_le == 2'b11);
|
1192 |
|
|
assign quet1 = acc1 ? temp_h : src_1; // select source during calculation
|
1193 |
|
|
|
1194 |
|
|
// Output data of state machine
|
1195 |
|
|
// LOAD if PULS if simple
|
1196 |
|
|
// NEXT -> ENABLE ENABLE out
|
1197 |
|
|
// [66:48] 19 ADDR : X ; Op-length REUSE RD/WR etc.
|
1198 |
|
|
// [47:40] 8 new phase X
|
1199 |
|
|
// [39:33] 7 SRC1 X
|
1200 |
|
|
// [32:26] 7 SRC2 X
|
1201 |
|
|
// [25] 1 WREN X
|
1202 |
|
|
// [24:19] 6 DEST X
|
1203 |
|
|
// [18:8] 11 OPER X
|
1204 |
|
|
// [7:6] 2 START X
|
1205 |
|
|
// [5:4] 2 LD_OUT X
|
1206 |
|
|
// [3] 1 ID Load X
|
1207 |
|
|
// [2:1] 2 ID Type X ; 0 = DISP
|
1208 |
|
|
// [0] 1 MEM Access X
|
1209 |
|
|
|
1210 |
|
|
// State acc2-src2_flag-dest_flag
|
1211 |
|
|
// no SRC2 x 0 x
|
1212 |
|
|
// SRC2=REG 0 1 0 ; CMP+TBIT
|
1213 |
|
|
// SRC2=REG 0 1 1 ; all else
|
1214 |
|
|
// SRC2=MEM 1 1 0 ; CMP+TBIT
|
1215 |
|
|
// SRC2=MEM 1 1 1 ; all else
|
1216 |
|
|
|
1217 |
|
|
// Input data for state machine
|
1218 |
|
|
|
1219 |
|
|
// 8 phase_reg : phase of state machine
|
1220 |
|
|
// 2 otype : Opcode type
|
1221 |
|
|
|
1222 |
|
|
// 1 idx : Index is available : 1 or 2 , only PHASE_0
|
1223 |
|
|
// 1 short_op : short opcodes like ADDQ
|
1224 |
|
|
// 1 long : "long" opcode
|
1225 |
|
|
// 1 qword : 8B access at Source (Exception DEI+MEI)
|
1226 |
|
|
|
1227 |
|
|
// 1 acc1 : Reg/Extern SRC1
|
1228 |
|
|
// 1 acc2 : Reg/Extern SRC2
|
1229 |
|
|
// 1 src2_flag : the 2. operand is being read
|
1230 |
|
|
// 1 dest_flag : there is a target operand : only CMP and TBIT have none
|
1231 |
|
|
|
1232 |
|
|
assign phase_ein = abbruch ? 8'h00 : phase_reg;
|
1233 |
|
|
|
1234 |
|
|
always @(*) // "_" "_"
|
1235 |
|
|
casex ({phase_ein,otype, idx,short_def,long,qword, acc1,acc2,src2_flag,dest_flag})
|
1236 |
11 |
ns32kum |
{8'h00,10'b00_1xxx_xxxx}: // Index must be loaded : phase 2 : in any case load TEMP for Short-Op and generate LD_OUT
|
1237 |
9 |
ns32kum |
new_op = short_op ? // START LD_OUT
|
1238 |
|
|
{addr_nop,8'h02, imme, src_x, 1'b1,temp_h, op_sho, 2'b00,2'b10, 1'b1,n_idx,1'b0}
|
1239 |
|
|
: {addr_nop,8'h02, src_1,src_1l,1'b0,dest_x, opera, 2'b00,~src2_flag,2'b1_1,n_idx,1'b0};
|
1240 |
|
|
{8'h00,10'b00_01xx_x0xx}: // Short-Op to register, LD_OUT because of CMPQ
|
1241 |
|
|
new_op = {addr_nop,goacb, imme, src_2,dest_flag,dest_r, opera, 2'b00,2'b10, 4'h0};
|
1242 |
|
|
{8'h00,10'b00_01xx_x11x}: // Short-Op : external operand read : SRC2 ! Data in TEMP ! Here no Index
|
1243 |
|
|
new_op = {adrd2, phrd2, imme, rega2, 1'b1,temp_h, op_mov, 2'b00,2'b00, nxrw2};
|
1244 |
|
|
{8'h00,10'b00_01xx_x10x}: // MOVQ to Mem
|
1245 |
|
|
new_op = {adwr2, phwr2, imme, rega2, 1'b0,dest_x, opera, 2'b00,2'b10, nxrw2};
|
1246 |
|
|
{8'h00,10'b00_0000_00xx}: // simple register operation : dest_flag controls WREN, LD_OUT for CMP
|
1247 |
|
|
new_op = {addr_nop,dowait,src_1,src_2, dest_flag,dest_r,opera, 2'b00,2'b10, 4'h0};
|
1248 |
|
|
{8'h00,10'b00_0001_00xx}: // "simple" Reg-Op of 8B, phase 8 after 2. DWord , not via LONG-path
|
1249 |
|
|
new_op = {addr_nop,8'h08, src_1,src_x, 1'b1,dest_r, opera, 2'b00,2'b00, 4'h0};
|
1250 |
|
|
{8'h00,10'b00_0010_00xx}: // long register operation i.e. DIV - phase 31
|
1251 |
|
|
new_op = {addr_nop,8'h1F, src_1,src_2, wlor,dest_r, opera, 2'b11,2'b00, 4'h0};
|
1252 |
|
|
{8'h00,10'b00_0011_001x}: // long register operation with QWORD - phase 26 then wait
|
1253 |
|
|
new_op = {addr_nop,8'h1A, src_1,src_2, 1'b0,dest_r, opera, 2'b01,2'b00, 4'h0};
|
1254 |
|
|
{8'h00,10'b00_00xx_1xxx}: // Source 1 in memory - first to read , here no Index
|
1255 |
|
|
new_op = {adrd1, phrd1, src_x,rega1, 1'b0,dest_x, opera, 2'b00,2'b00, nxrd1};
|
1256 |
|
|
{8'h00,10'b00_00xx_011x}: // Source 2 in memory - first to read (Source 1 in register)
|
1257 |
|
|
new_op = {adrd2, phrd2, src_x,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1258 |
|
|
{8'h00,10'b00_0000_0101}: // Source 1 store in Dest : "pass through" for MOV,NEG,ABS
|
1259 |
|
|
new_op = {adwr2, phwr2, src_1,rega2, 1'b0,dest_x, opera, 2'b00,2'b10, nxrw2};
|
1260 |
11 |
ns32kum |
{8'h00,10'b00_0001_0101}: // Source 1 store in Dest : "pass through" for MOV,NEG,ABS for Long operands
|
1261 |
|
|
new_op = //(op_feld[17:13] == 5'h17) ? // TOS : special case , first 8B out of Reg and then read SP
|
1262 |
9 |
ns32kum |
{addr_nop,8'h1C, src_1,src_1l,1'b0,dest_x, opera, 2'b00,2'b11, 4'h0};
|
1263 |
|
|
{8'h00,10'b00_0010_0101}: // SRC1 -> DEST with short operands
|
1264 |
|
|
new_op = {addr_nop,8'h1F, src_1,src_x, 1'b0,dest_r, opera, 2'b11,2'b00, 4'h0};
|
1265 |
|
|
{8'h00,10'b00_0011_0x01}: // SRC1 -> DEST i.e. ROUNDLi
|
1266 |
|
|
new_op = {addr_nop,8'h1F, src_1,src_1l,wlor,dest_r, opera, 2'b11,2'b00, 4'h0};
|
1267 |
|
|
|
1268 |
|
|
// Phase 2 : after read of Index nearly everything is repeated from PHASE_0
|
1269 |
|
|
{8'h02,10'bxx_x1xx_x11x}: // Short-Op : external operand read
|
1270 |
|
|
new_op = {adrd2, phrd2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1271 |
|
|
{8'h02,10'bxx_x1xx_x101}: // MOVQ to Mem, data is in Out-Register
|
1272 |
|
|
new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1273 |
|
|
{8'h02,10'bxx_x0xx_1xxx}: // Source 1 in memory - first to read
|
1274 |
|
|
new_op = {adrd1, phrd1, irrw1,rega1, 1'b0,dest_x, opera, 2'b00,2'b00, nxrd1};
|
1275 |
|
|
{8'h02,10'bxx_x0xx_011x}: // Source 2 in memory - first to read
|
1276 |
|
|
new_op = {adrd2, phrd2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1277 |
11 |
ns32kum |
{8'h02,10'bxx_x00x_0101}: // Source 1 store in Dest : "pass through" , data is already in Out-Register
|
1278 |
9 |
ns32kum |
new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1279 |
|
|
{8'h02,10'bxx_x010_0101}: // SRC1 -> DEST with short operands
|
1280 |
|
|
new_op = {addr_nop,8'h1F, src_1,src_x, 1'b0,dest_x, opera, 2'b11,2'b00, 4'h0};
|
1281 |
|
|
{8'h02,10'bxx_x011_0101}: // SRC1 -> DEST i.e. ROUNDLi
|
1282 |
|
|
new_op = {addr_nop,8'h1F, src_1,src_1l,1'b0,dest_x, opera, 2'b11,2'b00, 4'h0};
|
1283 |
|
|
|
1284 |
|
|
// +++++++++++++++++ SRC1 operand loading +++++++++++++++++++
|
1285 |
|
|
|
1286 |
|
|
// Phase 5 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
|
1287 |
|
|
// next phase fix : 6
|
1288 |
11 |
ns32kum |
{8'h05,10'bxx_xxxx_xxxx}: new_op = {exr11, 8'h06, src_x,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
|
1289 |
9 |
ns32kum |
// Phase 6 : Memory-Pointer for Memory Relative and last access External
|
1290 |
|
|
// next phase fix : 7 , add Index
|
1291 |
11 |
ns32kum |
{8'h06,10'bxx_xxxx_xxxx}: new_op = {exr12, 8'h07, irrw1,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 3'b111,atys[0]};
|
1292 |
9 |
ns32kum |
|
1293 |
|
|
// Phase 7 : wait for final data , direct from PHASE_0 if TOS without Index
|
1294 |
|
|
// next phase : if 8B data phase 8 is neccessary
|
1295 |
|
|
// if SRC2=REG execution started (otherwise store data in TEMP) and PHASE_0
|
1296 |
11 |
ns32kum |
{8'h07,10'bxx_xx00_x0xx}: // into Register , short operation execution , but LD_OUT for PSR Update ! dest_flag => WREN
|
1297 |
9 |
ns32kum |
new_op = {addr_nop,endea, imme, src_2, dest_flag,dest_r,opera, 2'b00,2'b10, diacb};
|
1298 |
|
|
{8'h07,10'bxx_xx01_x0xx}: // into Reg but with a step om between for ABSL etc. : phase 8
|
1299 |
|
|
new_op = {addr_nop,8'h08, imme, src_x, 1'b1,dest_r, opera, 2'b00,2'b00, 4'h0};
|
1300 |
|
|
{8'h07,10'bxx_xx10_x0xx}: // execute long operation , wait in phase 31
|
1301 |
|
|
new_op = {addr_nop,8'h1F, imme, src_2, wlor,dest_r, opera, 2'b11,2'b00, 4'h0};
|
1302 |
11 |
ns32kum |
{8'h07,10'bxx_xx11_xx0x}: // execute long operation : 2. operand only Dest , load LSD , phase 24 , wait in phase 31
|
1303 |
9 |
ns32kum |
new_op = {addr_nop,8'h18, imme, src_x, 1'b1,temp_l, op_mov, 2'b01,2'b00, 4'h0};
|
1304 |
|
|
{8'h07,10'bxx_xx11_x01x}: // lange Operation ausfuehren , LSD laden , phase 25 , warten in phase 31
|
1305 |
|
|
new_op = {addr_nop,8'h19, imme, src_2, 1'b0,dest_r, opera, 2'b01,2'b00, 4'h0};
|
1306 |
|
|
{8'h07,10'bxx_xxx0_x11x}: // Data into TEMP , read 2. operand , is there Index ? Yes -> phase 15
|
1307 |
|
|
new_op = idx_2[2] ?
|
1308 |
|
|
{addr_nop,8'h0F, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0}
|
1309 |
|
|
: {adrd2, phrd2, imme, rega2, 1'b1,temp_h, op_mov, 2'b00,2'b00, nxrw2};
|
1310 |
11 |
ns32kum |
{8'h07,10'bxx_xxx1_x11x}: // 8B data in TEMP , step in between then 2. Op read : phase 10 - can only be "long" operation
|
1311 |
9 |
ns32kum |
new_op = {addr_nop,8'h0A, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0};
|
1312 |
|
|
{8'h07,10'bxx_xx00_x101}: // something like ABSi , execute and store (LD_OUT)
|
1313 |
|
|
new_op = idx_2[2] ?
|
1314 |
|
|
{addr_nop,8'h10, imme, src_x, 1'b0,dest_x, opera, 2'b00,2'b10, 4'h0}
|
1315 |
|
|
: {adwr2, phwr2, imme, rega2, 1'b0,dest_x, opera, 2'b00,2'b10, nxrw2};
|
1316 |
11 |
ns32kum |
{8'h07,10'bxx_xx01_x101}: // ABS etc. : LSD data over SRC2 in 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9
|
1317 |
9 |
ns32kum |
new_op = {addr_nop,8'h09, imme, src_x, 1'b0,dest_x, opera, 2'b00,2'b10, 4'h0};
|
1318 |
|
|
{8'h07,10'bxx_xx10_x101}: // opcodes like MOVFL
|
1319 |
|
|
new_op = {addr_nop,8'h1F, imme, src_x, 1'b0,dest_x, opera, 2'b11,2'b00, 4'h0};
|
1320 |
|
|
|
1321 |
|
|
// Phase 8 : 2. part of 64 bit data : can be reached from PHASE_0 if 8B data
|
1322 |
11 |
ns32kum |
{8'h08,10'bxx_xxxx_xxxx}: new_op = {addr_nop,endea, quei1,src_x, 1'b1,dest_rl, op_mov, 2'b00,2'b00, diacb};
|
1323 |
9 |
ns32kum |
// Phase 9 : step in between to get data in OUT-Reg Low , SRC1 is not possible
|
1324 |
|
|
{8'h09,10'bxx_xxxx_xxxx}: // afterwards to data write
|
1325 |
|
|
new_op = {addr_nop,8'h10, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b01, 4'h0};
|
1326 |
|
|
// Phase 10 : LSD data write in TEMP , source can be IMME data to
|
1327 |
|
|
{8'h0A,10'bxx_xxxx_xxxx}: // 8B , after TEMP there can only be a 2. operand
|
1328 |
|
|
new_op = idx_2[2] ?
|
1329 |
|
|
{addr_nop,8'h0F, imme, src_x, 1'b1,temp_l, op_mov, 2'b00,2'b00, 4'h0}
|
1330 |
|
|
: {adrd2, phrd2, imme, rega2, 1'b1,temp_l, op_mov, 2'b00,2'b00, nxrw2};
|
1331 |
|
|
|
1332 |
|
|
// Phase 11 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure "1"
|
1333 |
|
|
{8'h0B,10'bxx_xx0x_x0xx}: // into Reg with step in between for ABSL etc. : phase 12
|
1334 |
|
|
new_op = {addr_nop,8'h0C, imme, src_x, 1'b1,dest_r, opera, 2'b00,2'b00, 4'b1100};
|
1335 |
|
|
{8'h0B,10'bxx_xx1x_x01x}: // execute long operation , load LSD , phase 25 , wait in phase 31
|
1336 |
|
|
new_op = {addr_nop,8'h19, imme, src_2, 1'b0,dest_r, opera, 2'b01,2'b00, 4'b1100};
|
1337 |
11 |
ns32kum |
{8'h0B,10'bxx_xxxx_x11x}: // 8B data into TEMP , step in between then read 2. Op : phase 10 - can only be "long" operation
|
1338 |
9 |
ns32kum |
new_op = {addr_nop,8'h0A, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'b1100};
|
1339 |
11 |
ns32kum |
{8'h0B,10'bxx_xx0x_x10x}: // ABS etc. : LSD data via SRC2 into 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9
|
1340 |
9 |
ns32kum |
new_op = {addr_nop,8'h09, imme, src_x, 1'b0,dest_x, opera, 2'b00,2'b10, 4'b1100};
|
1341 |
11 |
ns32kum |
{8'h0B,10'bxx_xx1x_xx0x}: // MOVLF with 8B IMME data ? Must be possible, the end in phase 24 like SRC1=MEM
|
1342 |
9 |
ns32kum |
new_op = {addr_nop,8'h18, imme, src_x, 1'b1,temp_l, op_mov, 2'b01,2'b00, 4'b1100};
|
1343 |
|
|
// Phase 12 : wait for 2. part of 64 bit IMME data : after phase 0
|
1344 |
11 |
ns32kum |
{8'h0C,10'bxx_xxxx_xxxx}: new_op = {addr_nop,endea, imme ,src_x, 1'b1,dest_rl, op_mov, 2'b00,2'b00, diacb};
|
1345 |
9 |
ns32kum |
|
1346 |
|
|
// Phase 15 : secure in TEMP with Index continue and read 2. operand
|
1347 |
11 |
ns32kum |
{8'h0F,10'bxx_xxxx_xxxx}: new_op = {adrd2, phrd2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1348 |
9 |
ns32kum |
// Phase 16 : after LD_OUT continue with Index and store 1. operand
|
1349 |
11 |
ns32kum |
{8'h10,10'bxx_xxxx_xxxx}: new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1350 |
9 |
ns32kum |
|
1351 |
|
|
// +++++++++++++++++ SRC2 operand loading : phase SRC1 + 16 +++++++++++++++++++
|
1352 |
|
|
|
1353 |
|
|
// Phase 21 : wait for data and Disp2 for external addressing : part 2 EA = (MOD+4)+4*DISP1
|
1354 |
|
|
// next phase fix : 22
|
1355 |
11 |
ns32kum |
{8'h15,10'bxx_xxxx_xxxx}: new_op = {exr11, 8'h16, src_x,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
|
1356 |
9 |
ns32kum |
// Phase 22 : Memory-Pointer for Memory Relative and last access external
|
1357 |
|
|
// next phase fix : 23 , add Index
|
1358 |
11 |
ns32kum |
{8'h16,10'bxx_xxxx_xxxx}: new_op = {exr22, 8'h17, irrw2,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 3'b111,atyd[0]};
|
1359 |
9 |
ns32kum |
|
1360 |
|
|
// Phase 23 : wait for final data , direct from PHASE_0 if TOS without Index
|
1361 |
|
|
// next phase : if 8B data phase 24 is used
|
1362 |
11 |
ns32kum |
{8'h17,10'bxx_xx0x_xxx1}: // execute short operation and write data into memory , no WREN -> phase 39 ACC_DONE
|
1363 |
9 |
ns32kum |
new_op = {re_wr, 8'h27, quet1,imme , 1'b0,dest_r, opera, 2'b00,2'b10, 4'b0001};
|
1364 |
|
|
{8'h17,10'bxx_xx0x_xxx0}: // execute short operation , no WREN -> phase 0 , CMP(+TBIT)
|
1365 |
|
|
new_op = {addr_nop,endea, quet1,imme , 1'b0,dest_r, opera, 2'b00,2'b10, diacb};
|
1366 |
|
|
{8'h17,10'bxx_xx10_xxxx}: // execute long operation , wait in phase 31
|
1367 |
|
|
new_op = {addr_nop,8'h1F, quet1,imme , wlor,dest_r, opera, 2'b11,2'b00, 4'h0};
|
1368 |
|
|
{8'h17,10'bxx_xx11_xxxx}: // execute long operation , load LSD in phase 24
|
1369 |
|
|
new_op = {addr_nop,8'h18, quet1,imme , 1'b0,dest_r, opera, 2'b01,2'b00, 4'h0};
|
1370 |
11 |
ns32kum |
// Phase 24 : load 2. part of 64 bit data : with and without wait - from 28 the phase waits , from 23 not
|
1371 |
9 |
ns32kum |
{8'h18,10'bxx_xxxx_0xxx}: // execute long operation , wait in phase 31
|
1372 |
|
|
new_op = {addr_nop,8'h1F, src_1l,imme, wlor,dest_r, opera, 2'b10,2'b00, 4'h0};
|
1373 |
11 |
ns32kum |
{8'h18,10'bxx_xxxx_1xxx}: // execute long operation , wait in phase 31 , data from TEMP, used also for ROUNDLi
|
1374 |
9 |
ns32kum |
new_op = {addr_nop,8'h1F, rtmpl,imme, wlor,dest_r, opera, 2'b10,2'b00, 4'h0};
|
1375 |
|
|
// Phase 25 : load 2. part of 64 bit data : SRC1 from memory and SRC2 from Reg
|
1376 |
|
|
{8'h19,10'bxx_xxxx_xxxx}: // execute long operation , wait in phase 31
|
1377 |
|
|
new_op = {addr_nop,8'h1F, imme, src_2l,wlor,dest_r, opera, 2'b10,2'b00, 4'h0};
|
1378 |
|
|
// Phase 26 : load 2. part of 64 bit data : SRC1 from Reg and SRC2 from Reg
|
1379 |
|
|
{8'h1A,10'bxx_xxxx_xxxx}: // execute long operation , wait in phase 31
|
1380 |
|
|
new_op = {addr_nop,8'h1F, src_1l,src_2l,wlor,dest_r, opera, 2'b10,2'b00, 4'h0};
|
1381 |
|
|
|
1382 |
|
|
// Phase 27 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure "1"
|
1383 |
|
|
{8'h1B,10'bxx_xxxx_xxxx}: // execute long operation , load LSD in phase 24
|
1384 |
|
|
new_op = {addr_nop,8'h18, quet1,imme , 1'b0,dest_r, opera, 2'b01,2'b00, 4'b1100};
|
1385 |
|
|
|
1386 |
|
|
// +++++++++++++++++ special case ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
1387 |
|
|
// Phase 28 : TOS with 8B SRC1 operand , no Index ! Jump to phase 39
|
1388 |
|
|
{8'h1C,10'bxx_xxxx_xxxx}: // store Source 1 in Dest : "pass through" for MOV,NEG,ABS
|
1389 |
|
|
new_op = {adwr2, phwr2, src_x,rega2, 1'b0,dest_x, opera, 2'b00,2'b00, nxrw2};
|
1390 |
|
|
// +++++++++++++++++ close operation : write out DEST , TOS update +++++++++++++++++++
|
1391 |
|
|
|
1392 |
|
|
// Phase 31 : wait for DONE of long operation
|
1393 |
|
|
{8'h1F,10'bxx_xxxx_xxx0}: // CMP done -> phase 0
|
1394 |
|
|
new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b10, 4'h0}; // no ACB
|
1395 |
|
|
{8'h1F,10'bxx_xxxx_x0x1}: // operation closed , data into register
|
1396 |
|
|
new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b00, 4'h0}; // no ACB
|
1397 |
11 |
ns32kum |
{8'h1F,10'bxx_xxxx_x101}: // operation closed , data into memory - first calculate address phase 32+x
|
1398 |
23 |
ns32kum |
new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_r, opera, 2'b00,2'b10, nxrw2};
|
1399 |
9 |
ns32kum |
{8'h1F,10'bxx_xxxx_x111}: // operation closed , data into memory - address reuse phase 39 ACC_DONE
|
1400 |
23 |
ns32kum |
new_op = {re_wr, 8'h27, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b10, 4'b0001};
|
1401 |
9 |
ns32kum |
|
1402 |
|
|
// Destination address calculate
|
1403 |
|
|
// Phase 37 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
|
1404 |
|
|
// next phase fix : 38
|
1405 |
11 |
ns32kum |
{8'h25,10'bxx_xxxx_xxxx}: new_op = {exr11, 8'h26, src_x,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
|
1406 |
9 |
ns32kum |
// Phase 38 : Memory-Pointer for Memory Relative and letzter Zugriff External
|
1407 |
|
|
// next phase fix : 39 , add Index and write
|
1408 |
11 |
ns32kum |
{8'h26,10'bxx_xxxx_xxxx}: new_op = {exw22, 8'h27, irrw2,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
|
1409 |
9 |
ns32kum |
|
1410 |
|
|
// Phase 39 : wait for ACC_DONE : consequent numbering : 7+32
|
1411 |
|
|
{8'h27,10'bxx_xxxx_xxxx}: // now operation closed , only ACB could follow
|
1412 |
|
|
new_op = {addr_nop,endea, src_x,src_x, 1'b0,dest_x, opera, 2'b00,2'b00, diacb};
|
1413 |
|
|
|
1414 |
|
|
// +++++++++++++++ special case : ACB to Reg is to fast ! One wait cycle for ZERO-Flag
|
1415 |
11 |
ns32kum |
{8'h28,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h01,src_x, src_x, 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1110};
|
1416 |
9 |
ns32kum |
|
1417 |
|
|
// +++++++++++++++ The other opcodes are following ++++++++++++++++++
|
1418 |
|
|
|
1419 |
11 |
ns32kum |
{8'h00,10'b01_xxxx_xxxx}: new_op = {new_addr,new_ph,new_regs, 1'b0,dest_x, op_mov, new_nx}; // 1 Byte Opcodes
|
1420 |
9 |
ns32kum |
|
1421 |
|
|
// Phase 1 : used for Bcond and ACB :
|
1422 |
|
|
{8'h01,10'bxx_xxxx_xxxx}: new_op = (ex_br_op[1] | jsr_flag) ? // BSR or JSR ?
|
1423 |
|
|
{push_op, 8'h27, imme, stack, 1'b0,dest_x, op_mov, 2'b00,2'b10, 4'b0001} // wait at end
|
1424 |
|
|
: {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1425 |
|
|
|
1426 |
|
|
// Phase 42 : RET : read of PC from Stack and DIN via SRC1 to PC
|
1427 |
11 |
ns32kum |
{8'h2A,10'bxx_xxxx_xxxx}: new_op = {adddisp, 8'h2B, imme, src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'hE};
|
1428 |
|
|
// Phase 43 : RET : Displacement add to Stack. Attention : "imme" important to keep source constant for PC
|
1429 |
|
|
{8'h2B,10'bxx_xxxx_xxxx}: new_op = {save_sp, 8'h2C, imme, src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1430 |
9 |
ns32kum |
// Phase 44 : RET : Update of Stack : fixed phase
|
1431 |
11 |
ns32kum |
{8'h2C,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1432 |
9 |
ns32kum |
|
1433 |
|
|
// Phase 45 : ENTER Entry
|
1434 |
11 |
ns32kum |
{8'h2D,10'bxx_xxxx_xxxx}: new_op = {dispmin, 8'h2E, src_x,src_x, 1'b1,temp_l, op_adr, 2'b00,2'b00, 4'hE};
|
1435 |
9 |
ns32kum |
// Phase 46 : ENTER Stack longer
|
1436 |
11 |
ns32kum |
{8'h2E,10'bxx_xxxx_xxxx}: new_op = {save_sp ,8'h31, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1437 |
9 |
ns32kum |
// Phase 48 : SAVE/ENTER : Init phase , phases 48 & 49 very similar
|
1438 |
|
|
{8'h30,10'bxx_xxxx_xxxx}: new_op = save_reg ?
|
1439 |
|
|
{push_op, 8'h31, saver,stack, 1'b0,dest_x, op_mov, 2'b00,2'b10, 4'h1} // 1. load SP=>EA
|
1440 |
11 |
ns32kum |
: {addr_nop,8'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov, 2'b00,2'b00, 4'h0}; // At ENTER FP Update
|
1441 |
9 |
ns32kum |
// Phase 49 : SAVE/ENTER : at the same time memory access and detection of next Reg
|
1442 |
|
|
{8'h31,10'bxx_xxxx_xxxx}: new_op = save_reg ?
|
1443 |
|
|
{push_ea, 8'h31, saver,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b10, 4'h1} // one more
|
1444 |
11 |
ns32kum |
: {addr_nop,8'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov, 2'b00,2'b00, 4'h0}; // At ENTER FP Update
|
1445 |
9 |
ns32kum |
|
1446 |
|
|
// Phase 50 : RESTORE/EXIT Entry
|
1447 |
|
|
{8'h32,10'bxx_xxxx_xxxx}: new_op = save_reg ?
|
1448 |
|
|
{pop_op, 8'h33, src_x,stack, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1}
|
1449 |
|
|
: {pop_fp, ppfp, src_x,frame, 1'b0,dest_x, op_mov, 2'b00,2'b00, 3'h0,new_fp};
|
1450 |
|
|
// Phase 51 : RESTORE/EXIT next reg
|
1451 |
|
|
{8'h33,10'bxx_xxxx_xxxx}: new_op = save_reg ?
|
1452 |
|
|
{next_po, 8'h33, imme, src_x, 1'b1,resto, op_mov, 2'b00,2'b00, 4'h1}
|
1453 |
|
|
: {pop_fp, ppfp, imme, frame, 1'b1,resto, op_mov, 2'b00,2'b00, 3'h0,new_fp};
|
1454 |
|
|
// Phase 52 : EXIT End
|
1455 |
11 |
ns32kum |
{8'h34,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h00, imme, src_x, 1'b1,frame[5:0], op_mov, 2'b00,2'b00, 4'h0};
|
1456 |
9 |
ns32kum |
|
1457 |
|
|
// Phase 53 : CXP Entry : this opcode needs 12 States and 16 cycles minimum ...
|
1458 |
11 |
ns32kum |
{8'h35,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h36, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0};
|
1459 |
9 |
ns32kum |
// Phase 54 : CXP : Store Address Link table
|
1460 |
11 |
ns32kum |
{8'h36,10'bxx_xxxx_xxxx}: new_op = {rdltab, 8'h37, src_x,rtmph, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'hE}; // EA Phase : DISP read
|
1461 |
9 |
ns32kum |
// Phase 55 : CXP : DISP is worked on, the return address => temp_l
|
1462 |
11 |
ns32kum |
{8'h37,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h38, imme, rtmph, 1'b1,temp_l, op_mov, 2'b00,2'b00, 4'h1}; // Access
|
1463 |
9 |
ns32kum |
// Phase 56 : CXP : Access to Link table => Result is MOD-Entry => store in temp_h
|
1464 |
11 |
ns32kum |
{8'h38,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h39, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0};
|
1465 |
9 |
ns32kum |
// Phase 57 : CXP : store and PUSH MOD prepare , Entry from Exception Processing
|
1466 |
11 |
ns32kum |
{8'h39,10'bxx_xxxx_xxxx}: new_op = {push_op, 8'h3A, modul,stack, 1'b0,dest_x, op_wrp, 2'b00,2'b10, 4'h1};
|
1467 |
9 |
ns32kum |
// Phase 58 : CXP : PUSH of MOD ongoing, PUSH PC prepare
|
1468 |
11 |
ns32kum |
{8'h3A,10'bxx_xxxx_xxxx}: new_op = {ea_push, 8'h3B, rtmpl,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b10, 4'h0};
|
1469 |
9 |
ns32kum |
// Phase 59 : CXP : New EA for PC
|
1470 |
11 |
ns32kum |
{8'h3B,10'bxx_xxxx_xxxx}: new_op = {save_sp, 8'h3C, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1471 |
9 |
ns32kum |
// Phase 60 : CXP : write of PC, calculate of Offset
|
1472 |
11 |
ns32kum |
{8'h3C,10'bxx_xxxx_xxxx}: new_op = {rmod_8, 8'h3D, rtmph,rtmph, 1'b1,temp_l, op_flip,2'b00,2'b00, 4'h1};
|
1473 |
9 |
ns32kum |
// Phase 61 : CXP : read from (MOD:New+8)
|
1474 |
11 |
ns32kum |
{8'h3D,10'bxx_xxxx_xxxx}: new_op = {ea_min8, 8'h3E, imme, rtmpl, 1'b1,temp_l, op_add, 2'b00,2'b00, 4'h0}; // Reuse of EA
|
1475 |
9 |
ns32kum |
// Phase 62 : CXP : EA Phase of SB read , new PC calculated
|
1476 |
11 |
ns32kum |
{8'h3E,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h3F, rtmpl,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1477 |
9 |
ns32kum |
// Phase 63 : CXP : read of SB , new PC to ICache
|
1478 |
11 |
ns32kum |
{8'h3F,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h2F, imme, src_x, 1'b1,6'h1A, op_mov, 2'b00,2'b00, 4'h0}; // SB load
|
1479 |
9 |
ns32kum |
// Phase 47 : CXP : Last phase update of MOD prepare
|
1480 |
11 |
ns32kum |
{8'h2F,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h00, rtmph,src_x, 1'b1,modul[5:0], op_mov, 2'b00,2'b00, 4'h0}; // MOD load
|
1481 |
9 |
ns32kum |
|
1482 |
|
|
// Phase 64 : RXP Entry : POP of PC , full Access
|
1483 |
11 |
ns32kum |
{8'h40,10'bxx_xxxx_xxxx}: new_op = {pop_ru, 8'h41, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0};
|
1484 |
9 |
ns32kum |
// Phase 65 : RXP : PC is read, next POP prepare
|
1485 |
11 |
ns32kum |
{8'h41,10'bxx_xxxx_xxxx}: new_op = {adddisp, 8'h42, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'hF};
|
1486 |
9 |
ns32kum |
// Phase 66 : RXP : DISP is addeed to Stack and MOD is read
|
1487 |
11 |
ns32kum |
{8'h42,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h43, imme, src_x, 1'b1,modul[5:0], op_mov, 2'b00,2'b00, 4'h0};
|
1488 |
9 |
ns32kum |
// Phase 67 : RXP : MOD is new
|
1489 |
11 |
ns32kum |
{8'h43,10'bxx_xxxx_xxxx}: new_op = {rmod_rxp,8'h44, rtmph,modul, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1490 |
9 |
ns32kum |
// Phase 68 : RXP : wait for SB data, parallel SP update
|
1491 |
11 |
ns32kum |
{8'h44,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h00, imme, src_x, 1'b1,6'h1A, op_mov, 2'b00,2'b00, 4'h0}; // SB load
|
1492 |
9 |
ns32kum |
|
1493 |
|
|
// Phase 69 : RETI : read of ICU for End-of-Interrupt Cycle , prepare read PC from Stack
|
1494 |
11 |
ns32kum |
{8'h45,10'bxx_xxxx_xxxx}: new_op = {pop_op, 8'h46, src_x,stack, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1495 |
9 |
ns32kum |
// Phase 70 : RETI/ RETT Entry : POP of PC , full Access
|
1496 |
11 |
ns32kum |
{8'h46,10'bxx_xxxx_xxxx}: new_op = {pop_ru, 8'h47, imme, src_x, 1'b1,temp_h, op_mov, 2'b00,2'b00, 4'h0};
|
1497 |
9 |
ns32kum |
// Phase 71 : RETI/RETT : PC is read, next POP prepare
|
1498 |
11 |
ns32kum |
{8'h47,10'bxx_xxxx_xxxx}: new_op = {save_sp, 8'h48, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1499 |
9 |
ns32kum |
// Phase 72 : RETI/RETT : DISP is added to Stack , PSR load and MOD is loaded if DE off
|
1500 |
11 |
ns32kum |
{8'h48,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h49, imme, src_x, no_modul, op_ldp, 2'b00,2'b00, 4'h0};
|
1501 |
9 |
ns32kum |
// Phase 73 : RETI/RETT : different paths
|
1502 |
|
|
{8'h49,10'bxx_xxxx_xxxx}: new_op = de_flag ?
|
1503 |
|
|
( reti_flag ?
|
1504 |
|
|
{addr_nop,8'h4A, rtmph,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0}
|
1505 |
|
|
: {addr_nop,8'h4B, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0} )
|
1506 |
|
|
: {rmod_rtt,8'h4B, rtmph,modul, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h1};
|
1507 |
|
|
// Phase 74 : RETI/RETT : one pause cycle if DE on
|
1508 |
11 |
ns32kum |
{8'h4A,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1509 |
9 |
ns32kum |
// Phase 75 : RETI/RETT : SB read if DE off
|
1510 |
|
|
{8'h4B,10'bxx_xxxx_xxxx}: new_op = reti_flag ?
|
1511 |
|
|
{addr_nop,8'h00, imme, src_x, 1'b1,6'h1A, op_mov, 2'b00,2'b00, 4'h0}
|
1512 |
|
|
: ( de_flag ?
|
1513 |
|
|
{adddispn,8'h4E, src_x,ttstak,1'b0,dest_x, op_mov, 2'b00,2'b00, 4'hE}
|
1514 |
|
|
: {adddispn,8'h4E, imme, ttstak,1'b1,6'h1A, op_mov, 2'b00,2'b00, 4'hE} );
|
1515 |
|
|
// Phase 78 : RETT : SP update
|
1516 |
11 |
ns32kum |
{8'h4E,10'bxx_xxxx_xxxx}: new_op = {save_sp, 8'h4A, rtmph,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1517 |
9 |
ns32kum |
|
1518 |
|
|
// +++++++++++++++ special wait states for PSR and the Cache/MMU system +++++++++++
|
1519 |
|
|
|
1520 |
|
|
// Phase 76 : PSR in Word case simple delay of 2 cycles : 1. cycle does nothing
|
1521 |
11 |
ns32kum |
{8'h4C,10'bxx_xxxx_xxxx}: new_op = {addr_nop,8'h4D, src_x,src_x, 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'h0};
|
1522 |
|
|
// Phase 77 : PSR in Word case simple delay of 2 cycles : 2. cycle does Restart of instruction processing
|
1523 |
|
|
{
|