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[/] [m32632/] [trunk/] [rtl/] [DECODER.v] - Blame information for rev 49

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Line No. Rev Author Line
1 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 9 ns32kum
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       DECODER.v
7 49 ns32kum
//      Version:        3.2 bug fix     
8
//  History:    3.0 of 2 December 2018
9
//                              2.0 of 11 August 2016
10 29 ns32kum
//                              1.0 first release of 30 Mai 2015
11 49 ns32kum
//      Date:           17 January 2021
12 9 ns32kum
//
13 49 ns32kum
// Copyright (C) 2021 Udo Moeller
14 9 ns32kum
// 
15
// This source file may be used and distributed without 
16
// restriction provided that this copyright statement is not 
17
// removed from the file and that any derivative work contains 
18
// the original copyright notice and the associated disclaimer.
19
// 
20
// This source file is free software; you can redistribute it 
21
// and/or modify it under the terms of the GNU Lesser General 
22
// Public License as published by the Free Software Foundation;
23
// either version 2.1 of the License, or (at your option) any 
24
// later version. 
25
// 
26
// This source is distributed in the hope that it will be 
27
// useful, but WITHOUT ANY WARRANTY; without even the implied 
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
29
// PURPOSE. See the GNU Lesser General Public License for more 
30
// details. 
31
// 
32
// You should have received a copy of the GNU Lesser General 
33
// Public License along with this source; if not, download it 
34
// from http://www.opencores.org/lgpl.shtml 
35
// 
36 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
37 9 ns32kum
//
38
//      Modules contained in this file:
39
//      DECODER         Instruction Decoding and Flow Control
40
//
41 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42 9 ns32kum
 
43 11 ns32kum
module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,
44 9 ns32kum
                                 PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,
45 11 ns32kum
                                 GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,
46 23 ns32kum
                                 INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP,
47
                                 PHOUT );
48 9 ns32kum
 
49
        input                   BCLK,BRESET;
50
        input                   INT_N,NMI_N;    // external inputs
51
        input    [2:0]   ANZ_VAL;
52
        input   [55:0]   OPREG;                  // the OPREG contains the bytes to decode, OPREG[55:32] are don't care
53
        input    [8:0]   CFG;                    // CONFIG : many bits are don't-care
54
        input   [11:0]   PSR;
55
        input                   ACC_DONE;
56
        input                   DC_ABORT,IC_ABORT;
57
        input                   ACB_ZERO;
58
        input                   DONE;
59
        input   [31:0]   PC_SAVE;
60
        input    [4:0]   STRING;
61
        input                   INIT_DONE;
62
        input                   ILL,UNDEF;
63
        input    [5:0]   TRAPS;
64
        input                   IC_READ;
65
        input                   STOP_CINV;              // not to mix it up with STOP_IC
66
 
67
        output   [2:0]   GENSTAT;
68 11 ns32kum
        output  [31:0]   DISP,IMME_Q,DISP_BR;    // three main data busses : Displacement, Immediate and Displacement for Branch
69 9 ns32kum
        output   [2:0]   USED;
70
        output                  NEW;
71
        output                  LOAD_PC;
72
        output                  NEXT_PCA;
73
        output   [7:0]   RDAA,RDAB;
74
        output  [10:0]   OPER;
75
        output   [1:0]   START,LD_OUT;
76
        output                  LD_DIN,LD_IMME;
77
        output   [6:0]   INFO_AU;
78
        output  [14:0]   ACC_FELD;
79
        output                  WREN;
80
        output   [5:0]   WRADR;
81
        output   [1:0]   WMASKE;
82
        output  reg             WR_REG;
83
        output  [12:0]   DETOIP;
84
        output   [1:0]   MMU_UPDATE;
85
        output                  RESTART;
86
        output                  STOP_IC;
87
        output   [2:0]   RWVAL;
88
        output                  ENA_HK;
89
        output  reg             ILO;
90
        output  [23:0]   COP_OP;
91 23 ns32kum
        output   [7:0]   PHOUT;          // for Debug purposes, phase_reg output
92 9 ns32kum
 
93
        reg             [31:0]   DISP,disp_val;
94
        reg             [10:0]   oper_i;
95
        reg              [2:0]   USED;
96
        reg             [14:0]   ACC_FELD;
97
        reg              [1:0]   ldoreg;
98
        reg                             wren_i;
99
        reg              [5:0]   wradr_i;
100
        reg              [1:0]   wmaske_i;
101 23 ns32kum
        reg              [1:0]   start_i;
102 9 ns32kum
        reg             [23:0]   COP_OP;
103
        reg                             spupd_i;
104
        reg              [3:0]   disp_sel;
105
        reg             [52:0]   op1_feld;
106
        reg             [47:0]   op2_feld;
107
        reg             [47:0]   op3_feld;
108
        reg             [47:0]   op_feld_reg;
109
        reg             [31:0]   imme_i;
110
        reg              [2:0]   valid;
111
        reg              [7:0]   phase_reg;
112
        reg              [3:0]   di_stat;        // Displacement Status
113
        reg              [3:0]   cc_feld;
114
        reg              [1:0]   ex_br_op;
115
        reg                             acb_reg;
116
        reg                             jsr_flag;
117
        reg              [8:0]   waitop,wait_reg;
118
        reg                             branch;
119
        reg              [3:0]   dim_feld;
120
        reg             [66:0]   new_op;
121
        reg                             short_op_reg;
122
        reg             [15:0]   idx_reg;
123
        reg             [35:0]   gen_src1;
124
        reg             [33:0]   gen_src2;
125
        reg                             qw_flag;
126
        reg                             long_reg;
127
        reg                             new_spsel;
128
        reg                             s_user,old_su;
129
        reg              [1:0]   stack_sel;      // Stack select for USER and SUPERVISOR
130
        reg              [1:0]   s_mod;          // Modifier for Stack select
131
        reg                             upd_info,dw_info;
132
        reg              [2:0]   rpointer;
133
        reg              [5:0]   resto;          // for RESTORE
134
        reg                             init_rlist;
135
        reg                             new_fp;
136
        reg                             format1;
137
        reg                             ldpc_phase;
138
        reg                             reti_flag;
139
        reg                             no_t2p;
140
        reg                             iabort,ia_save;
141
        reg                             mmu_sel;
142
        reg              [1:0]   nmi_reg;
143
        reg                             nmi_flag,int_flag;
144
        reg                             type_nmi;
145
        reg              [3:0]   exc_vector;
146
        reg                             phase_exc;
147
        reg              [3:0]   ovf_pipe;
148
        reg                             dbg_s,dbg_trap,dbg_en,addr_cmp;
149
        reg                             ssrc_flag,sdest_flag;
150
        reg                             op_setcfg,setcfg_lsb;
151
        reg                             inss_op;
152
        reg                             exin_cmd,extract;       // EXT/INS
153
        reg                             bit_reg;        // Flag for Bit opcodes : Source2 = Reg
154
        reg                             kurz_st;        // Flag for MOVM/CMPM
155
        reg                             kill_opt;       // Flag for optimized MOVS
156
        reg                             cmps_flag;      // Flag for CMPS
157
        reg                             skps_flag;      // Flag for SKPS
158
        reg                             mt_flag;        // Flag for Match and Translate
159
        reg                             spu_block;      // block of SP update at Long operation
160
        reg                             dia_op,dia_flag;        // Flag for DIA
161
        reg                             m_ussu,m_usel,dc_user;  // MOVUS/SU
162
        reg                             rwval_flag,wrval_flag;  // RDVAL/WRVAL
163
        reg                             cinv_flag;      // Flag for CINV
164
        reg              [5:0]   lmrreg;
165
        reg                             no_init,a_ivar;
166
        reg                             index_cmd;
167
        reg                             stop_d;
168
        reg                             dc_ilo;
169
 
170
        wire                    PHASE_0;
171
        wire     [7:0]   phase_ein;      // Phase after ABORT has changed the content to 0
172
        wire                    de_flag,ivec_flag;
173
        wire                    next;
174
        wire    [18:0]   new_addr,pop_fp,save_pc;
175
        wire    [13:0]   new_regs;
176
        wire     [7:0]   new_ph,ppfp;
177
        wire     [7:0]   new_nx;
178
        wire                    op_1byte,op_12byte,op_2byte,op_3byte;
179
        wire                    jump;
180
        wire                    short_op,short_def;
181 23 ns32kum
        wire                    opt_imme;
182
        wire     [7:0]   opti_byte;
183 9 ns32kum
        wire                    acb_op,acb_flag;
184
        wire                    zero,carry_psr,negativ,larger,flag;
185
        wire                    valid_size;
186
        wire                    op_ok;
187
        wire                    stop;
188
        wire    [47:0]   opc_bits;
189
        wire    [47:0]   op_feld;
190
        wire     [2:0]   atys,atyd;
191
        wire     [3:0]   auop_s,auop_d;
192
        wire                    long,src2_flag,dest_flag;
193
        wire     [6:0]   src_1,src_2,src_1l,src_2l;
194
        wire     [1:0]   src1_le,src2_le;
195
        wire                    acc1,acc2;
196
        wire                    spupd;
197
        wire     [6:0]   saver;  // for SAVE
198
        wire     [2:0]   reg_nr;
199
        wire                    save_reg;
200
        wire                    ld_disp,disp_ok;
201
        wire                    store_pc;
202
        wire                    do_xor;
203
        wire                    do_long;
204
        wire     [1:0]   idx_n,n_idx;
205
        wire                    idx;
206
        wire     [1:0]   otype;
207
        wire    [10:0]   opera,op_str,op_sho;
208
        wire     [5:0]   dest_r,dest_rl;
209
        wire                    phase_idx;
210
        wire    [15:0]   idx_bytes,idx_feld;
211
        wire     [3:0]   idx_1,idx_2;
212
        wire     [4:0]   src1_addr,src2_addr;
213
        wire     [6:0]   usp_1,usp_2;
214
        wire    [33:0]   tos_oper;
215 11 ns32kum
        wire    [18:0]   adrd1,exr11,exr12,adrd2,adwr2,exr22,exw22,re_wr,st_src,st_src2,st_dest,st_len,st_trde,st_trs2;
216 9 ns32kum
        wire     [7:0]   phrd1,phrd2,phwr2;
217
        wire     [6:0]   rega1,irrw1,rega2,irrw2;
218
        wire     [3:0]   nxrd1,nxrw2;
219
        wire                    rmw;
220
        wire     [6:0]   quei1,quet1;            // Registeradr
221
        wire     [7:0]   endea,goacb,dowait;     // Phase
222
        wire     [3:0]   diacb;                          // DIMM access
223
        wire                    qword;
224
        wire     [6:0]   stack,no_modul,ttstak;
225
        wire    [12:0]   pop_1;
226
        wire                    mpoi_1,mpoi_2;
227
        wire     [1:0]   src1_tos;               // the code for REUSE is 2'b11
228
        wire                    svc_flag,bpt_flag,flag_flag,trac_flag;
229
        wire     [3:0]   misc_vectors;
230
        wire     [2:0]   psr_code;
231
        wire                    exception;
232
        wire                    interrupt;
233
        wire                    abort;          // DC_ABORT | iabort;
234
        wire                    abo_int;
235
        wire                    iabo_fall;
236
        wire                    abbruch,fpu_trap,dvz_trap;
237
        wire                    abbruch2;
238
        wire                    dbg_flag;
239
        wire                    ovf_op,ovf2_op,ovf_flag;
240
        wire                    pc_match;
241
        wire                    no_trap;
242
        wire    [10:0]   op_psr,op_scp;
243
        wire    [30:0]   ai_next;
244
        wire                    set_src,set_dest,clr_sflag;
245
        wire     [7:0]   rrepa;  // Repair Phase of Abort for String opcodes
246
        wire     [7:0]   ph_str; // working phase String
247
        wire                    ph_match;
248
        wire                    t2p;
249
        wire                    rw_bit,op_ilo;
250
        wire                    setcfg;
251
        wire                    string_ende;
252
        wire                    wlor;   // Flag to generate WR_REG signal
253
        wire     [5:0]   wstr0,wstr1,wstr2;
254
        wire     [6:0]   rstr0,rstr1,rstr2;
255
        wire                    rett_exc;
256
        wire                    chk_rmw;
257
 
258
        // Variables for 2- and 3-Byte Dekoder :
259
        reg              [5:0]   hzr_c;  // CASE Statement
260
        wire     [1:0]   hzl_a;
261
        wire     [2:0]   hzl_b;
262
        wire     [5:0]   hzr_a,hzr_b,hzr_s;
263
        wire                    hdx_a;
264
        wire     [3:0]   hdo_a,hdo_c,hdo_e;
265
        wire     [7:0]   hdo_d;
266
        wire     [1:0]   hdl_b,hdl_d,hdl_f,hdl_g,hdl_h;
267
        wire     [2:0]   hdl_a,hdl_c,hdl_e;
268
        wire     [5:0]   hdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;
269
 
270
        wire    [66:0]   state_0,state_group_50,state_group_60;  // for the Gruppe 2 opcodes
271
 
272
        // Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
273
 
274
        parameter addr_nop      = 19'b10_0000_0000_0_0000_0000; // all parameter to 0
275
        parameter push_op       = 19'b10_0111_0000_1_1010_0000; // i.e. for BSR, ENTER ...
276
        parameter push_ea       = 19'b10_0111_0000_1_1010_0011; // SAVE middle
277
        parameter pop_op        = 19'b10_1011_0010_1_0000_1000; // RET/RESTORE
278
        parameter adddisp       = 19'b10_0010_0000_0_0000_0011; // for RET : reuse of EA
279
        parameter adddispn      = 19'b10_0010_0000_0_0000_0000; // for RETT : add Disp to Stack
280
        parameter save_sp       = 19'b10_0000_0000_1_0000_0000; // u.a. RET : update of Stack
281
        parameter next_po       = 19'b10_1011_0010_1_0000_1011; // RESTORE middle
282
        parameter dispmin       = 19'b10_0010_0000_0_0100_0011; // Reuse for ENTER
283 11 ns32kum
        parameter rmod_rxp      = 19'b10_1001_0000_1_0000_0100; // MODUL+0 read : SB , SP Update , therefore no LDEA
284 9 ns32kum
        parameter rmod_rtt      = 19'b10_1001_0000_0_0000_0100; // MODUL+0 read : SB , no LDEA
285
        parameter rmod_4        = 19'b10_1011_0000_0_0001_0100; // MODUL+4 read : Link Table Base
286
        parameter rmod_8        = 19'b10_1011_0000_0_0010_0100; // MODUL+8 read : Program Base
287
        parameter rdltab        = 19'b10_1010_0000_0_1000_0000; // Link table read - EA Phase
288
        parameter ea_push       = 19'b10_0110_0000_0_1010_0011; // CXP : 2. Push EA Phase
289
        parameter ea_min8       = 19'b10_1010_0000_0_1011_0011; // CXP : reuse of MOD+8
290
        parameter pop_ru        = 19'b10_1010_0010_0_0000_1011; // RXP : EA Phase MOD POP
291
        parameter rd_icu        = 19'b00_1001_0000_0_1100_0010; // Read ICU : Byte of fix address
292
        parameter get_vec       = 19'b10_1001_0000_0_01xx_0000; // Read Exception-Vector : Index Exception No.
293 11 ns32kum
        parameter get_veci      = 19'b10_1001_0110_0_0000_0000; // Read Exception-Vector : Index external Interrupt
294 9 ns32kum
        parameter load_ea       = 19'b10_0010_0000_0_0000_0000; // used for store of TEAR and MSR
295
        parameter save_msr      = 19'b10_0010_0001_0_0000_0000; // used for store of TEAR and MSR
296
        parameter ivar_adr      = 19'b10_0000_0100_0_0000_0010; // only pass SRC1
297
        parameter st_trans      = 19'b00_1001_0100_0_0000_0000; // Translate at String : SRC1 + SRC2 , Byte
298
        parameter src_x         = 7'hxx;
299
        parameter dest_x        = 6'hxx;
300
        parameter imme          = {1'b1,6'hxx};
301
        parameter frame         = 7'h18;
302
        parameter ibase         = 7'h1E;
303
        parameter modul         = 7'h1F;
304
        parameter w_msr         = 6'h0A;
305
        parameter w_tear        = 6'h0B;
306
        parameter fsr_r         = 6'h17;        // not defined register for FSR for opcodes LFSR and SFSR
307
        parameter temp_l        = 6'h3C;
308
        parameter temp_h        = 6'h3D;        // second last space for 8B TEMP register
309
        parameter temp_1        = 6'h3E;        // Backup for register at String operations
310
        parameter temp_2        = 6'h3F;
311
        parameter rtmpl         = 7'h3C;
312
        parameter rtmph         = 7'h3D;
313
        parameter rtmp1         = 7'h3E;
314
        parameter rtmp2         = 7'h3F;
315 14 ns32kum
        parameter op_mov        = 11'h345;
316
        parameter op_adr        = 11'h349;
317 9 ns32kum
        parameter op_add        = 11'h340;      // for CXP
318
        parameter op_flip       = 11'h364;      // for CXP : LSHD -16,Ri
319
        parameter op_lmr        = 11'h36A;      // for LPR CFG, LMR and CINV
320
        parameter op_wrp        = 11'h387;      // for CXP : write PSR , used also for Exception processing
321
        parameter op_ldp        = 11'h388;      // for RETT and RETI : load of PSR from Stack
322
        parameter op_zex        = 11'h076;      // Zero Extension for ICU Vector - is also used at String Option "T"
323
        parameter op_cop        = 8'hDD;        // Coprozessor Opcode
324
 
325 11 ns32kum
        // ++++++++++++++++++++++++++  The switch logic for the state machine  +++++++++++++++++++++++++++++
326 9 ns32kum
 
327
        always @(ANZ_VAL)
328
                case (ANZ_VAL)
329
                  3'd0  : valid = 3'b000;
330
                  3'd1  : valid = 3'b001;
331
                  3'd2  : valid = 3'b011;
332
                default : valid = 3'b111;
333
                endcase
334
 
335
        assign next = ( PHASE_0 ? op_ok :               // Opcode decoded or Exception processed
336
                                                // Displacement or Immediate operand and external memory access can happen in parallel
337
                                                // i.e. addressing mode Memory Relative
338
                                    (  ((~dim_feld[0] | ACC_DONE) & (~dim_feld[3] | di_stat[0]))  // ACC_DONE resets dim_feld
339
                                                // long operation
340
                                     & ~(long_reg & ~DONE) ) )
341
                                                // hard break : abort or fpu_trap or dvz_trap or ovf_flag
342
                                  | abbruch ;
343
 
344
        always @(posedge BCLK or negedge BRESET)
345
                if (!BRESET) long_reg <= 1'b0;
346
                  else
347
                        long_reg <= next ? do_long : long_reg;  // START[1]
348
 
349
        always @(posedge BCLK or negedge BRESET)        // the central phase register
350
                if (!BRESET) phase_reg <= 8'h0;
351
                  else
352
                        if (next) phase_reg <= new_op[47:40];
353
 
354 23 ns32kum
        assign PHOUT = phase_reg;       // only to debug
355
 
356 9 ns32kum
        always @(*)     // next switch of micro program counter
357
                casex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})
358 23 ns32kum
                  4'b11_xx : USED = {1'b0,~op_1byte,(op_1byte | op_3byte)} + {2'd0,opt_imme};
359 9 ns32kum
                  4'b0x_11 : USED = di_stat[3:1];
360
                  default  : USED = 3'd0;
361
                endcase
362
 
363
        // Special phases
364
 
365
        assign PHASE_0 = (phase_reg == 8'h00);  // During Phase 0 the opcode is decoded
366
 
367
        assign NEXT_PCA = PHASE_0 & ~ovf_flag & ~dbg_flag;
368
 
369
        // Pulse to transfer from Trace Bit to Pending Trace Bit, only once in the beginning of phase 0
370
        // The priority is such that a TRACE exception is served before an UNDEFINED/ILLEGAL exception
371
        always @(posedge BCLK) no_t2p <= PHASE_0 & ~op_ok;
372
        assign t2p = PHASE_0 & ~no_t2p; // signal to I_PFAD
373
 
374
        // ++++++++++++++++++++++++++  global control signals  ++++++++++++++++
375
 
376
        assign de_flag   = CFG[8];
377
        assign ivec_flag = CFG[0];
378
        assign dvz_trap  = TRAPS[1];
379
        assign fpu_trap  = TRAPS[0];
380
 
381 11 ns32kum
        always @(posedge BCLK) nmi_reg  <= {nmi_reg[0],NMI_N};   // one clock sync and than falling edge detection
382 9 ns32kum
 
383
        always @(posedge BCLK or negedge BRESET)
384
                if (!BRESET) nmi_flag <= 1'b0;
385
                  else nmi_flag <= (nmi_reg == 2'b10) | (nmi_flag & ~(phase_reg == 8'h82));
386
 
387
        always @(posedge BCLK) int_flag <= PSR[11] & ~INT_N;    // one clock to synchronise
388
 
389 11 ns32kum
        assign stop              = (int_flag | nmi_flag) &   PHASE_0 & ~stop_d;         // neccesary if FPU_TRAP and INT at the same time
390 9 ns32kum
        assign interrupt = (int_flag | nmi_flag) & (~PHASE_0 |  stop_d);
391
 
392
        always @(posedge BCLK or negedge BRESET)
393
                if (!BRESET) stop_d <= 1'd0;
394
                  else stop_d <= stop;
395
 
396
        // ++++++++++++++++++++++++++  Exception processing  +++++++++++++++
397
 
398
        // IC_ABORT is valid if Opcode Decoder cannot continue
399
        assign iabo_fall = IC_ABORT & (PHASE_0 ? ~op_ok : (~di_stat[0] & dim_feld[3]));
400
 
401
        always @(posedge BCLK) iabort  <= iabo_fall & ~ia_save; // DC_ABORT ist a pulse
402
        always @(posedge BCLK) ia_save <= iabo_fall;
403
 
404
        // mmu_sel is used in ADDR_UNIT
405
        always @(posedge BCLK) mmu_sel <= DC_ABORT | (mmu_sel & ~iabort);       // 1 = DCACHE , 0 = ICACHE
406
        assign MMU_UPDATE[0] = mmu_sel;
407
 
408
        assign abort = DC_ABORT | iabort;
409
 
410
        // that is the end of String loops where interrupts are checked : 8'hC7 & 8'hCF
411 11 ns32kum
        assign string_ende = (phase_reg[7:4] == 4'hC) & (phase_reg[2:0] == 3'b111);      // attention : 8'hCF does not exist
412 9 ns32kum
 
413 11 ns32kum
        always @(posedge BCLK) if (PHASE_0 || string_ende) type_nmi <= nmi_flag;        // during processing kept stable
414 9 ns32kum
 
415
        assign svc_flag  = (OPREG[7:0] == 8'hE2) & valid[0];      // Vector  5 : 0101 , Illegal Vector  4 : 0100
416
        assign bpt_flag  = (OPREG[7:0] == 8'hF2) & valid[0];      // Vector  8 : 1000 , Undefined Vec. 10 : 1010
417
        assign flag_flag = (phase_reg  == 8'h89) & flag;                // Vector  7 - has an own state
418
        assign trac_flag = t2p & PSR[10];                                               // Vector  9 : 1001 , PSR[10] = P Bit , Pending Trace
419
        assign ovf_flag  = (ovf_pipe[3] & flag) | (ovf_pipe[1] & TRAPS[2]);             // Vector 13 : 1101
420
        assign dbg_flag  = dbg_trap | (dbg_s & PHASE_0);                // Vector 14 : 1110
421
 
422
        // abort + dvz_trap during a opcode, fpu_trap + ovf_flag + dbg_flag later
423
        assign abbruch  = abort | fpu_trap | dvz_trap | ovf_flag | dbg_flag;    // this 5 stop everything
424
        assign abbruch2 = abort | fpu_trap | dvz_trap | ovf_flag;       // for exc_vector generation
425
 
426
        // forces the next step of state machine (op_ok), generates otype="11" for Trap Service
427
        assign exception = interrupt | svc_flag | bpt_flag | ILL | UNDEF | trac_flag | abbruch;
428
 
429
        // a TRACE Exception is done before the opcode execution
430 11 ns32kum
        assign misc_vectors = trac_flag ? 4'h9 : {(bpt_flag | UNDEF),(svc_flag | ILL),UNDEF,svc_flag};  // the vectors are exclusiv
431 9 ns32kum
 
432
        always @(posedge BCLK)
433
                if (PHASE_0 || abbruch) // ABORTs, fpu_trap, dvz_trap + ovf_flag can happen every time
434
                  begin
435 11 ns32kum
                        exc_vector <= abbruch ? (abbruch2  ? {ovf_flag,(dvz_trap | ovf_flag),~ovf_flag,(fpu_trap | ovf_flag)} : 4'hE)
436 9 ns32kum
                                                                  : (interrupt ? {3'b0,nmi_flag} : misc_vectors);       // misc_vectors is default
437
                  end
438
                  else
439
                    if (flag_flag) exc_vector <= 4'h7;  // FLAG-Trap
440
                      else
441
                                if (interrupt && string_ende) exc_vector <= {3'b0,nmi_flag};
442
 
443 11 ns32kum
        assign psr_code[2] = ~psr_code[1];                                              // Absicht : codiert das Sichern des PSR bei Exception-Entry 
444
        assign psr_code[1] = abort | ILL | UNDEF | trac_flag;   // enable for reseting the P-Bit during write of PSR to stack
445 9 ns32kum
        assign psr_code[0] = (interrupt & ~fpu_trap) | abort;    // enable for reseting the I-Bit of new PSR
446
 
447
        // valid codes are x'89 to x'8F
448 11 ns32kum
        assign op_psr = {8'b0_00_1000_1,psr_code};      // is used during first clock cylce after exception, is transfered as OPCODE to I_PFAD
449 9 ns32kum
 
450 11 ns32kum
        // Specialitiies : ABORT stores address & flags , the Interrrupts read vectors : all is used in big CASE
451 9 ns32kum
        assign abo_int = (exc_vector == 4'h2) | (exc_vector[3:1] == 3'b000);
452
        assign ai_next = (exc_vector == 4'h2) ? {load_ea,8'h84,4'h0} : {rd_icu,8'h82,4'h1};
453
 
454 11 ns32kum
        assign save_pc = {7'b10_0010_0,dia_flag,7'b00_0_0000,dia_flag,3'b001};  // Exception : PC_ARCHI => EA, special case DIA
455
        assign no_trap = ~fpu_trap & ~ovf_flag & ~dbg_flag;     // suppresion of WREN and LD_OUT[1] and ADDR_UNIT operation
456 9 ns32kum
 
457
        // ++++++++++++++++++++++++++  Overflow Trap  ++++++++++++++
458
 
459
        always @(posedge BCLK)
460
                if (ovf_flag || !PSR[4]) ovf_pipe <= 4'd0;
461
                  else
462 11 ns32kum
                        if (PHASE_0) ovf_pipe <= {ovf_pipe[2],(ovf_op & op_ok),ovf_pipe[0],(ovf2_op & op_ok)};   // V-Bit switches on
463 9 ns32kum
 
464
        assign ovf_op =  ( ((OPREG[6:2] == 5'b000_11)   // ADDQi
465
                                          | (OPREG[3:2] == 2'b00)) & (OPREG[1:0] != 2'b10))              // ADDi,ADDCi,SUBi,SUBCi
466
                                        | ((OPREG[7:0] == 8'h4E) & OPREG[13] & (OPREG[11:10] == 2'b00))  // NEGi,ABSi
467
                                        | ((OPREG[7:0] == 8'hEE) & ~OPREG[10]);  // CHECKi
468
 
469 11 ns32kum
        assign ovf2_op =  ((OPREG[6:2] == 5'b100_11) & (OPREG[1:0] != 2'b10))    // ACBi, these overflows have no FLAG
470 9 ns32kum
                                        | ((OPREG[13:10] == 4'h1) & (OPREG[7:0] == 8'h4E))       // ASHi
471
                                        | ( OPREG[13] & (OPREG[11] == OPREG[10]) & (OPREG[7:0] == 8'hCE)); // MULi,DEIi,QUOi,DIVi
472
 
473
        // ++++++++++++++++++++++++++  Debug Trap  ++++++++++++++
474
 
475
        always @(posedge BCLK or negedge BRESET)
476
                if (!BRESET) dbg_s <= 1'b0;
477
                  else dbg_s <= dbg_trap | (dbg_s & ~((exc_vector == 4'hE) & (phase_reg == 8'h81)));
478
 
479
        always @(posedge BCLK) dbg_en <= op_ok | ~PHASE_0;
480
 
481
        assign pc_match = dbg_en & TRAPS[3] & PHASE_0 & ~exception;     // TRAPS[3] is only combinatorical
482
 
483 11 ns32kum
        always @(posedge BCLK) dbg_trap <= (pc_match | (addr_cmp & PHASE_0)) & TRAPS[5];        // TRAPS[5] = Enable Trap
484 9 ns32kum
 
485
        always @(posedge BCLK) addr_cmp <= TRAPS[4] | (addr_cmp & ~PHASE_0);    // TRAPS[4] = CAR HIT
486
 
487
        // ++++++++++++++++++++++++++  Special case String Abort  ++++++++++++++
488
 
489 11 ns32kum
        // Flags cleared if entry and exit of string operation and during  Abort sequence, not valid for MOVM/CMPM
490 9 ns32kum
        // special case UNTIL/WHILE : reset if exit (op_feld_reg[17] = 1 = UNTIL)
491 11 ns32kum
        assign clr_sflag =         (phase_reg == 8'hC0) | (phase_reg == 8'hC7) | (phase_reg == 8'hC8) | (phase_reg == 8'h81)
492 9 ns32kum
                                           | (((phase_reg == 8'hD7) | (phase_reg == 8'hDF)) & ~(STRING[3] ^ op_feld_reg[17])) ;
493
        assign set_src   =     (phase_reg == 8'hC1) | (phase_reg == 8'hC9);
494
        assign set_dest  =     (phase_reg == 8'hC4) | (phase_reg == 8'hCC);
495
 
496
        always @(posedge BCLK or negedge BRESET)        // R1 is modified
497
                if (!BRESET) ssrc_flag <= 1'b0;
498
                  else ssrc_flag <= (set_src & ~kurz_st) | (ssrc_flag & ~clr_sflag);
499
 
500
        always @(posedge BCLK or negedge BRESET)        // R2 is modified
501
                if (!BRESET) sdest_flag <= 1'b0;
502
                  else sdest_flag <= (set_dest & ~kurz_st) | (sdest_flag & ~clr_sflag);
503
 
504
        assign rrepa = {7'b1000_011,~sdest_flag};       // R1 and if necessary R2 restore
505
 
506
        // ++++++++++++++++++++++++++  The one byte opcodes  +++++++++++++++++++
507
 
508 11 ns32kum
        // The one byte opcodes have a special case : one byte opcode but the second byte should be valid too
509 9 ns32kum
        // Used with SAVE, RESTORE, ENTER and EXIT with their reg list. 
510
        // The advantage is that the reg list is store in op_feld_reg.
511
 
512
        //      [52:34] addressing
513
        //      [33:20] register
514
        //      [19:18] 1 or 2 Byte opcode
515
        //      [17:16] BSR/BR
516
        //       [15:8] next phase
517
        //        [7:4] START + LD_OUT
518
        //        [3:0] operand access : Displacement or Speicher
519
 
520
        always @(*)             // SVC (E2) and BPT (F2) decode as exception
521
                casex (OPREG[7:0])
522
                        8'hxA : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b01,8'h01,4'h0,4'hE};       // Bcc , DISP read
523
                        8'h02 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b10,8'h01,4'h0,4'hE};       // BSR , DISP read
524
                        8'h12 : op1_feld = {pop_op  , src_x, stack, 2'b01,2'b00,8'h2A,4'h0,4'h1};       // RET , DISP later
525
                        8'h22 : op1_feld = {rmod_4      , src_x, modul, 2'b01,2'b00,8'h35,4'h0,4'h1};   // CXP
526
                        8'h32 : op1_feld = {pop_op,   src_x, stack, 2'b01,2'b00,8'h40,4'h0,4'h1};       // RXP
527
                        8'h42 : op1_feld = {pop_op,       src_x, stack, 2'b01,2'b00,8'h46,4'h0,4'h1};   // RETT
528
                        8'h52 : op1_feld = {rd_icu,       src_x, src_x, 2'b01,2'b00,8'h45,4'h0,4'h1};   // RETI
529
                        8'h62 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h30,4'h0,4'h0};       // SAVE
530
                        8'h72 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h32,4'h0,4'h0};       // RESTORE
531
                        8'h82 : op1_feld = {push_op , frame, stack, 2'b10,2'b00,8'h2D,4'h2,4'h1};       // ENTER : PUSH FP
532
                        8'h92 : op1_feld = {addr_nop, src_x, src_x, 2'b10,2'b00,8'h32,4'h0,4'h0};       // EXIT : POP FP
533
                        8'hA2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h00,4'h0,4'h0};       // NOP
534
                        8'hB2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h88,4'h0,4'h0};       // WAIT
535
                        8'hC2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h88,4'h0,4'h0};       // DIA
536
                        8'hD2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h89,4'h0,4'h0};       // FLAG
537
                  default : op1_feld = {19'hxxxxx,14'hxxxx,     2'b00,2'b00,16'hxxxx};
538
                endcase
539
 
540 23 ns32kum
        assign op_1byte  = op1_feld[18] & valid[0];
541
        assign op_12byte = op1_feld[19] & valid[1];
542 9 ns32kum
 
543
        assign new_addr = op1_feld[52:34];
544
        assign new_regs = op1_feld[33:20];
545
        assign new_ph   = op1_feld[15:8];
546
        assign new_nx   = op1_feld[7:0]; // at Bcond DISP read
547
 
548
        assign pop_fp   = new_fp ? pop_op : addr_nop;
549
        assign ppfp             = new_fp ? 8'h34 : 8'h00;
550
 
551
        always @(posedge BCLK)
552
                if (PHASE_0)
553
                  begin
554
                        ex_br_op        <= op1_feld[17:16];     // BSR/BR
555
                        cc_feld         <= OPREG[7:4];
556
                        new_fp          <= (OPREG[7:6] == 2'b10);       // not decoded complete but is sufficient
557
                        reti_flag       <= OPREG[4];            // only difference between RETI and RETT is important
558
                        dia_op          <= OPREG[6];            // only difference between DIA and WAIT is important
559
                  end
560
 
561 11 ns32kum
        always @(posedge BCLK) dia_flag <= dia_op & (phase_reg == 8'h88);       // special case DIA compared to WAIT : Addr DIA to Stack
562 9 ns32kum
 
563 11 ns32kum
        always @(posedge BCLK)  // Format 1 opcodes write always DWord to reg, the same is true for Exceptions
564 9 ns32kum
                if (PHASE_0 || abbruch) format1 <= (valid[0] & (OPREG[3:0] == 4'h2)) | exception;
565
                  else
566
                        if (flag_flag || (interrupt && string_ende)) format1 <= 1'b1;
567
 
568
        //                                      Branch etc.                             CXP                                             CXPD
569 11 ns32kum
        assign store_pc = (phase_reg == 8'd1) | (phase_reg == 8'h37) | (phase_reg == 8'h6B);    // only save in DIN Reg of DATENPFAD
570 9 ns32kum
        assign jump = (ex_br_op[0] & branch) | (acb_reg & ~ACB_ZERO) | ex_br_op[1];
571
 
572 11 ns32kum
        always @(posedge BCLK) ldpc_phase <=  (phase_reg == 8'h3E)      // PC load at CXP/Traps , all one clock cycle guaranted
573 9 ns32kum
                                                                                | (phase_reg == 8'h43)  // PC load at RXP
574
                                                                                | ((phase_reg == 8'h49) & reti_flag)    // PC load at RETI
575 49 ns32kum
                                                                                | ((phase_reg == 8'h4E) & next) // PC load at RETT - here not one clock cycle guaranted
576 9 ns32kum
                                                                                | (phase_reg == 8'h66)  // PC load at JUMP/JSR/CASE
577
                                                                                | (phase_reg == 8'h7B); // PC load at DE = Direct Exception
578
 
579
        assign NEW = ((phase_reg == 8'd1) &  jump & di_stat[0]) | LOAD_PC;
580 11 ns32kum
        assign LOAD_PC = ((phase_reg == 8'h2B) & di_stat[0])     // only one pulse, but DISP must be ok => di_stat[0] (RET)
581 9 ns32kum
                                        | ldpc_phase;
582
 
583
        assign no_modul = de_flag ? {1'b0,dest_x} : {1'b1,modul[5:0]};
584
 
585
        assign negativ   = PSR[7];
586
        assign zero      = PSR[6];
587
        assign flag              = PSR[5];
588
        assign larger    = PSR[2];
589
        assign carry_psr = PSR[0];
590
 
591 11 ns32kum
        assign rett_exc = ~reti_flag & (phase_reg == 8'h4B);    // special case RETT : Stack can change during opcode
592 9 ns32kum
        always @(posedge BCLK) phase_exc <= (phase_reg == 8'h80);       // 1. Exception phase
593 11 ns32kum
        always @(negedge BCLK) if (PHASE_0 || phase_exc || rett_exc) s_user <= PSR[9];  // Select Bit for Stack, delayed update
594 9 ns32kum
        always @(negedge BCLK)
595
                if (PHASE_0 || phase_exc) s_mod <= {PSR[9],~PSR[9]};
596
                  else
597
                        if (rett_exc) s_mod <= s_mod | {PSR[9],~PSR[9]};        // Both can be updated
598
 
599
        always @(cc_feld or zero or carry_psr or larger or negativ or flag)
600
                case (cc_feld)
601
                  4'h0 : branch =  zero;                // EQual
602
                  4'h1 : branch = ~zero;                // Not Equal
603
                  4'h2 : branch =  carry_psr;   // Carry Set
604
                  4'h3 : branch = ~carry_psr;   // Carry Clear
605
                  4'h4 : branch =  larger;              // Higher
606
                  4'h5 : branch = ~larger;              // Lower or Same
607
                  4'h6 : branch =  negativ;             // Greater Than
608
                  4'h7 : branch = ~negativ;             // Less or Equal
609
                  4'h8 : branch =  flag;                // Flag Set
610
                  4'h9 : branch = ~flag;                // Flag Clear
611
                  4'hA : branch = ~larger  & ~zero;     // LOwer
612
                  4'hB : branch =  larger  |  zero;     // Higher or Same
613
                  4'hC : branch = ~negativ & ~zero;     // Less Than
614
                  4'hD : branch =  negativ |  zero;     // Greater or Equal
615
                  4'hE : branch = 1'b1;                 // True
616
                  4'hF : branch = 1'b0;                 // False
617
                endcase
618
 
619
        // +++++++++++++++++++++++  Register List Processing  ++++++++++++++++++++++++++++
620
 
621
        always @(posedge BCLK) init_rlist <= PHASE_0 | (phase_reg == 8'h2E);
622
 
623
        always @(posedge BCLK)
624
                if (PHASE_0) rpointer <= 3'b000;
625
                  else
626
                        if (ACC_DONE || init_rlist) rpointer <= reg_nr;
627
 
628 11 ns32kum
        REG_LIST scanner ( .DIN(op_feld_reg[22:15]), .INIT(init_rlist), .IPOS(rpointer), .VALID(save_reg), .OPOS(reg_nr) );
629 9 ns32kum
 
630
        assign saver = {4'h0,reg_nr};
631
 
632 11 ns32kum
        always @(posedge BCLK) if (ACC_DONE || init_rlist) resto <= {3'h0,~reg_nr};     // EXIT and RESTORE have the list mirrored : R0...R7
633 9 ns32kum
 
634 11 ns32kum
        // ++++++++++++++++++++++++++  Processing of Displacement and Immediate Operand  +++++++++++++++++++
635 9 ns32kum
 
636
        always @(posedge BCLK or negedge BRESET)        // Flag for DISP and IMME access
637
                if (!BRESET) dim_feld[3] <= 1'b0;
638
                  else dim_feld[3] <= next ? new_op[3] : ~di_stat[0] & dim_feld[3];
639
 
640
        always @(posedge BCLK) if (next) dim_feld[2:1] <= new_op[2:1];
641
 
642
        always @(posedge BCLK or negedge BRESET)        // Flag for external access
643
                if (!BRESET) dim_feld[0] <= 1'b0;
644
                  else dim_feld[0] <= next ? new_op[0] : ~ACC_DONE & dim_feld[0];
645
 
646
        // special case QWORD, last term for security
647
        always @(posedge BCLK) qw_flag <= dim_feld[0] & ACC_DONE & (ACC_FELD[13:12] == 2'b11) & ~qw_flag;
648
 
649 11 ns32kum
        assign LD_IMME = (dim_feld[3] & (dim_feld[2:1] != 2'b11)) | short_op | store_pc;        // Data multiplexer
650
        assign LD_DIN  =  (di_stat[0] & dim_feld[3] & (dim_feld[2:1] != 2'b11))                          // Enable for DIN Register
651
                                        | (ACC_DONE   & dim_feld[0]) | qw_flag | short_op | store_pc;            // next not possible : i.e. immediate and disp parallel
652 9 ns32kum
        assign ld_disp = (dim_feld[3:1] == 3'b111);                                                                                     // Enable for DISP Register
653
 
654
        // Signal to ADDR_UNIT , only Displacement critical
655
        assign disp_ok = ld_disp ? di_stat[0] : 1'b1;
656
 
657 11 ns32kum
        always @(dim_feld or OPREG or valid or ANZ_VAL) // Bit 0 is "Data ok", the upper 3 bits are for USED
658 9 ns32kum
                casex ({dim_feld[2:1],OPREG[7:6]})
659
                  4'b00_xx : di_stat = {3'b001,valid[0]};
660 23 ns32kum
                  4'b01_xx : di_stat = {3'b010,valid[1]};
661 9 ns32kum
                  4'b10_xx : di_stat = {3'b100,ANZ_VAL[2]};
662
                  4'b11_0x : di_stat = {3'b001,valid[0]};
663 23 ns32kum
                  4'b11_10 : di_stat = {3'b010,valid[1]};
664 9 ns32kum
                  4'b11_11 : di_stat = {3'b100,ANZ_VAL[2]};
665
                endcase
666
 
667
        always @(OPREG)
668
                casex (OPREG[7:6])
669
                  2'b0x : disp_val = {{26{OPREG[6]}},OPREG[5:0]};
670
                  2'b10 : disp_val = {{19{OPREG[5]}},OPREG[4:0],OPREG[15:8]};
671
                  2'b11 : disp_val = {{3{OPREG[5]}},OPREG[4:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
672
                endcase
673
 
674
        assign DISP_BR = disp_val;      // DISP is also used for Bcc opcode
675
 
676
        // The generator for DISP : data is used in ADDR_UNIT
677
        always @(*)
678
                casex ({ld_disp,disp_sel})      //      disp_sel from new_op
679
                  5'b1_00xx : DISP = disp_val;
680
                  5'b1_01xx : DISP = 32'h0 - disp_val;  // special case for ENTER
681
                  5'b1_1xxx : DISP = {disp_val[29:0],2'b00};     // DISP*4 for External Address Mode
682
                  5'b0_11xx : DISP = {20'hFFFFF,3'h7,type_nmi,8'h00};    // Interrupt Service Address
683
                  5'b0_1000 : DISP = 32'hFFFF_FFFF;             // PUSH Byte
684
                  5'b0_1001 : DISP = 32'hFFFF_FFFE;             // PUSH Word
685
                  5'b0_1010 : DISP = 32'hFFFF_FFFC;             // PUSH DWord
686
                  5'b0_1011 : DISP = 32'hFFFF_FFF8;             // PUSH QWord
687
                  5'b0_01xx : DISP = {26'h0,exc_vector,2'b00};          // the exception vector as Offset for INTBASE
688
                  5'b0_00xx : DISP = {28'h0,disp_sel[1:0],2'b00};        // 0,+4,+8,+12 used with MOD, default is 0
689
                endcase
690
 
691 23 ns32kum
        always @(*)
692 9 ns32kum
                casex ({short_op,dim_feld[2:1]})
693
                  3'b000 : imme_i = op_setcfg ? {28'h0000_00F,OPREG[2:0],setcfg_lsb} : {24'hxx_xxxx,OPREG[7:0]};
694
                  3'b001 : imme_i =    {16'hxxxx,OPREG[7:0],OPREG[15:8]};
695
                  3'b01x : imme_i = {OPREG[7:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
696 23 ns32kum
                  3'b1xx : imme_i = opt_imme ? {24'hxxxx_xx,opti_byte} : {{29{OPREG[10]}},OPREG[9:7]};  // for MOVQ etc. only OPREG can be used
697 9 ns32kum
                endcase
698
 
699
        assign IMME_Q = store_pc ? PC_SAVE : imme_i;
700
 
701
        // ++++++++++++++  Stack Control  +++++++++++++++++
702
 
703
        always @(posedge BCLK or negedge BRESET)
704
                if (!BRESET) new_spsel <= 1'b0;
705
                  else new_spsel <= spupd | (new_spsel & ~PHASE_0 & ~fpu_trap & ~dvz_trap);
706
 
707 11 ns32kum
        always @(posedge BCLK) upd_info <= PHASE_0 & new_spsel; // one clock cycle earlier a change occurs, i.e. ADDF TOS,F0 => fpu_trap
708 9 ns32kum
 
709
        assign do_xor = fpu_trap ? upd_info : (PHASE_0 & new_spsel);
710
 
711
        always @(negedge BCLK or negedge BRESET)
712
                if (!BRESET) stack_sel <= 2'b00;
713
                  else
714
                        if (do_xor) stack_sel <= stack_sel ^ s_mod;
715
 
716
        // Special case RETT
717 11 ns32kum
        always @(posedge BCLK) if (!phase_reg[1]) old_su <= s_user;     // is tested in state x'49 and used in x'4B
718 9 ns32kum
        assign ttstak = {1'b0,((old_su == PSR[9]) ^ stack_sel[PSR[9]]),3'b110,PSR[9],1'b1};
719
 
720
        // ++++++++++++++  2 byte opcodes  +++++++++++++++++
721
 
722
        // Hint : short_op is decoded separatly
723
 
724
        // [47:45]      Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
725
        // [44:42]      Destination : like [47:45]
726
        //        [41]  long opcode     [41:39] only for standard sequenz - not Gruppe 2
727
        //    [40]      src2_flag - Source 2 is read
728
        //        [39]  dest_flag - a target operand exists
729
        // [38:33]      src1_r Register field, no message about Immediate
730
        // [32:27]      src2_r Register field
731
        // [26:25]      src1_le Length of Source1 - this is used for qword
732
        // [24:23]      src2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE 
733
        // [22:18]      src1 field
734
        // [17:13]      src2 field
735
        // [12:11]      op_type 2 Bit for sort of opcode
736
        //    [10]      FL : F=1/L=0
737
        //   [9:8]      original BWD : B=00/W=01/D=11
738
        //   [7:0]      opcode: operation code
739
 
740 23 ns32kum
        assign valid_size = (OPREG[1:0] != 2'b10) & valid[1];    // valid size + valid OPREG-Bytes
741 9 ns32kum
 
742
        assign hzl_a = (OPREG[1:0] == 2'b11) ? 2'b10 : OPREG[1:0];        // length field recoded
743
        assign hzl_b = {1'b0,OPREG[1:0]};                // standard Length field
744
        assign hzr_a = {3'b000,OPREG[13:11]};   // SRC2 or SRC1 regfield
745
        assign hzr_b = {3'b000,OPREG[8:6]};             // SRC2 regfield
746 11 ns32kum
        assign hzr_s = {((OPREG[15:11] == 5'h17) ^ stack_sel[s_user]),3'b110,s_user,1'b1};      // USER or SUPERVISOR Stack, TOS special case
747 9 ns32kum
        // Special case LPR & SPR regfield:
748
        always @(OPREG or stack_sel or s_user)
749
                casex ({OPREG[10:7]})
750
                  4'b1001 : hzr_c = {stack_sel[s_user],3'b110,s_user,1'b1};     // USER or SUPERVISOR Stack
751
                  4'b1011 : hzr_c = {stack_sel[1]         ,3'b110,1'b1,  1'b1}; // USER Stack
752
                  4'b1100 : hzr_c = OPREG[6] ? temp_h : 6'h1C;  // CFG special case : LPR : SPR
753
                  default : hzr_c = {2'b01,OPREG[10:7]};
754
                endcase
755
 
756 11 ns32kum
        // Unfortunately SETCFG must be implemented : it is transformed to a two byte opcode with one byte IMM operand
757 23 ns32kum
        assign setcfg = (OPREG[13:0] == 14'h0B0E) & valid[1];
758 9 ns32kum
 
759
        always @(*)
760
          casex ({setcfg,OPREG[10:2]})
761
                // Short-Op Codes , ACB is an ADD with following jump
762 11 ns32kum
                10'b0xxxx_x0011 : op2_feld = {6'o11,3'o3,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h40};  // ADDQ ACB
763
                10'b0xxxx_00111 : op2_feld = {6'o11,3'o2,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h41};  // CMPQ
764
                10'b0xxxx_01011 : op2_feld = {6'o11,3'o1,hzr_c,hzr_a,hzl_a,hzl_a,5'h00,OPREG[15:11],2'b00,hzl_b,8'h45};  // SPR
765 9 ns32kum
                // Scond is moving the SHORT operand in the Integer area as condition field
766 11 ns32kum
                10'b0xxxx_01111 : op2_feld = {6'o11,3'o1,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h7A};  // Format 7, A=(UNDEF)
767
                10'b0xxxx_10111 : op2_feld = {6'o11,3'o1,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h45};  // MOVQ
768
                10'b0xxxx_11011 : op2_feld = {6'o11,3'o1,hzr_a,hzr_c,hzl_a,2'b10,OPREG[15:11],5'h00,2'b00,hzl_b,8'h76};  // LPR => MOVZiD
769 9 ns32kum
                // Format 3 opcodes :
770 11 ns32kum
                10'b00x10_11111 : op2_feld = {6'o11,3'o1,hzr_a,6'h1D,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b00,hzl_b,4'h3,OPREG[10:7]}; // BIC/SPSR
771
                10'b0x100_11111 : op2_feld = {6'o61,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // JUMP/JSR
772
                10'b01110_11111 : op2_feld = {6'o11,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // CASE
773 9 ns32kum
                // Format 4 opcodes : main group
774 11 ns32kum
                10'b0xxxx_xxxx0 : op2_feld = {6'o11,3'o3,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],            2'b00,hzl_b,4'h4,OPREG[5:2]};
775
                10'b0xxxx_x0001 : op2_feld = {6'o11,3'o2,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],            2'b00,hzl_b,4'h4,OPREG[5:2]}; //CMP no WR
776
                10'b0xxxx_x0101 : op2_feld = {6'o11,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],            2'b00,hzl_b,4'h4,OPREG[5:2]}; //MOV no 2.Op
777 9 ns32kum
                10'b0xxxx_x1101 : op2_feld = (OPREG[10:9] == 2'b00) ?    // target is Register => standard flow
778
                                                                         {6'o11,3'o2,hzr_a,hzr_b,hzl_a,2'bxx,OPREG[15:6],               2'b00,hzl_b,4'h4,OPREG[5:2]}    // TBIT
779
                                                                   : {6'o14,3'o2,hzr_a,hzr_b,hzl_a,2'b00,OPREG[15:6],           2'b10,hzl_b,4'h4,OPREG[5:2]};
780
                // ADJSPi
781 11 ns32kum
                10'b01010_11111 : op2_feld = {6'o11,3'o3,hzr_a,hzr_s,hzl_a,2'b10,OPREG[15:11],5'h00,2'b00,hzl_b,8'h48};  // is a SUBD
782 9 ns32kum
                // ADDR, length field not valid
783
                10'b0xxxx_x1001 : op2_feld = {6'o61,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],            2'b00,hzl_b,8'h49};
784 11 ns32kum
                10'b00000_11111 : op2_feld = {6'o71,3'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5'h00,2'b10,hzl_b,4'h3,OPREG[10:7]}; // CXPD no Opcode
785 9 ns32kum
                // SETCFG => MOV Befehl , SRC1 is genrated for 32 bit , target is Register temp_h
786
                10'b1xxxx_xxxxx  : op2_feld = {40'b001001_001_000000_111101_00_10_10100_00000_00_011,                     8'h76};
787
                default                 : op2_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
788
          endcase
789
 
790 11 ns32kum
        assign op_2byte = (valid_size | setcfg) & ~op2_feld[7]; // it must be for sure shown "Invalid Opcode"
791 9 ns32kum
 
792
        // Special case : the quick opcodes with the exception SPR and LPR
793 23 ns32kum
        assign short_op = ((((~OPREG[5]) | (OPREG[6:4] == 3'b011)) & (OPREG[3:2] == 2'b11) & valid_size) | opt_imme) & PHASE_0;
794 9 ns32kum
        always @(posedge BCLK) if (PHASE_0) short_op_reg <= short_op;
795
        assign short_def =  PHASE_0 ? short_op : short_op_reg;                                                  // for the big state machine
796 11 ns32kum
        assign op_sho = (OPREG[6:4] == 3'b011) ? 11'h07A : op_mov;      // Special case Scond at Index as Dest. , used only in Phase 0
797 9 ns32kum
 
798
        // 2. special case ACB
799
        assign acb_op = (OPREG[6:2] == 5'h13) & valid_size;
800
        always @(posedge BCLK) if (PHASE_0) acb_reg <= acb_op;
801
        assign acb_flag = PHASE_0 ? acb_op : acb_reg;
802 11 ns32kum
        assign goacb = acb_flag ? 8'h28 : 8'h00;        // x'28 = 40 , wait jump at REG operation - short-op special case
803 9 ns32kum
 
804 11 ns32kum
        // 3. special case load of PSR and Init-Done opcodes : because of U bit in PSR a restart must follow,
805 9 ns32kum
        // CINV and LMR PTB must wait until Init-Done and than Restart.
806
        // All variants of LPR and BIC/S have an extra cycle due to TRACE operation
807
        always @(OPREG)
808
                casex (OPREG[18:0])
809
                  19'bxxx_xxxxx_1101_110_11_xx : waitop = 9'h14C;       // LPRi PSR,...
810
                  19'bxxx_xxxxx_1100_110_11_xx : waitop = 9'h174;       // LPRi CFG,...
811
                  19'bxxx_xxxxx_0x10_111_11_xx : waitop = 9'h14C;       // BICPSRi/BISPSRi ...
812
                  19'bxxxx_x_0010_xx_0000_1110 : waitop = 9'h174;       // SETCFG []
813
                  19'bxxxx_0_0010_xx_0001_1110 : waitop = 9'h174;       // LMR  - at the end Restart
814
                  19'bxxxx_0_1001_xx_0001_1110 : waitop = 9'h174;       // CINV - at the end Restart
815
                  default                                          : waitop = 9'h000;
816
                endcase
817
 
818
        assign dowait = waitop[7:0];     // is used in Phase 0 if PSR is loaded from Register
819
        always @(posedge BCLK) if (PHASE_0) wait_reg <= waitop;
820
 
821
        // Here 2. and 3. special case are coming together:
822
        // Phase definition, end over jump for ACB , not used in Phase 0
823
        assign endea = acb_reg ? 8'h01 : (wait_reg[8] ? wait_reg[7:0] : 8'h00);
824
        assign diacb = acb_reg ? 4'hE : 4'h0;   // load Disp ?
825
 
826
        // special case ADJSPi : SP=SRC2 always 32 Bit
827
        always @(posedge BCLK)
828
                if (PHASE_0) dw_info <= (OPREG[10:2] == 9'b1010_11111);
829
                  else dw_info <= dw_info & ~phase_reg[7];      // for security at ABORT
830
 
831
        // SETCFG : Flag to transform the Byte Immeadiate operand
832
        always @(posedge BCLK) if (PHASE_0) op_setcfg  <= setcfg;
833
        always @(posedge BCLK) if (PHASE_0) setcfg_lsb <= OPREG[15];
834
 
835
        always @(posedge BCLK) if (PHASE_0) jsr_flag <= (OPREG[10:2] == 9'b1100_11111);         // JSR : for PUSH
836
        always @(posedge BCLK)  // Bit opcodes to Register and EXT:SRC1 / INS:SRC2
837 11 ns32kum
                if (PHASE_0) bit_reg  <= ((OPREG[3] ? ((OPREG[7:6] == 2'd0) ? OPREG[23:22] : OPREG[18:17]) : OPREG[10:9]) == 2'b00);
838 23 ns32kum
        always @(posedge BCLK) if (PHASE_0) exin_cmd <= (~OPREG[10] & (OPREG[6:0] == 7'h2E)) & valid[2];
839 9 ns32kum
        always @(posedge BCLK) if (PHASE_0) extract <= ~OPREG[7];
840 23 ns32kum
        always @(posedge BCLK) if (PHASE_0) inss_op <= (OPREG[13:10] == 4'h2) & (OPREG[7:0] == 8'hCE) & valid[2];        // INSS
841 9 ns32kum
 
842
        // ++++++++++++++  3 byte opcodes  +++++++++++++++++
843
 
844
        // [47:45]      Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
845
        // [44:42]      Destination : like [47:45]
846
        //        [41]  long opcode     [41:39] only for standard sequenz - not Gruppe 2
847
        //    [40]      src2_flag - Source 2 is read
848
        //        [39]  dest_flag - a target operand exists
849
        // [38:33]      src1_r Register field, no message about Immediate
850
        // [32:27]      src2_r Register field
851
        // [26:25]      src1_le Length of Source1 - this is used for qword
852
        // [24:23]      src2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE 
853
        // [22:18]      src1 field
854
        // [17:13]      src2 field
855
        // [12:11]      op_type 2 Bit for sort of opcode
856
        //    [10]      FL : F=1/L=0
857
        //   [9:8]      original BWD : B=00/W=01/D=11
858
        //   [7:0]      opcode: operation code
859
 
860
        assign hdx_a = OPREG[7] ? OPREG[8] : OPREG[10];
861
        assign hdo_a = OPREG[13:10];
862
        assign hdo_c = {1'b0,OPREG[10],OPREG[7:6]};     // Format 8 opcodes
863
        assign hdo_d = {6'b0101_00,OPREG[10],1'b0};     // CMPM/S or MOVM/S : 8'h52 or 8'h50
864
        assign hdo_e = {3'b011,OPREG[10]};      // Special codes for LOGB and SCALB due to DP_OUT datapath
865
        // Definitions of length
866
        assign hdl_a = {1'b0,OPREG[9:8]};       // i size, is used in OPER
867 11 ns32kum
        assign hdl_b = (OPREG[9:8] == 2'b11) ? 2'b10 : OPREG[9:8];      // recode length field, is used in ACC field
868 9 ns32kum
        assign hdl_c = OPREG[10:8];                     // FL + BWD
869
        assign hdl_d = {1'b1,~hdx_a};           // length FP
870
        assign hdl_e = {OPREG[8],2'bxx};        // BWD don't care
871 11 ns32kum
        assign hdl_f = (OPREG[18:17] == 2'b00) ? OPREG[9:8] : {OPREG[8],~(OPREG[9] ^ OPREG[8])};        // exclusiv for DEI
872 9 ns32kum
        assign hdl_g = {(OPREG[9:8] != 2'b00),(OPREG[9:8] == 2'b00)};   // exclusiv for EXT/EXTS base operand
873
        assign hdl_h = {(OPREG[9:8] != 2'b00),(OPREG[9:8] != 2'b01)};   // exclusiv for CHECK bound operand
874
        // Register definitions
875
        assign hdr_a = {3'b000,OPREG[21:19]};   // SRC1 Integer Register
876
        assign hdr_b = {3'b000,OPREG[16:14]};   // SRC2 Integer Register
877
        assign hdr_c = hdx_a ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
878
        assign hdr_d = hdx_a ? {2'b10,OPREG[16:15],1'b0,OPREG[14]} : {2'b10,OPREG[16:14],1'b1};
879
        assign hdr_e = OPREG[11] ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
880
        assign hdr_f = OPREG[11] ? {2'b10,OPREG[16:14],1'b1}               : {2'b10,OPREG[16:15],1'b0,OPREG[14]};
881 23 ns32kum
        assign hdr_g = {3'b000,OPREG[16:15],~OPREG[14]};        // exclusiv for DEI and MEI
882 9 ns32kum
        assign hdr_m = {3'b001,OPREG[17:15]};   // MMU Register Index 8-15
883
 
884
        always @(*)
885
                casex (OPREG[13:3])
886 11 ns32kum
                  11'b1000_xx_1100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a};     // MULi
887
                  11'b000x_xx_0100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, 2'b00,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a};     // ROTi,ASHi
888
                  11'b0101_xx_0100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, 2'b00,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a};     // LSHi
889
                  11'b1x0x_xx_0100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a};     // NEGi,NOTi,ABSi,COMi
890
                  11'b010x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b01,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a};     // MOVX/ZiW
891
                  11'b011x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a};     // MOVX/ZiD
892
                  11'b0001_xx_0110x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b00,hdl_a,4'h8,hdo_c};     // FFSi
893 9 ns32kum
        // Floating Point opcodes
894 23 ns32kum
                  11'b000x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_a,hdr_d, hdl_b,hdl_d,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a};     // MOVif
895
                  11'b010x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_e,hdr_f, 2'b11,2'b10,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a};     // MOVLF
896
                  11'b011x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_e,hdr_f, 2'b10,2'b11,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a};     // MOVFL
897
                  11'b10xx_xx_0011x : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a};     // ROUNDi,TRUNCi
898
                  11'b111x_xx_00111 : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a};     // FLOORi
899
                  11'b111x_xx_00110 : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,op_cop};         // SEARCH
900
                  11'b0x00_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // ADDf,SUBf
901
                  11'bxx00_0x_10110 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop};         // Coprocessor
902
                  11'b1000_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // DIVf
903
                  11'b1100_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // MULf
904
                  11'b0010_0x_1011x : op3_feld = {6'o11,3'o6,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // CMPf
905
                  11'b0001_0x_10111 : op3_feld = {6'o11,3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // MOVf
906
                  11'bx101_0x_10111 : op3_feld = {6'o11,3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a};     // NEGf,ABSf
907
                  11'b001x_11_00111 : op3_feld = {6'o11,3'o1,hdr_a,fsr_r, 2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h92};      // LFSR
908
                  11'b110x_11_00111 : op3_feld = {6'o11,3'o1,fsr_r,hdr_b, 2'b10,2'b10,5'b0,OPREG[18:14],2'b00,3'o3,8'h9C};      // SFSR
909 9 ns32kum
        // MMU opcodes
910 11 ns32kum
                  11'b0010_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00, 3'o3,8'h45};     // LMR
911
                  11'b0011_11_0001x : op3_feld = {6'o11,3'o1,hdr_m,hdr_a, 2'b10,2'b10,5'b0,OPREG[23:19],2'b00, 3'o3,8'h45};     // SMR
912 9 ns32kum
        // String opcodes
913 11 ns32kum
                  11'b000x_xx_0000x : op3_feld = {6'o11,3'o0,6'hxx,6'hxx, 2'bxx,2'b10,OPREG[23:14],     2'b10,hdl_c,hdo_d};     // MOVS,CMPS
914
                  11'b0011_xx_0000x : op3_feld = {6'o11,3'o0,6'hxx,6'hxx, 2'bxx,2'b10,OPREG[23:14],     2'b10,hdl_c,hdo_d};     // SKPS
915 9 ns32kum
        // Custom opcodes
916 23 ns32kum
                  11'bxx01_0x_10110 : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop};
917 9 ns32kum
        // Integer Divisionen : QUOi REMi DIVi MODi and DEIi + MEIi
918 11 ns32kum
                  11'b11xx_xx_1100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a};
919
                  11'b10x1_xx_1100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_g, hdl_b,hdl_f,OPREG[23:14],2'b10,hdl_a,4'h7,hdo_a};     // DEI/MEI
920 9 ns32kum
        // Gruppe 2 opcodes
921 11 ns32kum
                  11'b0x11_xx_1010x : op3_feld = {6'o77,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,8'h45};          // MOVUS,MOVSU
922
                  11'b000x_xx_1100x : op3_feld = {6'o66,3'o0,hdr_a,hdr_b, 2'bxx,2'b10,OPREG[23:14],2'b10,hdl_c, hdo_d};         // MOVM/CMPM
923 14 ns32kum
                  11'b001x_0x_1111x : op3_feld = {6'o11,3'o2,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b10,hdl_e,4'hC,hdo_a};     // DOTf,POLYf
924 11 ns32kum
                  11'b0101_0x_1111x : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e};     // LOGB
925 23 ns32kum
                  11'b0100_0x_1111x : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e};     // SCALB
926 11 ns32kum
                  11'b0011_xx_1100x : op3_feld = {6'o50,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h7,hdo_a};     // EXTS
927 14 ns32kum
                  11'bxxx0_xx_1110x : op3_feld = {6'o71,3'o2,hdr_a,hdr_b, hdl_h,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c};     // CHECK
928 9 ns32kum
                  11'b0x1x_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ?      // target is register => standard flow
929
                                                                                 {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}      // SBIT/CBIT
930
                                                                           : {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
931
                  11'b1110_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ?      // target is register => standard flow
932
                                                                                 {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}      // IBIT
933
                                                                           : {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
934 23 ns32kum
                  11'b1x11_xx_0100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,3'd0,OPREG[12]}; // ADDP,SUBP
935 11 ns32kum
                  11'bxxx0_xx_0010x : op3_feld = {6'o40,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // EXT
936
                  11'bxxx0_xx_1010x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // INS
937
                  11'b0010_xx_1100x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_a}; // INSS
938
                  11'bxxx0_xx_0110x : op3_feld = {6'o61,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // CVTP no Opcode
939 14 ns32kum
                  11'bxxx1_xx_0010x : op3_feld = {6'o11,3'o2,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b10, 3'o3,8'h84};          // INDEX
940 11 ns32kum
        // Gruppe 2 opcodes can have dedicated operation codes. Therefore the operation code definition here is "don't care"
941
                  11'b000x_xx_0001x : op3_feld = {6'o70,3'o0,hdr_a,hdr_b, 2'b00,2'b10,OPREG[23:19],5'b0,2'b10,3'o0,8'h45};      // RDVAL+WRVAL 
942
                  11'b1001_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h45};      // CINV
943 9 ns32kum
 
944
                  default                   : op3_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
945
                endcase
946
 
947 23 ns32kum
        assign op_3byte = valid[2] & (OPREG[2:0] == 3'b110) & (op3_feld[7:4] != 4'hA);   // valid for all incl. CUSTOM
948 9 ns32kum
 
949
        // +++++++++++++  Evaluation for 2 and 3 byte opcodes  ++++++++++++++++++
950
 
951
        // for one byte opcodes special treatmant neccessary
952
        assign opc_bits = op_3byte ? op3_feld : op2_feld;
953
 
954 11 ns32kum
        assign op_ok = (op_1byte | op_12byte | op_2byte | op_3byte | exception) & ~stop;        // used for computation of USED
955 9 ns32kum
 
956
        always @(posedge BCLK) if (PHASE_0) op_feld_reg <= opc_bits;
957
        assign op_feld = PHASE_0 ? opc_bits : op_feld_reg;      // constant for all following cycles
958
 
959
        // Evaluation of op_feld :
960
 
961
        assign atys              = op_feld[47:45];      // [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory
962
        assign atyd              = op_feld[44:42];      // [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory
963
        assign long              = op_feld[41];
964
        assign src2_flag = op_feld[40];
965
        assign dest_flag = op_feld[39];
966
 
967
        assign src_1    = {1'b0,op_feld[38:33]};
968
        assign src_2    = {1'b0,op_feld[32:27]};
969
        assign src1_le  = op_feld[26:25];
970
        assign src2_le  = op_feld[24:23];
971 11 ns32kum
        assign acc1     = (op_feld[22:21] != 2'b00) | atys[1];  // external access Source1 or "addr" : Reg => (Reg)
972
        assign acc2     = (op_feld[17:16] != 2'b00) | atyd[1];  // external access Source2 or "addr" : Reg => (Reg)
973 9 ns32kum
        assign wlor             = dest_flag & ~acc2;
974 11 ns32kum
        assign idx_n    = {1'b0,(op_feld[22:20] == 3'b111)} + {1'b0,(op_feld[17:15] == 3'b111)};        // Index : 0,1 or 2
975 9 ns32kum
        assign idx              = (idx_n != 2'b00);     // Index is active
976
        assign n_idx    = idx_n - 2'b01;
977
 
978
        // The field otype is used only in Phase 0
979 11 ns32kum
        assign otype    = exception ? 2'b11 : ((op_1byte | op_12byte) ? 2'b01 : opc_bits[12:11]);       // string opcodes use code 2'b10
980 9 ns32kum
 
981
        assign opera    = op_feld[10:0];
982
 
983
        assign dest_r   = src_2[5:0];
984
        assign dest_rl  = {dest_r[5:1],1'b0};
985
 
986 23 ns32kum
        // ++++++++++++++++++++++++++++ Immediate Optimization +++++++++++++++++++++++++++++++++++
987
 
988
        //                                              3               Byte                                    Immediate
989
        assign opt_imme =  (valid[2] & (OPREG[1:0] == 2'd0) & (OPREG[15:11] == 5'b10100) &
990
        //                                                       ADD,ADDC,SUB,SUBC,BIC,OR,AND,XOR               CMP                                     MOV
991
                                                ( ((OPREG[10:8] != 3'b111) & (~OPREG[2] | (OPREG[5:2] == 4'h1) | (OPREG[5:2] == 4'h5))) // not ADDR und TBIT
992
                                                 |((OPREG[6:2] == 5'b11111) & (OPREG[8:7] == 2'b10) & (OPREG[10:9] != 2'b11)))) // BICPSR,BISPSR,ADJSP and ~CASE
993
        //                                              4                       not Scaled Index                        Immediate
994
                                         | (ANZ_VAL[2] & (OPREG[18:16] != 3'b111) & (OPREG[23:19] == 5'b10100) &
995
                                                ( ((OPREG[7:0] == 8'h4E) & ~OPREG[13] & ~OPREG[11])              // ROT,ASH,LSH but not NEG,NOT,ABS,COM
996
                                                 |((OPREG[7:0] == 8'hCE) & (OPREG[13:12] == 2'b01) & (OPREG[9:8] == 2'd0))));    // MOVX/ZBi
997
 
998
        assign opti_byte = (OPREG[1:0] == 2'b10) ? OPREG[31:24] : OPREG[23:16];
999
 
1000 9 ns32kum
        // +++++++++++++++++++++++++  Coprocessor operations field  ++++++++++++++++++++++++++++++
1001
 
1002
        always @(posedge BCLK) if (PHASE_0) COP_OP <= OPREG[23:0];
1003
 
1004
        // +++++++++++++++++++++++++  Special signals for LMR and CINV  ++++++++++++++++++++++++++
1005
        // op_lmr is constant = parameter
1006
 
1007
        assign STOP_IC  = (phase_reg == 8'h74) | (phase_reg == 8'h75);
1008
 
1009
        // CINV uses Register x'30 - x'37 :  CINV = 110... , LMR = 001... otherwise CFG
1010 11 ns32kum
        always @(posedge BCLK) if (PHASE_0) lmrreg <= op_3byte ? {{2{OPREG[13]}},~OPREG[13],OPREG[17:15]} : 6'h1C;
1011 9 ns32kum
 
1012 11 ns32kum
        always @(posedge BCLK) no_init <= (lmrreg[5:4] == 2'b00) & (lmrreg[3:1] != 3'b110);     // LMR waits for INIT at PTB0/1
1013 9 ns32kum
        // a_ivar = "Addresse IVAR0/1"
1014 11 ns32kum
        always @(posedge BCLK) a_ivar  <= STOP_IC;      // Phase 74 & 75, is used at INFO_AU together with IC_READ
1015 9 ns32kum
 
1016
        // CINV detection for IC_CACHE
1017
        always @(posedge BCLK)
1018
                if (PHASE_0) cinv_flag <= OPREG[13] & (OPREG[7:0] == 8'h1E);
1019
                        else cinv_flag <= cinv_flag & ~phase_reg[7];    // reset at exception
1020
 
1021
        assign ENA_HK = ~(cinv_flag & STOP_IC); // always "1", if CINV then "0" 
1022
 
1023
        // +++++++++++++++++++++++++  USER flag for MOVUS & MOVSU  ++++++++++++++++++++++++
1024
 
1025
        always @(posedge BCLK)
1026
                if (PHASE_0) m_ussu <= (~OPREG[13] & (OPREG[11:10] == 2'b11) & (OPREG[7:0] == 8'hAE));
1027
                        else m_ussu <= m_ussu & ~phase_reg[7];  // reset at exception
1028
 
1029
        always @(posedge BCLK) if (PHASE_0) m_usel <= OPREG[12];
1030
 
1031
        // +++++++++++++++++++++++++  USER flag for RDVAL & WRVAL  ++++++++++++++++++++++++
1032
 
1033
        always @(posedge BCLK)
1034
                if (PHASE_0) rwval_flag <= (OPREG[13:11] == 3'd0) & (OPREG[7:0] == 8'h1E);
1035
                        else rwval_flag <= rwval_flag & ~phase_reg[7];  // reset at exception
1036
 
1037
        always @(posedge BCLK) if (PHASE_0) wrval_flag <= OPREG[10];    // Difference RDVAL=0 and WRVAL=1
1038
 
1039
        // +++++++++++++++++++++++++  Flags for CBIT/I+SBIT/I+IBIT  +++++++++++++++++++++++
1040
 
1041 11 ns32kum
        assign rw_bit = (op_feld_reg[7:4] == 4'd6) & ((~op_feld_reg[3] & op_feld_reg[1]) | (op_feld_reg[3:0] == 4'hE));
1042 9 ns32kum
        assign op_ilo = rw_bit & op_feld_reg[0]; // Interlocked : CBITI and SBITI
1043
 
1044
        // +++++++++++++++++++++++++++++  Operations for String processing  +++++++++++++++++
1045
        // Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
1046
 
1047 11 ns32kum
        assign st_src   = {STRING[1:0],5'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1000};        // [15] = BACKWARD
1048
        assign st_src2  = {STRING[1:0],5'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1011};        // Reuse EA
1049
        assign st_dest  = {STRING[1:0],5'b0110_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9'b0_0000_1011};        // Reuse EA
1050
        assign st_trde  = {2'b00,      5'b0110_0, op_feld_reg[15],            2'b00,      9'b0_0000_1000};      // after Translate to Dest
1051
        assign st_trs2  = {STRING[1:0],5'b1010_0, op_feld_reg[15],            STRING[1:0],9'b0_0000_1000};        // after Match to SRC2
1052 9 ns32kum
        assign st_len   = {STRING[1:0],17'b0000_0000_0_0000_0000};       // length important for qw_flag
1053
 
1054
        // Signals of DETOIP go to I_PFAD
1055 11 ns32kum
        always @(posedge BCLK) if (PHASE_0) kill_opt <= ~OPREG[7] & (OPREG[17:15] != 3'b000);   // watch difference of MOVM and MOVS
1056 9 ns32kum
        assign ph_match = (phase_reg[7:4] == 4'hD) & (phase_reg[2:0] == 3'd7);   // Phase D7 and DF
1057
 
1058
        assign op_str   = {op_feld_reg[10:8],6'b0101_00,op_feld_reg[1],1'b1}; // Opcode 8'h51 or 8'h53;
1059
        assign op_scp   = {op_feld_reg[10:8],8'h41};    // normal CMPi
1060
        assign ph_str   = {4'hC,op_feld_reg[1],3'b001}; // Phase 8'hC1 (MOVS/M) or 8'hC9 (CMPS/M)
1061
 
1062 11 ns32kum
        always @(posedge BCLK) kurz_st <= (phase_reg == 8'h65) | (kurz_st & ~PHASE_0);                  // Flag for MOVM/CMPM
1063
        always @(posedge BCLK) if (PHASE_0) cmps_flag <= ~OPREG[7] & (OPREG[11:10] == 2'b01);   // Flag for CMPS
1064
        always @(posedge BCLK) if (PHASE_0) skps_flag <= ~OPREG[7] & (OPREG[11:10] == 2'b11);   // Flag for SKPS
1065
        always @(posedge BCLK) if (PHASE_0) mt_flag <= ~OPREG[7] & (OPREG[17] | OPREG[15]);             // Flag for Match and Translate
1066 9 ns32kum
 
1067
        assign wstr0    = {{4{kurz_st}},2'b00};
1068
        assign wstr1    = {{4{kurz_st}},2'b01};
1069
        assign wstr2    = {{4{kurz_st}},2'b10};
1070
        assign rstr0    = {1'b0,wstr0};
1071
        assign rstr1    = {1'b0,wstr1};
1072
        assign rstr2    = {1'b0,wstr2};
1073
 
1074
        // +++++++++++++++++++++++++++++++++++  Index processing  +++++++++++++++++++++++++++++++++++++++++
1075
 
1076
        assign phase_idx = (phase_reg == 8'h02) | (phase_reg == 8'h50);
1077
 
1078
        assign idx_bytes = idx_1[2] ? OPREG[15:0] : {OPREG[7:0],OPREG[7:0]};       // here last access of OPREG
1079
        always @(posedge BCLK) if (phase_idx) idx_reg <= idx_bytes;
1080
        assign idx_feld = (phase_idx) ? idx_bytes : idx_reg;
1081
 
1082
        // +++++++++++++++++++++++++++++++++++  The big state machine  ++++++++++++++++++++++++++++++++++++
1083
 
1084
        // Hints :
1085
        // 1. At short-op SRC1 is out of memory to use TEMP
1086
        // 2. At SRC2 rmw suppresed TOS and changed it to (SP)
1087
        // 3. The Long-operation path takes the dest_r address to write if WR_REG activ
1088 11 ns32kum
        // 4. It is ok, that an extra cycle for the read of the index registers is needed - then data could be written ins Out register
1089 9 ns32kum
 
1090
        // Source 1
1091
 
1092
        assign idx_1 = {1'b0,(op_feld[22:20] == 3'b111),op_feld[19:18]};
1093
        assign src1_addr = idx_1[2] ? idx_feld[7:3] : op_feld[22:18];
1094
        assign stack  = {1'b0,stack_sel[s_user],3'b110,s_user,1'b1};
1095
        assign usp_1  = src1_addr[0] ? stack : {5'b0_0110,src1_addr[1:0]};
1096
        assign src_1l = {src_1[6:1],1'b0};
1097
        assign pop_1  = {2'b00,src1_le,9'h108}; // SP update, DISP=0 and POST
1098 11 ns32kum
        assign mpoi_1 = (src1_addr[4:2] == 3'b100) | (src1_addr == 5'h16);      // Pointer in memory always DWord
1099 9 ns32kum
        assign auop_s = atys[0] ? 4'b1011 : 4'b0010;     // Only make effective address ?
1100 14 ns32kum
        assign src1_tos = (op_feld[22:18] == 5'h17) & ~atys[2] ? 2'b11 : 2'b00; // Source 1 is true TOS
1101 9 ns32kum
 
1102
        // Nextfield : 11=DISP read
1103
        // Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
1104
        always @(*)
1105
                casex (src1_addr)       //       RWLF   IDX    ADDR_F NEUP  SRC_REG                   NEXT
1106 11 ns32kum
                  // Special case which is only valid at INDEX or "addr" : REG -> ADDR , DISP=0 : starts immediate at read
1107 9 ns32kum
                  5'b00xxx : gen_src1 = {auop_s, idx_1,9'h000,8'h07,4'h0,src1_addr[2:0],3'b000,atys[0]};
1108
                  // Register relativ : 0(R0)
1109
                  5'b01xxx : gen_src1 = {auop_s, idx_1,9'h000,8'h07,4'h0,src1_addr[2:0],3'b111,atys[0]};
1110
                  // Memory relativ : 0(0(SB))
1111 11 ns32kum
                  5'b100xx : gen_src1 = {4'b1011,4'h0, 9'h000,8'h06,usp_1,                        4'b1111};                     // 1. access always full
1112 9 ns32kum
                  // Immediate
1113
                  5'b10100 : gen_src1 = (src1_le == 2'b11) ?
1114
                                                                {4'h0,   4'h0, 9'h000,8'h0B,src_x,                        1'b1,2'b10,1'b0}      // load in DWord pieces
1115
                                                          : {4'h0,   4'h0, 9'h000,8'h07,src_x,                    1'b1,src1_le,1'b0};
1116 11 ns32kum
                  5'b10101 : gen_src1 = {auop_s, idx_1,9'h002,8'h07,src_x,                        3'b111,atys[0]};       // Absolut Addressing
1117
                  5'b10110 : gen_src1 = {4'b1011,4'h0, 9'h014,8'h05,7'h1F,                        4'b0001};                     // External with MOD Register +4
1118 9 ns32kum
                  5'b10111 : gen_src1 = (idx_1[2] | atys[2]) ?                                                                                  // Access class "addr" ?
1119
                                                                {auop_s, idx_1,9'h000,8'h07,stack,                        3'b000,atys[0]}        // 0(SP) : no TOS flag
1120
                                                          : {4'b1011,pop_1,       8'h07,stack,                    4'b0001};                     // TOS
1121
                  // Memory Space : 0(SB)
1122 11 ns32kum
                  5'b110x0 : gen_src1 = {auop_s, idx_1,9'h000,8'h07,5'b0_0110,src1_addr[1:0],3'b111,atys[0]};     // SB+FP
1123 9 ns32kum
                  5'b11001 : gen_src1 = {auop_s, idx_1,9'h000,8'h07,stack,                        3'b111,atys[0]};       // SP
1124
                  5'b11011 : gen_src1 = {auop_s, idx_1,9'h001,8'h07,src_x,                        3'b111,atys[0]};       // PC relativ
1125
                  default  : gen_src1 = 36'hx_xxxx_xxxx;        // don't care
1126
                endcase
1127
 
1128
        assign adrd1 = {(mpoi_1 ? 2'b10 : src1_le),gen_src1[35:19]};    // Addressfield : 19 Bits
1129
        assign phrd1 = gen_src1[18:11];                                 // next phase
1130
        assign rega1 = gen_src1[10:4];                                  // Source 1 Register
1131
        assign irrw1 = {4'b0,idx_feld[2:0]};                     // Index-Register
1132
        assign nxrd1 = gen_src1[3:0];                                    // Memory/Disp/Immediate operation
1133
        assign exr11 = {2'b10  ,4'b1011,4'h0 ,9'h080};  // 2. access external with Mem.-Pointer + 4* Disp
1134
        assign exr12 = {src1_le,auop_s,idx_1,9'h000};   // for Memory Relative and EXT in last step
1135
 
1136
        // Source 2 resp. Destination
1137
 
1138
        assign rmw = src2_flag & dest_flag;
1139
        assign idx_2 = {1'b0,(op_feld[17:15] == 3'b111),op_feld[14:13]};        // 4 bits
1140
        assign src2_addr = idx_2[2] ? idx_feld[15:11] : op_feld[17:13];
1141
        assign usp_2 = src2_addr[0] ? stack : {5'b0_0110,src2_addr[1:0]};
1142
        assign src_2l = {src_2[6:1],1'b0};
1143 11 ns32kum
        assign mpoi_2 = (src2_addr[4:2] == 3'b100) | (src2_addr == 5'h16);      // Pointer in memory always DWord
1144 9 ns32kum
        assign auop_d = atyd[0] ? 4'b1011 : 4'b0010;     // Only make effective address ?
1145
 
1146
        // The next assessment processes TOS separated for PUSH and POP
1147
        assign tos_oper =                       src2_flag ?
1148 11 ns32kum
                                                                {2'b00,atyd[0],2'b01,atyd[0],2'b00,src2_le,7'b1_0000_10,   src1_tos,4'h7,stack,3'b0,atyd[0]}       // POP
1149
                                                          : {1'b0,atyd[0],3'b001,atyd[0],4'h0,   1'b1,2'b10,src2_le,2'b0,src1_tos,4'h7,stack,3'b0,atyd[0]};        // PUSH
1150 9 ns32kum
 
1151
        // Nextfield : 11=DISP read
1152
        // Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
1153
        always @(*)
1154
                casex (src2_addr)       //       RW:W  RW:R  LF    IDX   ADDR_F NEUP   SRC_REG          NEXT
1155 11 ns32kum
                  // Special case which is only valid at INDEX or "addr" : REG -> ADDR , DISP=0 : starts immediate at read
1156
                  5'b00xxx : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h000,4'h7,4'h0,src2_addr[2:0],3'b000,atyd[0]};
1157 9 ns32kum
                  // Register relativ : 0(R0)
1158 11 ns32kum
                  5'b01xxx : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h000,4'h7,4'h0,src2_addr[2:0],3'b111,atyd[0]};
1159 9 ns32kum
                  // Memory relativ : 0(0(SB))
1160 11 ns32kum
                  5'b100xx : gen_src2 = {2'b10,2'b10,2'b11,4'h0, 9'h000,4'h6,usp_2,             4'b1111};       // 1. access always full
1161 9 ns32kum
                  // Immediate
1162
                  5'b10100 : gen_src2 = (src2_le == 2'b11) ?
1163
                                                                {2'b00,2'b00,2'b00,4'h0, 9'h000,4'hB,src_x,             1'b1,2'b10,1'b0}        // load in DWord pieces
1164
                                                          : {2'b00,2'b00,2'b00,4'h0, 9'h000,4'h7,src_x,         1'b1,src2_le,1'b0};
1165 11 ns32kum
                  5'b10101 : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h002,4'h7,src_x,               3'b111,atyd[0]}; // Absolut with special coding
1166
                  5'b10110 : gen_src2 = {2'b10,2'b10,2'b11,4'h0, 9'h014,4'h5,7'h1F,             4'b0001};       // External with MOD Register +4
1167 9 ns32kum
                  5'b10111 : gen_src2 = (idx_2[2] | rmw | atyd[2]) ?
1168 11 ns32kum
                                                                {1'b0,atyd[0],auop_d, idx_2,7'b0_0000_00,src1_tos,4'h7,stack,    3'b000,atyd[0]}  // 0(SP) : TOS + DISP=0
1169 9 ns32kum
                                                          : tos_oper;   // TOS : 2 cases for PUSH and POP
1170
                  // Memory Space
1171 11 ns32kum
                  5'b110x0 : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h000,4'h7,5'b0_0110,src2_addr[1:0],3'b111,atyd[0]};
1172 9 ns32kum
                  5'b11001 : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h000,4'h7,stack,               3'b111,atyd[0]};
1173 11 ns32kum
                  5'b11011 : gen_src2 = {1'b0,atyd[0],auop_d,     idx_2,9'h001,4'h7,src_x,               3'b111,atyd[0]}; // PC relativ
1174 9 ns32kum
                  default  : gen_src2 = 34'hx_xxxx_xxxx;        // don't care
1175
                endcase
1176
 
1177
        assign adrd2 = {(mpoi_2 ? 2'b10 : src2_le),gen_src2[31:15]};
1178
        assign adwr2 = {(mpoi_2 ? 2'b10 : src2_le),gen_src2[33:32],gen_src2[29:15]};
1179
        assign phrd2 = {4'h1,gen_src2[14:11]};                          // Phase for Read Source 2
1180
        assign phwr2 = {4'h2,gen_src2[14:11]};                          // Phase for Write Destination
1181
        assign rega2 = gen_src2[10:4];
1182
        assign nxrw2 = gen_src2[3:0];
1183
        assign irrw2 = {4'b0,idx_feld[10:8]};
1184
        assign re_wr = {src2_le,4'b0101,4'h0, 9'h003};          // REUSE Address : Write of rmw
1185 11 ns32kum
        assign exr22 = {src2_le,atyd[0],1'b0,1'b1,atyd[0],idx_2,9'h000};  // for Memory Relative and EXT in last step
1186
        assign exw22 = {src2_le,1'b0,atyd[0],1'b1,atyd[0],idx_2,9'h000};  // for Memory Relative and EXT in last step
1187 9 ns32kum
 
1188
        // Special case :
1189
 
1190
        assign quei1 = acc1 ? imme : src_1l;    // 8B passing either from register or from extern
1191
        // 8B is requested from both operands but only to certain times
1192
        assign qword = (phase_reg[7:4] != 4'h0) ? (src2_le == 2'b11) :  (src1_le == 2'b11);
1193
        assign quet1 = acc1 ? temp_h : src_1;   // select source during calculation
1194
 
1195
        // Output data of state machine 
1196
        //                                                      LOAD if  PULS if        simple
1197
        //                                      NEXT -> ENABLE   ENABLE         out
1198
        //  [66:48] 19  ADDR :                  X                                               ; Op-length REUSE RD/WR etc.
1199
        //      [47:40]  8      new phase               X
1200
        //      [39:33]  7      SRC1                                                    X
1201
        //      [32:26]  7      SRC2                                                    X
1202
        //         [25]  1      WREN                                    X
1203
        //      [24:19]  6      DEST                    X
1204
        //       [18:8] 11      OPER                    X
1205
        //        [7:6]  2      START                                   X
1206
        //        [5:4]  2      LD_OUT                                  X
1207
        //      [3]  1  ID Load                 X
1208
        //        [2:1]  2      ID Type                 X                                               ; 0 = DISP
1209
        //              [0]  1  MEM Access              X
1210
 
1211
        // State         acc2-src2_flag-dest_flag
1212
        // no SRC2      x               0                x
1213
        // SRC2=REG             0                1               0        ; CMP+TBIT
1214
        // SRC2=REG             0                1               1       ; all else
1215
        // SRC2=MEM             1               1               0        ; CMP+TBIT
1216
        // SRC2=MEM             1               1               1       ; all else
1217
 
1218
        // Input data for state machine
1219
 
1220
        //      8 phase_reg :   phase of state machine
1221
        //      2 otype :               Opcode type
1222
 
1223
        //      1 idx :                 Index is available : 1 or 2 , only PHASE_0
1224
        //      1 short_op :    short opcodes like ADDQ
1225
        //      1 long :                "long" opcode
1226
        //      1 qword :               8B access at Source (Exception DEI+MEI)
1227
 
1228
        //      1 acc1 :                Reg/Extern SRC1
1229
        //      1 acc2 :                Reg/Extern SRC2
1230
        //      1 src2_flag :   the 2. operand is being read
1231
        //      1 dest_flag :   there is a target operand : only CMP and TBIT have none
1232
 
1233
        assign phase_ein = abbruch ? 8'h00 : phase_reg;
1234
 
1235
        always @(*)             //                 "_"                                           "_"
1236
                casex ({phase_ein,otype, idx,short_def,long,qword, acc1,acc2,src2_flag,dest_flag})
1237 11 ns32kum
 {8'h00,10'b00_1xxx_xxxx}:       // Index must be loaded : phase 2 : in any case load TEMP for Short-Op and generate LD_OUT
1238 9 ns32kum
                                                        new_op = short_op ?     //                                                                                      START LD_OUT
1239
                                                                         {addr_nop,8'h02, imme, src_x, 1'b1,temp_h,             op_sho, 2'b00,2'b10,    1'b1,n_idx,1'b0}
1240
                                                                   : {addr_nop,8'h02, src_1,src_1l,1'b0,dest_x,         opera,  2'b00,~src2_flag,2'b1_1,n_idx,1'b0};
1241
 {8'h00,10'b00_01xx_x0xx}:       // Short-Op to register, LD_OUT because of CMPQ
1242
                                                        new_op = {addr_nop,goacb, imme, src_2,dest_flag,dest_r, opera,  2'b00,2'b10,    4'h0};
1243
 {8'h00,10'b00_01xx_x11x}:       // Short-Op : external operand read : SRC2 ! Data in TEMP ! Here no Index
1244
                                                        new_op = {adrd2,   phrd2, imme, rega2, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    nxrw2};
1245
 {8'h00,10'b00_01xx_x10x}:       // MOVQ to Mem
1246
                                                        new_op = {adwr2,   phwr2, imme, rega2, 1'b0,dest_x,             opera,  2'b00,2'b10,    nxrw2};
1247
 {8'h00,10'b00_0000_00xx}:       // simple register operation : dest_flag controls WREN, LD_OUT for CMP
1248
                                                        new_op = {addr_nop,dowait,src_1,src_2, dest_flag,dest_r,opera,  2'b00,2'b10,    4'h0};
1249
 {8'h00,10'b00_0001_00xx}:       // "simple" Reg-Op of 8B, phase 8 after 2. DWord , not via LONG-path
1250
                                                        new_op = {addr_nop,8'h08, src_1,src_x, 1'b1,dest_r,             opera,  2'b00,2'b00,    4'h0};
1251
 {8'h00,10'b00_0010_00xx}:       // long register operation i.e. DIV - phase 31
1252
                                                        new_op = {addr_nop,8'h1F, src_1,src_2, wlor,dest_r,             opera,  2'b11,2'b00,    4'h0};
1253
 {8'h00,10'b00_0011_001x}:       // long register operation with QWORD - phase 26 then wait
1254
                                                        new_op = {addr_nop,8'h1A, src_1,src_2, 1'b0,dest_r,             opera,  2'b01,2'b00,    4'h0};
1255
 {8'h00,10'b00_00xx_1xxx}:       // Source 1 in memory - first to read , here no Index
1256
                                                        new_op = {adrd1,   phrd1, src_x,rega1, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrd1};
1257
 {8'h00,10'b00_00xx_011x}:       // Source 2 in memory - first to read (Source 1 in register)
1258
                                                        new_op = {adrd2,   phrd2, src_x,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1259
 {8'h00,10'b00_0000_0101}:       // Source 1 store in Dest : "pass through" for MOV,NEG,ABS
1260
                                                        new_op = {adwr2,   phwr2, src_1,rega2, 1'b0,dest_x,             opera,  2'b00,2'b10,    nxrw2};
1261 11 ns32kum
 {8'h00,10'b00_0001_0101}:       // Source 1 store in Dest : "pass through" for MOV,NEG,ABS for Long operands
1262
                                                        new_op = //(op_feld[17:13] == 5'h17) ?  // TOS : special case , first 8B out of Reg and then read SP
1263 9 ns32kum
                                                                         {addr_nop,8'h1C, src_1,src_1l,1'b0,dest_x,             opera,  2'b00,2'b11,    4'h0};
1264
 {8'h00,10'b00_0010_0101}:       // SRC1 -> DEST with short operands 
1265
                                                        new_op = {addr_nop,8'h1F, src_1,src_x, 1'b0,dest_r,             opera,  2'b11,2'b00,    4'h0};
1266
 {8'h00,10'b00_0011_0x01}:       // SRC1 -> DEST i.e. ROUNDLi
1267
                                                        new_op = {addr_nop,8'h1F, src_1,src_1l,wlor,dest_r,             opera,  2'b11,2'b00,    4'h0};
1268
 
1269
                // Phase 2 : after read of Index nearly everything is repeated from PHASE_0
1270
 {8'h02,10'bxx_x1xx_x11x}:       // Short-Op : external operand read
1271
                                                        new_op = {adrd2,   phrd2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1272
 {8'h02,10'bxx_x1xx_x101}:       // MOVQ to Mem, data is in Out-Register
1273
                                                        new_op = {adwr2,   phwr2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1274
 {8'h02,10'bxx_x0xx_1xxx}:       // Source 1 in memory - first to read
1275
                                                        new_op = {adrd1,   phrd1, irrw1,rega1, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrd1};
1276
 {8'h02,10'bxx_x0xx_011x}:       // Source 2 in memory - first to read
1277
                                                        new_op = {adrd2,   phrd2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1278 11 ns32kum
 {8'h02,10'bxx_x00x_0101}:       // Source 1 store in Dest : "pass through" , data is already in Out-Register
1279 9 ns32kum
                                                        new_op = {adwr2,   phwr2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1280
 {8'h02,10'bxx_x010_0101}:       // SRC1 -> DEST with short operands
1281
                                                        new_op = {addr_nop,8'h1F, src_1,src_x, 1'b0,dest_x,             opera,  2'b11,2'b00,    4'h0};
1282
 {8'h02,10'bxx_x011_0101}:       // SRC1 -> DEST i.e. ROUNDLi 
1283
                                                        new_op = {addr_nop,8'h1F, src_1,src_1l,1'b0,dest_x,             opera,  2'b11,2'b00,    4'h0};
1284
 
1285
        // +++++++++++++++++  SRC1 operand loading  +++++++++++++++++++
1286
 
1287
                // Phase 5 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
1288
                //              next phase fix : 6
1289 11 ns32kum
 {8'h05,10'bxx_xxxx_xxxx}:       new_op = {exr11,   8'h06, src_x,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    4'b1111};
1290 9 ns32kum
                // Phase 6 : Memory-Pointer for Memory Relative and last access External
1291
                //              next phase fix : 7 , add Index
1292 11 ns32kum
 {8'h06,10'bxx_xxxx_xxxx}:       new_op = {exr12,   8'h07, irrw1,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    3'b111,atys[0]};
1293 9 ns32kum
 
1294
                // Phase 7 : wait for final data , direct from PHASE_0 if TOS without Index
1295
                //              next phase : if 8B data phase 8 is neccessary
1296
                // if SRC2=REG execution started (otherwise store data in TEMP) and PHASE_0
1297 11 ns32kum
 {8'h07,10'bxx_xx00_x0xx}:       // into Register , short operation execution , but LD_OUT for PSR Update ! dest_flag => WREN
1298 9 ns32kum
                                                        new_op = {addr_nop,endea, imme, src_2, dest_flag,dest_r,opera,  2'b00,2'b10,    diacb};
1299
 {8'h07,10'bxx_xx01_x0xx}:       // into Reg but with a step om between for ABSL etc. : phase 8
1300
                                                        new_op = {addr_nop,8'h08, imme, src_x, 1'b1,dest_r,             opera,  2'b00,2'b00,    4'h0};
1301
 {8'h07,10'bxx_xx10_x0xx}:       // execute long operation , wait in phase 31
1302
                                                        new_op = {addr_nop,8'h1F, imme, src_2, wlor,dest_r,             opera,  2'b11,2'b00,    4'h0};
1303 11 ns32kum
 {8'h07,10'bxx_xx11_xx0x}:       // execute long operation : 2. operand only Dest , load LSD , phase 24 , wait in phase 31
1304 9 ns32kum
                                                        new_op = {addr_nop,8'h18, imme, src_x, 1'b1,temp_l,             op_mov, 2'b01,2'b00,    4'h0};
1305
 {8'h07,10'bxx_xx11_x01x}:       // lange Operation ausfuehren , LSD laden , phase 25 , warten in phase 31
1306
                                                        new_op = {addr_nop,8'h19, imme, src_2, 1'b0,dest_r,             opera,  2'b01,2'b00,    4'h0};
1307
 {8'h07,10'bxx_xxx0_x11x}:       // Data into TEMP , read 2. operand , is there Index ? Yes -> phase 15
1308
                                                        new_op = idx_2[2] ?
1309
                                                                         {addr_nop,8'h0F, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0}
1310
                                                                   : {adrd2,   phrd2, imme, rega2, 1'b1,temp_h,         op_mov, 2'b00,2'b00,    nxrw2};
1311 11 ns32kum
 {8'h07,10'bxx_xxx1_x11x}:       // 8B data in TEMP , step in between then 2. Op read : phase 10 - can only be "long" operation
1312 9 ns32kum
                                                        new_op = {addr_nop,8'h0A, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0};
1313
 {8'h07,10'bxx_xx00_x101}:       // something like ABSi , execute and store (LD_OUT)
1314
                                                        new_op = idx_2[2] ?
1315
                                                                         {addr_nop,8'h10, imme, src_x, 1'b0,dest_x,             opera,  2'b00,2'b10,    4'h0}
1316
                                                                   : {adwr2,   phwr2, imme, rega2, 1'b0,dest_x,         opera,  2'b00,2'b10,    nxrw2};
1317 11 ns32kum
 {8'h07,10'bxx_xx01_x101}:       // ABS etc. : LSD data over SRC2 in 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9
1318 9 ns32kum
                                                        new_op = {addr_nop,8'h09, imme, src_x, 1'b0,dest_x,             opera,  2'b00,2'b10,    4'h0};
1319
 {8'h07,10'bxx_xx10_x101}:       // opcodes like MOVFL
1320
                                                        new_op = {addr_nop,8'h1F, imme, src_x, 1'b0,dest_x,             opera,  2'b11,2'b00,    4'h0};
1321
 
1322
                // Phase 8 : 2. part of 64 bit data : can be reached from PHASE_0 if 8B data
1323 11 ns32kum
 {8'h08,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,endea, quei1,src_x, 1'b1,dest_rl,    op_mov, 2'b00,2'b00,    diacb};
1324 9 ns32kum
                // Phase 9 : step in between to get data in OUT-Reg Low , SRC1 is not possible
1325
 {8'h09,10'bxx_xxxx_xxxx}:       // afterwards to data write
1326
                                                        new_op = {addr_nop,8'h10, src_x,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b01,    4'h0};
1327
                // Phase 10 : LSD data write in TEMP , source can be IMME data to
1328
 {8'h0A,10'bxx_xxxx_xxxx}:       // 8B , after TEMP there can only be a 2. operand
1329
                                                        new_op = idx_2[2] ?
1330
                                                                         {addr_nop,8'h0F, imme, src_x, 1'b1,temp_l,             op_mov, 2'b00,2'b00,    4'h0}
1331
                                                                   : {adrd2,   phrd2, imme, rega2, 1'b1,temp_l,         op_mov, 2'b00,2'b00,    nxrw2};
1332
 
1333
                // Phase 11 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure "1"
1334
 {8'h0B,10'bxx_xx0x_x0xx}:       // into Reg with step in between for ABSL etc. : phase 12
1335
                                                        new_op = {addr_nop,8'h0C, imme, src_x, 1'b1,dest_r,             opera,  2'b00,2'b00,    4'b1100};
1336
 {8'h0B,10'bxx_xx1x_x01x}:       // execute long operation , load LSD , phase 25 , wait in phase 31
1337
                                                        new_op = {addr_nop,8'h19, imme, src_2, 1'b0,dest_r,             opera,  2'b01,2'b00,    4'b1100};
1338 11 ns32kum
 {8'h0B,10'bxx_xxxx_x11x}:       // 8B data into TEMP , step in between then read 2. Op : phase 10 - can only be "long" operation
1339 9 ns32kum
                                                        new_op = {addr_nop,8'h0A, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'b1100};
1340 11 ns32kum
 {8'h0B,10'bxx_xx0x_x10x}:       // ABS etc. : LSD data via SRC2 into 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9
1341 9 ns32kum
                                                        new_op = {addr_nop,8'h09, imme, src_x, 1'b0,dest_x,             opera,  2'b00,2'b10,    4'b1100};
1342 11 ns32kum
 {8'h0B,10'bxx_xx1x_xx0x}:       // MOVLF with 8B IMME data ? Must be possible, the end in phase 24 like SRC1=MEM
1343 9 ns32kum
                                                        new_op = {addr_nop,8'h18, imme, src_x, 1'b1,temp_l,             op_mov, 2'b01,2'b00,    4'b1100};
1344
                // Phase 12 : wait for 2. part of 64 bit IMME data : after phase 0
1345 11 ns32kum
 {8'h0C,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,endea, imme ,src_x, 1'b1,dest_rl,    op_mov, 2'b00,2'b00,    diacb};
1346 9 ns32kum
 
1347
                // Phase 15 : secure in TEMP with Index continue and read 2. operand
1348 11 ns32kum
 {8'h0F,10'bxx_xxxx_xxxx}:       new_op = {adrd2,   phrd2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1349 9 ns32kum
                // Phase 16 : after LD_OUT continue with Index and store 1. operand
1350 11 ns32kum
 {8'h10,10'bxx_xxxx_xxxx}:       new_op = {adwr2,   phwr2, irrw2,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1351 9 ns32kum
 
1352
        // +++++++++++++++++  SRC2 operand loading : phase SRC1 + 16  +++++++++++++++++++
1353
 
1354
                // Phase 21 : wait for data and Disp2 for external addressing : part 2 EA = (MOD+4)+4*DISP1
1355
                //              next phase fix : 22
1356 11 ns32kum
 {8'h15,10'bxx_xxxx_xxxx}:       new_op = {exr11,   8'h16, src_x,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    4'b1111};
1357 9 ns32kum
                // Phase 22 : Memory-Pointer for Memory Relative and last access external
1358
                //              next phase fix : 23 , add Index
1359 11 ns32kum
 {8'h16,10'bxx_xxxx_xxxx}:       new_op = {exr22,   8'h17, irrw2,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    3'b111,atyd[0]};
1360 9 ns32kum
 
1361
                // Phase 23 : wait for final data , direct from PHASE_0 if TOS without Index
1362
                //              next phase : if 8B data phase 24 is used
1363 11 ns32kum
 {8'h17,10'bxx_xx0x_xxx1}:       // execute short operation and write data into memory , no WREN -> phase 39 ACC_DONE
1364 9 ns32kum
                                                        new_op = {re_wr,   8'h27, quet1,imme , 1'b0,dest_r,             opera,  2'b00,2'b10,    4'b0001};
1365
 {8'h17,10'bxx_xx0x_xxx0}:       // execute short operation , no WREN -> phase 0 , CMP(+TBIT)
1366
                                                        new_op = {addr_nop,endea, quet1,imme , 1'b0,dest_r,             opera,  2'b00,2'b10,    diacb};
1367
 {8'h17,10'bxx_xx10_xxxx}:       // execute long operation , wait in phase 31
1368
                                                        new_op = {addr_nop,8'h1F, quet1,imme , wlor,dest_r,             opera,  2'b11,2'b00,    4'h0};
1369
 {8'h17,10'bxx_xx11_xxxx}:       // execute long operation , load LSD in phase 24
1370
                                                        new_op = {addr_nop,8'h18, quet1,imme , 1'b0,dest_r,             opera,  2'b01,2'b00,    4'h0};
1371 11 ns32kum
                // Phase 24 : load 2. part of 64 bit data : with and without wait - from 28 the phase waits , from 23 not
1372 9 ns32kum
 {8'h18,10'bxx_xxxx_0xxx}:       // execute long operation , wait in phase 31
1373
                                                        new_op = {addr_nop,8'h1F, src_1l,imme, wlor,dest_r,             opera,  2'b10,2'b00,    4'h0};
1374 11 ns32kum
 {8'h18,10'bxx_xxxx_1xxx}:       // execute long operation , wait in phase 31 , data from TEMP, used also for ROUNDLi
1375 9 ns32kum
                                                        new_op = {addr_nop,8'h1F, rtmpl,imme,  wlor,dest_r,             opera,  2'b10,2'b00,    4'h0};
1376
                // Phase 25 : load 2. part of 64 bit data : SRC1 from memory and SRC2 from Reg
1377
 {8'h19,10'bxx_xxxx_xxxx}:       // execute long operation , wait in phase 31
1378
                                                        new_op = {addr_nop,8'h1F, imme, src_2l,wlor,dest_r,             opera,  2'b10,2'b00,    4'h0};
1379
                // Phase 26 : load 2. part of 64 bit data : SRC1 from Reg and SRC2 from Reg
1380
 {8'h1A,10'bxx_xxxx_xxxx}:       // execute long operation , wait in phase 31
1381
                                                        new_op = {addr_nop,8'h1F, src_1l,src_2l,wlor,dest_r,    opera,  2'b10,2'b00,    4'h0};
1382
 
1383
                // Phase 27 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure "1"
1384
 {8'h1B,10'bxx_xxxx_xxxx}:       // execute long operation , load LSD in phase 24
1385
                                                        new_op = {addr_nop,8'h18, quet1,imme , 1'b0,dest_r,             opera,  2'b01,2'b00,    4'b1100};
1386
 
1387
        // +++++++++++++++++  special case  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1388
                // Phase 28 : TOS with 8B SRC1 operand , no Index ! Jump to phase 39
1389
 {8'h1C,10'bxx_xxxx_xxxx}:       // store Source 1 in Dest : "pass through" for MOV,NEG,ABS
1390
                                                        new_op = {adwr2,   phwr2, src_x,rega2, 1'b0,dest_x,             opera,  2'b00,2'b00,    nxrw2};
1391
        // +++++++++++++++++  close operation : write out DEST , TOS update  +++++++++++++++++++
1392
 
1393
                // Phase 31 : wait for DONE of long operation
1394
 {8'h1F,10'bxx_xxxx_xxx0}:       // CMP done -> phase 0
1395
                                                        new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r,             opera,  2'b00,2'b10,    4'h0};  // no ACB
1396
 {8'h1F,10'bxx_xxxx_x0x1}:       // operation closed , data into register
1397
                                                        new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r,             opera,  2'b00,2'b00,    4'h0};  // no ACB
1398 11 ns32kum
 {8'h1F,10'bxx_xxxx_x101}:       // operation closed , data into memory - first calculate address phase 32+x
1399 23 ns32kum
                                                        new_op = {adwr2,   phwr2, irrw2,rega2, 1'b0,dest_r,             opera,  2'b00,2'b10,    nxrw2};
1400 9 ns32kum
 {8'h1F,10'bxx_xxxx_x111}:       // operation closed , data into memory - address reuse phase 39 ACC_DONE
1401 23 ns32kum
                                                        new_op = {re_wr,   8'h27, src_x,src_x, 1'b0,dest_r,             opera,  2'b00,2'b10,    4'b0001};
1402 9 ns32kum
 
1403
                // Destination address calculate
1404
                // Phase 37 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
1405
                //              next phase fix : 38
1406 11 ns32kum
 {8'h25,10'bxx_xxxx_xxxx}:       new_op = {exr11,   8'h26, src_x,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    4'b1111};
1407 9 ns32kum
                // Phase 38 : Memory-Pointer for Memory Relative and letzter Zugriff External
1408
                //              next phase fix : 39 , add Index and write
1409 11 ns32kum
 {8'h26,10'bxx_xxxx_xxxx}:       new_op = {exw22,   8'h27, irrw2,imme , 1'b0,dest_x,             opera,  2'b00,2'b00,    4'b1111};
1410 9 ns32kum
 
1411
                // Phase 39 : wait for ACC_DONE : consequent numbering : 7+32
1412
 {8'h27,10'bxx_xxxx_xxxx}:       // now operation closed , only ACB could follow
1413
                                                        new_op = {addr_nop,endea, src_x,src_x, 1'b0,dest_x,             opera,  2'b00,2'b00,    diacb};
1414
 
1415
        // +++++++++++++++ special case : ACB to Reg is to fast ! One wait cycle for ZERO-Flag
1416 11 ns32kum
 {8'h28,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h01,src_x, src_x, 1'b0,dest_x,             opera,  2'b00,2'b00,    4'b1110};
1417 9 ns32kum
 
1418
        // +++++++++++++++  The other opcodes are following  ++++++++++++++++++
1419
 
1420 11 ns32kum
 {8'h00,10'b01_xxxx_xxxx}:       new_op = {new_addr,new_ph,new_regs,        1'b0,dest_x,         op_mov,                                 new_nx};        // 1 Byte Opcodes
1421 9 ns32kum
 
1422
                // Phase 1 : used for Bcond and ACB :
1423
 {8'h01,10'bxx_xxxx_xxxx}:       new_op = (ex_br_op[1] | jsr_flag) ?     // BSR or JSR ?
1424
                                                                         {push_op, 8'h27, imme, stack, 1'b0,dest_x,             op_mov, 2'b00,2'b10,    4'b0001}        // wait at end
1425
                                                                   : {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x,         op_mov, 2'b00,2'b00,    4'h0};
1426
 
1427
                // Phase 42 : RET : read of PC from Stack and DIN via SRC1 to PC
1428 11 ns32kum
 {8'h2A,10'bxx_xxxx_xxxx}:  new_op = {adddisp, 8'h2B, imme, src_x, 1'b0,dest_x,          op_mov, 2'b00,2'b00,    4'hE};
1429
                // Phase 43 : RET : Displacement add to Stack. Attention : "imme" important to keep source constant for PC
1430
 {8'h2B,10'bxx_xxxx_xxxx}:  new_op = {save_sp, 8'h2C, imme, src_x, 1'b0,dest_x,          op_mov, 2'b00,2'b00,    4'h0};
1431 9 ns32kum
                // Phase 44 : RET : Update of Stack : fixed phase
1432 11 ns32kum
 {8'h2C,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h0};
1433 9 ns32kum
 
1434
                // Phase 45 : ENTER Entry
1435 11 ns32kum
 {8'h2D,10'bxx_xxxx_xxxx}:       new_op = {dispmin, 8'h2E, src_x,src_x, 1'b1,temp_l,             op_adr, 2'b00,2'b00,    4'hE};
1436 9 ns32kum
                // Phase 46 : ENTER Stack longer
1437 11 ns32kum
 {8'h2E,10'bxx_xxxx_xxxx}:       new_op = {save_sp ,8'h31, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h0};
1438 9 ns32kum
                // Phase 48 : SAVE/ENTER : Init phase , phases 48 & 49 very similar
1439
 {8'h30,10'bxx_xxxx_xxxx}:       new_op = save_reg ?
1440
                                                                         {push_op, 8'h31, saver,stack, 1'b0,dest_x,             op_mov, 2'b00,2'b10,    4'h1}   // 1. load SP=>EA
1441 11 ns32kum
                                                                   : {addr_nop,8'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov,      2'b00,2'b00,    4'h0};  // At ENTER FP Update
1442 9 ns32kum
                // Phase 49 : SAVE/ENTER : at the same time memory access and detection of next Reg
1443
 {8'h31,10'bxx_xxxx_xxxx}:       new_op = save_reg ?
1444
                                                                         {push_ea, 8'h31, saver,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b10,    4'h1}   // one more
1445 11 ns32kum
                                                                   : {addr_nop,8'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov,      2'b00,2'b00,    4'h0};  // At ENTER FP Update
1446 9 ns32kum
 
1447
                // Phase 50 : RESTORE/EXIT Entry
1448
 {8'h32,10'bxx_xxxx_xxxx}:       new_op = save_reg ?
1449
                                                                         {pop_op,  8'h33, src_x,stack, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1}
1450
                                                                   : {pop_fp,  ppfp,  src_x,frame, 1'b0,dest_x,         op_mov, 2'b00,2'b00,    3'h0,new_fp};
1451
                // Phase 51 : RESTORE/EXIT next reg
1452
 {8'h33,10'bxx_xxxx_xxxx}:       new_op = save_reg ?
1453
                                                                         {next_po, 8'h33, imme, src_x, 1'b1,resto,              op_mov, 2'b00,2'b00,    4'h1}
1454
                                                                   : {pop_fp,  ppfp,  imme, frame, 1'b1,resto,          op_mov, 2'b00,2'b00,    3'h0,new_fp};
1455
                // Phase 52 : EXIT End
1456 11 ns32kum
 {8'h34,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h00, imme, src_x, 1'b1,frame[5:0],  op_mov, 2'b00,2'b00,    4'h0};
1457 9 ns32kum
 
1458
                // Phase 53 : CXP Entry : this opcode needs 12 States and 16 cycles minimum ...
1459 11 ns32kum
 {8'h35,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h36, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0};
1460 9 ns32kum
                // Phase 54 : CXP : Store Address Link table
1461 11 ns32kum
 {8'h36,10'bxx_xxxx_xxxx}:       new_op = {rdltab,  8'h37, src_x,rtmph, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'hE};  // EA Phase : DISP read
1462 9 ns32kum
                // Phase 55 : CXP : DISP is worked on, the return address => temp_l
1463 11 ns32kum
 {8'h37,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h38, imme, rtmph, 1'b1,temp_l,             op_mov, 2'b00,2'b00,    4'h1};  // Access
1464 9 ns32kum
                // Phase 56 : CXP : Access to Link table => Result is MOD-Entry => store in temp_h
1465 11 ns32kum
 {8'h38,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h39, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0};
1466 9 ns32kum
                // Phase 57 : CXP : store and PUSH MOD prepare , Entry from Exception Processing
1467 11 ns32kum
 {8'h39,10'bxx_xxxx_xxxx}:       new_op = {push_op, 8'h3A, modul,stack, 1'b0,dest_x,             op_wrp, 2'b00,2'b10,    4'h1};
1468 9 ns32kum
                // Phase 58 : CXP : PUSH of MOD ongoing, PUSH PC prepare
1469 11 ns32kum
 {8'h3A,10'bxx_xxxx_xxxx}:       new_op = {ea_push, 8'h3B, rtmpl,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b10,    4'h0};
1470 9 ns32kum
                // Phase 59 : CXP : New EA for PC
1471 11 ns32kum
 {8'h3B,10'bxx_xxxx_xxxx}:       new_op = {save_sp, 8'h3C, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1};
1472 9 ns32kum
                // Phase 60 : CXP : write of PC, calculate of Offset
1473 11 ns32kum
 {8'h3C,10'bxx_xxxx_xxxx}:       new_op = {rmod_8,  8'h3D, rtmph,rtmph, 1'b1,temp_l,             op_flip,2'b00,2'b00,    4'h1};
1474 9 ns32kum
                // Phase 61 : CXP : read from (MOD:New+8)
1475 11 ns32kum
 {8'h3D,10'bxx_xxxx_xxxx}:       new_op = {ea_min8, 8'h3E, imme, rtmpl, 1'b1,temp_l,             op_add, 2'b00,2'b00,    4'h0};  // Reuse of EA
1476 9 ns32kum
                // Phase 62 : CXP : EA Phase of SB read , new PC calculated
1477 11 ns32kum
 {8'h3E,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h3F, rtmpl,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1};
1478 9 ns32kum
                // Phase 63 : CXP : read of SB , new PC to ICache
1479 11 ns32kum
 {8'h3F,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h2F, imme, src_x, 1'b1,6'h1A,              op_mov, 2'b00,2'b00,    4'h0};  // SB load
1480 9 ns32kum
                // Phase 47 : CXP : Last phase update of MOD prepare
1481 11 ns32kum
 {8'h2F,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h00, rtmph,src_x, 1'b1,modul[5:0],  op_mov, 2'b00,2'b00,    4'h0};  // MOD load
1482 9 ns32kum
 
1483
                // Phase 64 : RXP Entry : POP of PC , full Access
1484 11 ns32kum
 {8'h40,10'bxx_xxxx_xxxx}:       new_op = {pop_ru,  8'h41, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0};
1485 9 ns32kum
                // Phase 65 : RXP : PC is read, next POP prepare
1486 11 ns32kum
 {8'h41,10'bxx_xxxx_xxxx}:       new_op = {adddisp, 8'h42, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'hF};
1487 9 ns32kum
                // Phase 66 : RXP : DISP is addeed to Stack and MOD is read
1488 11 ns32kum
 {8'h42,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h43, imme, src_x, 1'b1,modul[5:0],  op_mov, 2'b00,2'b00,    4'h0};
1489 9 ns32kum
                // Phase 67 : RXP : MOD is new
1490 11 ns32kum
 {8'h43,10'bxx_xxxx_xxxx}:       new_op = {rmod_rxp,8'h44, rtmph,modul, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1};
1491 9 ns32kum
                // Phase 68 : RXP : wait for SB data, parallel SP update
1492 11 ns32kum
 {8'h44,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h00, imme, src_x, 1'b1,6'h1A,              op_mov, 2'b00,2'b00,    4'h0};  // SB load
1493 9 ns32kum
 
1494
                // Phase 69 : RETI : read of ICU for End-of-Interrupt Cycle , prepare read PC from Stack
1495 11 ns32kum
 {8'h45,10'bxx_xxxx_xxxx}:       new_op = {pop_op,  8'h46, src_x,stack, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1};
1496 9 ns32kum
                // Phase 70 : RETI/ RETT Entry : POP of PC , full Access
1497 11 ns32kum
 {8'h46,10'bxx_xxxx_xxxx}:       new_op = {pop_ru,  8'h47, imme, src_x, 1'b1,temp_h,             op_mov, 2'b00,2'b00,    4'h0};
1498 9 ns32kum
                // Phase 71 : RETI/RETT : PC is read, next POP prepare
1499 11 ns32kum
 {8'h47,10'bxx_xxxx_xxxx}:       new_op = {save_sp, 8'h48, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h1};
1500 9 ns32kum
                // Phase 72 : RETI/RETT : DISP is added to Stack , PSR load and MOD is loaded if DE off
1501 11 ns32kum
 {8'h48,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h49, imme, src_x, no_modul,                op_ldp, 2'b00,2'b00,    4'h0};
1502 9 ns32kum
                // Phase 73 : RETI/RETT : different paths
1503
 {8'h49,10'bxx_xxxx_xxxx}:       new_op = de_flag ?
1504
                                                                         ( reti_flag ?
1505
                                                                     {addr_nop,8'h4A, rtmph,src_x, 1'b0,dest_x,         op_mov, 2'b00,2'b00,    4'h0}
1506
                                                                   : {addr_nop,8'h4B, src_x,src_x, 1'b0,dest_x,         op_mov, 2'b00,2'b00,    4'h0} )
1507
                                                                   : {rmod_rtt,8'h4B, rtmph,modul, 1'b0,dest_x,         op_mov, 2'b00,2'b00,    4'h1};
1508
                // Phase 74 : RETI/RETT : one pause cycle if DE on
1509 11 ns32kum
 {8'h4A,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h0};
1510 9 ns32kum
                // Phase 75 : RETI/RETT : SB read if DE off
1511
 {8'h4B,10'bxx_xxxx_xxxx}:       new_op = reti_flag ?
1512
                                                                         {addr_nop,8'h00, imme, src_x, 1'b1,6'h1A,              op_mov, 2'b00,2'b00,    4'h0}
1513
                                                                   : ( de_flag ?
1514
                                                                     {adddispn,8'h4E, src_x,ttstak,1'b0,dest_x,         op_mov, 2'b00,2'b00,    4'hE}
1515
                                                                   : {adddispn,8'h4E, imme, ttstak,1'b1,6'h1A,          op_mov, 2'b00,2'b00,    4'hE} );
1516
                // Phase 78 : RETT : SP update
1517 11 ns32kum
 {8'h4E,10'bxx_xxxx_xxxx}:       new_op = {save_sp, 8'h4A, rtmph,src_x, 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'h0};
1518 9 ns32kum
 
1519
        // +++++++++++++++  special wait states for PSR and the Cache/MMU system  +++++++++++
1520
 
1521
                // Phase 76 : PSR in Word case simple delay of 2 cycles : 1. cycle does nothing
1522 11 ns32kum
 {8'h4C,10'bxx_xxxx_xxxx}:       new_op = {addr_nop,8'h4D, src_x,src_x, 1'b0,dest_x,             op_mov, 2'b00,