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[/] [m32632/] [trunk/] [rtl/] [I_PFAD.v] - Blame information for rev 41

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1 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 9 ns32kum
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       I_PFAD.v
7 29 ns32kum
//      Version:        3.0
8 23 ns32kum
//      History:        1.1 bug fix of 7 November 2015
9
//                              1.0 first release of 30 Mai 2015
10 29 ns32kum
//      Date:           2 December 2018
11 9 ns32kum
//
12 29 ns32kum
// Copyright (C) 2018 Udo Moeller
13 9 ns32kum
// 
14
// This source file may be used and distributed without 
15
// restriction provided that this copyright statement is not 
16
// removed from the file and that any derivative work contains 
17
// the original copyright notice and the associated disclaimer.
18
// 
19
// This source file is free software; you can redistribute it 
20
// and/or modify it under the terms of the GNU Lesser General 
21
// Public License as published by the Free Software Foundation;
22
// either version 2.1 of the License, or (at your option) any 
23
// later version. 
24
// 
25
// This source is distributed in the hope that it will be 
26
// useful, but WITHOUT ANY WARRANTY; without even the implied 
27
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
28
// PURPOSE. See the GNU Lesser General Public License for more 
29
// details. 
30
// 
31
// You should have received a copy of the GNU Lesser General 
32
// Public License along with this source; if not, download it 
33
// from http://www.opencores.org/lgpl.shtml 
34
// 
35 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
36 9 ns32kum
//
37
//      Modules contained in this file:
38
//      1. BITMASK      Mask Generator , was a ROM on falling edge in early days
39
//      2. MULFILTER    Filter for Multiplier Input Data
40 29 ns32kum
//      3. SHIFTER              Barrel Shifter for all Shift Opcodes
41
//      4. FFS_LOGIK    Logic for FFS opcode 
42
//      5. SCHALE               Enclosure for Adder/Subtractor
43
//      6. I_PFAD               The Integer Datapath
44 9 ns32kum
//
45 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
46 9 ns32kum
 
47 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
48 9 ns32kum
//
49
//      1. BITMASK      Mask Generator , was a ROM on falling edge in early days
50
//
51 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
52 9 ns32kum
module BITMASK (AA, DOUT);
53
 
54
//      0    :   FFFFFFFF;      Masktype 1 , Zero from right
55
//      1    :   FFFFFFFE;
56
//      2    :   FFFFFFFC;
57
//      3    :   FFFFFFF8;
58
//      .    :   ...
59
//      32   :   00000001;      Masktype 2 , Decoder
60
//      33   :   00000002;
61
//      34   :   00000004;
62
//      35   :   00000008;
63
//      ..   :   ...
64
//      64   :   00000001;      Masktyte 3 , One from right
65
//      65   :   00000003;
66
//      66   :   00000007;
67
//      67   :   0000000F;
68
//      ..   :   ...
69
//      96   :   FFFFFFFF;      Masktype 4 , like Masktype 3 but AA-1
70
//      97   :   00000001;
71
//      98   :   00000003;
72
//      99   :   00000007;
73
//      ..   :   ...
74
 
75
        input           [6:0]    AA;
76
 
77
        output  reg     [31:0]   DOUT;
78
 
79
        reg             [7:0]    dec_bit;
80
 
81
        wire     [4:0]   code;
82
        wire                    high,low;
83
 
84
 
85
        assign code = AA[4:0] - {4'd0,&AA[6:5]};
86
 
87
        assign high = (AA[6:5] == 2'd0);
88
        assign low  =  AA[6];
89
 
90
        always @(code or high or low)
91
                case (code[2:0])
92
                  3'b000 : dec_bit = {{7{high}},1'b1         };
93
                  3'b001 : dec_bit = {{6{high}},1'b1,   low  };
94
                  3'b010 : dec_bit = {{5{high}},1'b1,{2{low}}};
95
                  3'b011 : dec_bit = {{4{high}},1'b1,{3{low}}};
96
                  3'b100 : dec_bit = {{3{high}},1'b1,{4{low}}};
97
                  3'b101 : dec_bit = {{2{high}},1'b1,{5{low}}};
98
                  3'b110 : dec_bit = {   high  ,1'b1,{6{low}}};
99
                  3'b111 : dec_bit = {          1'b1,{7{low}}};
100
                endcase
101
 
102
        always @(code or high or low or dec_bit)
103
                case (code[4:3])
104
                  2'b00 : DOUT = {{24{high}},dec_bit              };
105
                  2'b01 : DOUT = {{16{high}},dec_bit,{ 8{low}}};
106
                  2'b10 : DOUT = {{ 8{high}},dec_bit,{16{low}}};
107
                  2'b11 : DOUT = {           dec_bit,{24{low}}};
108
                endcase
109
 
110
endmodule
111
 
112 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
113 9 ns32kum
//
114
//      2. MULFILTER    Filter for Multiplier Input Data
115
//
116 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
117 29 ns32kum
module MULFILTER (BWD, SRC1, SRC2, MRESULT);
118 9 ns32kum
 
119
        input    [1:0]   BWD;
120 29 ns32kum
        input   signed  [31:0]   SRC1,SRC2;
121
        output  [32:0]   MRESULT;
122 9 ns32kum
 
123 29 ns32kum
        wire    signed  [63:0]   muld;
124
        wire    signed  [31:0]   mulw;
125 9 ns32kum
 
126 29 ns32kum
        wire                    no_ovf;
127
 
128
        assign muld = SRC1 * SRC2;
129
        assign mulw = {(BWD[0] ? SRC1[15:8] : {8{SRC1[7]}}),SRC1[7:0]} * {(BWD[0] ? SRC2[15:8] : {8{SRC2[7]}}),SRC2[7:0]};
130
 
131
        assign no_ovf = BWD[1] ? (muld[63:32] == {32{muld[31]}})
132
                                                   : ( BWD[0] ? (mulw[31:16] == {16{mulw[15]}})
133
                                                                          : (mulw[15:8] == {8{mulw[7]}}) );
134 9 ns32kum
 
135 29 ns32kum
        assign MRESULT = {~no_ovf,muld[31:16],(BWD[1] ? muld[15:0] : mulw[15:0])};
136 9 ns32kum
 
137
endmodule
138
 
139 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
140 9 ns32kum
//
141 29 ns32kum
//      3. SHIFTER              Barrel Shifter for all Shift Opcodes
142 9 ns32kum
//
143 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
144 9 ns32kum
module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
145
 
146
        input  [31:0] MASKE;
147
        input         ROT,LSH,ASH;
148
        input   [1:0] SIZE;
149
        input   [7:0] SH_VAL;
150
        input  [31:0] SH_DAT;
151
        output [31:0] SH_OUT;
152
        output  [4:0] MASK_SEL;
153
 
154
        reg  [31:0] sh_dat_in;
155
        wire [31:0] sh_dat_0,sh_dat_1,sh_dat_2,sh_dat_3,sh_dat_4;
156
        wire  [4:0] shift;
157
        reg                 msb;
158
        wire  [1:0] mask_code;
159
        reg  [31:0] SH_OUT;
160
        reg   [4:0] MASK_SEL;
161
 
162
        // Inputstage : prepare for ROT opcode :
163
 
164
        always @(ROT or SIZE or SH_DAT)
165
          casex ({ROT,SIZE})
166
                3'b100  : sh_dat_in = {SH_DAT[31:16],SH_DAT[7:0],SH_DAT[7:0]};    // Byte copy to left
167
                3'b101  : sh_dat_in = {SH_DAT[15:0],SH_DAT[15:0]};        // Word copy to left
168
                default : sh_dat_in = SH_DAT;
169
          endcase
170
 
171
        // Special case for ROT and BYTE : this way less logic
172
 
173
        assign shift = (ROT & (SIZE == 2'b00)) ? {2'b11,SH_VAL[2:0]} : SH_VAL[4:0];
174
 
175
        // Rotation logic
176
 
177 11 ns32kum
        assign sh_dat_0 = shift[0] ? {sh_dat_in[30:0],sh_dat_in[31]} : sh_dat_in; // Rotation of 1 bit position
178 9 ns32kum
        assign sh_dat_1 = shift[1] ? {sh_dat_0[29:0],sh_dat_0[31:30]} : sh_dat_0;        // 2
179
        assign sh_dat_2 = shift[2] ? {sh_dat_1[27:0],sh_dat_1[31:28]} : sh_dat_1;        // 4
180
        assign sh_dat_3 = shift[3] ? {sh_dat_2[23:0],sh_dat_2[31:24]} : sh_dat_2;        // 8
181
        assign sh_dat_4 = shift[4] ? {sh_dat_3[15:0],sh_dat_3[31:16]} : sh_dat_3;        // 16
182
 
183
        // Detection of negativ data    
184
 
185
        always @(SIZE or SH_DAT)
186
          casex (SIZE)
187
                2'b00   : msb = SH_DAT[7];      // Byte
188
                2'b01   : msb = SH_DAT[15];     // Word
189
                default : msb = SH_DAT[31];     // Double = 11
190
          endcase
191
 
192
        // needs mask for output data : SH_VAL[7] says negativ number and "right" shift
193
 
194
        assign mask_code[1] = ROT | (SH_VAL[7] &   ASH &  msb);
195
        assign mask_code[0] = ROT | (SH_VAL[7] & ((ASH & ~msb) | LSH));
196
 
197
        always @(SH_VAL or SIZE)
198
          casex ({SH_VAL[7],SIZE})
199
                3'b100  : MASK_SEL = {2'b00,SH_VAL[2:0]};        // special mask for Byte at right-shift
200
                3'b101  : MASK_SEL = {1'b0,SH_VAL[3:0]}; // special mask for Word at right-shift
201
                default : MASK_SEL = SH_VAL[4:0];
202
          endcase
203
 
204
        always @(mask_code or sh_dat_4 or MASKE)        // top bits of MASKE are "1", lower bits are "0"
205
          casex (mask_code)
206
                  2'b00 : SH_OUT = sh_dat_4 &  MASKE;   // LSH and ASH with positiv shift count
207
                  2'b01 : SH_OUT = sh_dat_4 & ~MASKE;   // Negativ shift count : LSH or ASH with positiv data
208
                  2'b10 : SH_OUT = sh_dat_4 |  MASKE;   // ASH with negativ shift count and negativ input data
209
                default : SH_OUT = sh_dat_4;                    // ROT
210
          endcase
211
 
212
endmodule
213
 
214 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
215 9 ns32kum
//
216 29 ns32kum
//      4. FFS_LOGIK    Logic for FFS opcode 
217 9 ns32kum
//
218 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
219 9 ns32kum
module FFS_LOGIK  (SRC1, SRC2, BWD, FLAG, DOUT);
220
 
221
        input   [31:0]   SRC1;
222
        input    [4:0]   SRC2;
223
        input    [1:0]   BWD;
224
        output  reg             FLAG;
225
        output   [4:0]   DOUT;
226
 
227
        reg              [6:0]   maske;
228
        reg              [7:0]   byte_1,byte_2;
229
 
230
        wire     [7:0]   byte_0,byte_3;
231
        wire    [15:0]   mdat_0;
232
        wire     [7:0]   mdat_1;
233
        wire     [3:0]   mdat_2;
234
        wire     [4:0]   obits;
235
 
236
        always @(*)
237
                case (SRC2[2:0])
238
                  3'd0 : maske = 7'h7F;
239
                  3'd1 : maske = 7'h7E;
240
                  3'd2 : maske = 7'h7C;
241
                  3'd3 : maske = 7'h78;
242
                  3'd4 : maske = 7'h70;
243
                  3'd5 : maske = 7'h60;
244
                  3'd6 : maske = 7'h40;
245
                  3'd7 : maske = 7'h00;
246
                endcase
247
 
248
        assign byte_0 = (SRC2[4:3] == 2'b00) ? {SRC1[7],(SRC1[6:0] & maske)} : 8'h00;
249
 
250
        always @(*)
251
                casex (SRC2[4:3])
252
                  2'b00 : byte_1 = SRC1[15:8];
253
                  2'b01 : byte_1 = {SRC1[15],(SRC1[14:8] & maske)};
254
                  2'b1x : byte_1 = 8'h00;
255
                endcase
256
 
257
        always @(*)
258
                casex (SRC2[4:3])
259
                  2'b0x : byte_2 = SRC1[23:16];
260
                  2'b10 : byte_2 = {SRC1[23],(SRC1[22:16] & maske)};
261
                  2'b11 : byte_2 = 8'h00;
262
                endcase
263
 
264
        assign byte_3 = (SRC2[4:3] == 2'b11) ? {SRC1[31],(SRC1[30:24] & maske)} : SRC1[31:24];
265
 
266
        assign obits[4] = ({byte_1,byte_0} == 16'h0);
267
        assign mdat_0   = obits[4] ? {byte_3,byte_2} : {byte_1,byte_0}; // 16 Bit
268
 
269
        assign obits[3] = (mdat_0[7:0] == 8'h0);
270
        assign mdat_1   = obits[3] ? mdat_0[15:8] : mdat_0[7:0];
271
 
272
        assign obits[2] = (mdat_1[3:0] == 4'h0);
273
        assign mdat_2   = obits[2] ? mdat_1[7:4] : mdat_1[3:0];
274
 
275 23 ns32kum
        assign obits[1] =   (mdat_2[1:0] == 2'b00);
276
        assign obits[0] = ~((mdat_2[2:1] == 2'b10) | mdat_2[0]);
277 9 ns32kum
 
278 23 ns32kum
        always @(BWD or obits or mdat_2)
279 9 ns32kum
                casex ({BWD,obits[4:3]})
280
                  4'b00_x1 : FLAG = 1;  // Byte Overflow => nothing found
281
                  4'b00_10 : FLAG = 1;  // Byte Overflow => nothing found
282
                  4'b01_1x : FLAG = 1;  // Word Overflow => nothing found
283 23 ns32kum
                  default  : FLAG = (mdat_2 == 4'b0000);
284 9 ns32kum
                endcase
285
 
286
        assign DOUT = FLAG ? 5'h0 : obits;
287
 
288
endmodule
289
 
290 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
291 9 ns32kum
//
292 29 ns32kum
//      5. SCHALE               Enclosure for Adder/Subtractor
293 9 ns32kum
//
294 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
295 9 ns32kum
module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
296
 
297
        input   [31:0]   dataa,datab;
298
        input                   cin;
299
        input                   add_sub;        // 1 = Addition , 0 = Subtraction
300
        input    [1:0]   bwd;
301
 
302
        output  [31:0]   result;
303
        output                  cout,overflow;
304
 
305
        reg              [2:0]   seldat;
306
        reg                             overflow;
307
 
308
        wire    [32:0]   summe;
309
 
310
        assign summe = {1'b0,dataa} + {1'b0,(add_sub ? datab : ~datab)} + {32'd0,cin};
311
 
312
        always @(bwd or dataa or datab or summe)
313
                case (bwd)
314
                  2'b00   : seldat = {summe[7], dataa[7], datab[7]};
315
                  2'b01   : seldat = {summe[15],dataa[15],datab[15]};
316
                  default : seldat = {summe[31],dataa[31],datab[31]};
317
                endcase
318
 
319
        always @(seldat or add_sub)
320
                case (seldat[1:0])
321
                  2'b00 : overflow = add_sub ?  seldat[2] : 1'b0;
322
                  2'b01 : overflow = add_sub ? 1'b0 :  seldat[2];
323
                  2'b10 : overflow = add_sub ? 1'b0 : ~seldat[2];
324
                  2'b11 : overflow = add_sub ? ~seldat[2] : 1'b0;
325
                endcase
326
 
327
        assign cout = add_sub ? summe[32] : ~summe[32];
328
        assign result = summe[31:0];
329
 
330
endmodule
331
 
332 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
333 9 ns32kum
//
334 29 ns32kum
//      6. I_PFAD               The Integer Datapath
335 9 ns32kum
//
336 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
337
module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,
338
                                WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);
339 9 ns32kum
 
340
        input                   BCLK,BRESET;
341
        input   [31:0]   SFP_DAT,FSR,DP_OUT;
342
        input   [31:0]   SRC1,SRC2;
343
        input   [31:0]   BMASKE;
344
        input   [31:0]   ADDR;
345 29 ns32kum
        input   [32:0]   MRESULT;
346 9 ns32kum
        input    [7:0]   OPCODE;
347
        input    [1:0]   BWD;
348
        input                   FL;
349
        input    [2:0]   SP_CMP;
350
        input    [2:0]   DP_CMP;
351
        input                   LD_OUT;
352
        input                   WREN;
353
        input    [5:0]   WRADR;
354
        input    [7:0]   RDAA;
355
        input   [11:0]   DETOIP;
356
        input    [2:0]   BITSEL;
357
        input    [3:0]   OVF_BCD;
358
        input    [4:0]   DISP;
359
        input                   RWVFLAG;
360
        input    [3:0]   DSR;
361
 
362
        output  [31:0]   I_OUT;
363
        output  [11:0]   PSR;
364
        output   [6:0]   BMCODE; // ROM Address for BITMASK
365
        output  reg             OV_FLAG;
366
        output                  ACB_ZERO;
367
        output   [4:0]   STRING;
368
 
369
        reg             [31:0]   I_OUT;
370
        reg             [31:0]   pfad_7,pfad_6,pfad_8,pfad_4a;
371
        wire    [31:0]   pfad_4,pfad_5,pfad_11;
372
 
373
        reg             [31:0]   bwd_daten1,bwd_daten2;
374
        wire    [31:0]   addsub_q;
375
 
376
        // +++++++++++++  Global Output Multiplexer  ++++++++++++++++++++++++++++
377
 
378 11 ns32kum
        always @(OPCODE or pfad_4 or pfad_5 or pfad_6 or pfad_7 or pfad_8 or DP_OUT or FL or SFP_DAT or FSR or pfad_11)
379 9 ns32kum
                casex (OPCODE[7:3])
380
                  5'b0100_x : I_OUT = pfad_4;
381
                  5'b0101_x : I_OUT = pfad_5;   // String opcodes
382
                  5'b0110_x : I_OUT = pfad_6;
383
                  5'b0111_x : I_OUT = pfad_7;
384
                  5'b1000_x : I_OUT = pfad_8;
385
                  5'b1001_0 : I_OUT = DP_OUT;   // SP_FPU has higher priority ! LFSR has no output
386
                  // SFSR : ROUND,TRUNC,FLOOR Integer Data : SP or DP Block
387
                  5'b1001_1 : I_OUT = (OPCODE[2:1] == 2'b10) ? FSR : (FL ? SFP_DAT : DP_OUT);
388
                  5'b1011_x : I_OUT = pfad_11;
389
                  5'b1101_x : I_OUT = DP_OUT;   // Coprocessor
390
                  default       : I_OUT = 32'hxxxx_xxxx;        // don't care
391
                endcase
392
 
393
        // ++++++++++++++ PSR Register :         I  P S U / N Z F V - L T C
394
        //                                                                      11 10 9 8   7 6 5 4 3 2 1 0
395
 
396
        reg              [3:0]   psr_high;
397
        reg              [7:0]   psr_low,psr_new;
398
        reg             [11:0]   push_psr;       // true Register
399
        reg             [11:0]   calc_psr;       // only verilog case
400
        reg              [1:0]   nl_int;
401
 
402
        wire                    ld_psr_l,ld_psr_h,up_psr;
403
        wire                    cmp_op,bit_op,ari_op,neg_op,ffs_op,str_op,chk_op,abs_op,rwv_op;
404
        wire     [1:0]   fp_nz;
405
        wire                    f_flag,z_flag;
406
        wire     [1:0]   nl_flags;
407
        wire                    over_flow,cy_out;
408
        wire                    ffs_flag;       // FLAG result of FFS
409
        wire                    chk_flag;       // FLAG result of CHECK
410
        wire                    save_psr,pop_psr;
411
        wire     [4:0]   selbits;
412
        // Bits from DETOIP;
413 11 ns32kum
        wire                    cmps_op,ph_match,until,kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p;
414 9 ns32kum
        wire                    bcd_op,bcd_carry;
415
 
416
        assign cmps_op  = DETOIP[11];   // for CMPS
417
        assign ph_match = DETOIP[10];   // MATCH phase
418
        assign until    = DETOIP[9];    // UNITL Flag for String
419
        assign kill_opt = DETOIP[8];    // optimized execution of MOVS/MOVM
420
        assign inss_op  = DETOIP[7];    // 1=INSS
421
        assign exin_cmd = DETOIP[6];    // for EXT/INS
422
        assign extract  = DETOIP[5] & exin_cmd; // 1=EXT
423
        assign bit_reg  = DETOIP[4];    // for Bit opcodes
424
        assign kurz_st  = DETOIP[3];    // for MOVM/CMPM
425
        assign dw_info  = DETOIP[2];    // at ADJSPi is SP=SRC2 always 32 Bit
426
        assign acb_reg  = DETOIP[1];    // suppresses Carry-Set at ACB
427
        assign t2p          = DETOIP[0]; // Pulse to Load Trace-Bit to Pending-Trace-Bit
428
 
429
        assign bcd_op    = OVF_BCD[1];  // ADDPi,SUBPi - from DP_FPU
430
        assign bcd_carry = OVF_BCD[0];
431
 
432
        assign ld_psr_l = ((WRADR == 6'h1D) | (WRADR == 6'h10)) & WREN; // Register PSR & UPSR
433
        assign ld_psr_h =  (WRADR == 6'h1D) & (BWD != 2'b00) & WREN;    // Register PSR
434
        // LD_OUT[1] is coming out of DECODER for this purpose
435
        assign up_psr = bcd_op | ((cmp_op | bit_op | ari_op | neg_op | ffs_op | chk_op) & LD_OUT);
436
 
437 11 ns32kum
        assign cmp_op = (OPCODE == 8'h41) | ((OPCODE == 8'hB2) & (FL ? ~SP_CMP[2] : ~DP_CMP[2]));       // CMPi or (CMPf & ~NAN)
438
        assign bit_op =   ((OPCODE[7:4] == 4'h6) & ((~OPCODE[3] & OPCODE[1]) | OPCODE[3:0] == 4'hE))     // the last term is for IBIT
439 9 ns32kum
                                        | (OPCODE == 8'h4D) | str_op | rwv_op;  // TBIT or CMPS or RDVAL/WRVAL
440 11 ns32kum
        assign ari_op = (OPCODE[7:4] == 4'h4) & (OPCODE[1:0] == 2'b0) & ~dw_info;        // ADDi,ADDCi,SUBi,SUBCi - special case ADJSPi no flags
441 9 ns32kum
        assign neg_op = (OPCODE[7:4] == 4'h6) & (OPCODE[3] & (OPCODE[1:0] == 2'b0));     // ABSi,NEGi  
442
        assign ffs_op = (OPCODE          == 8'h85);     // FFS
443
        assign chk_op = (OPCODE          == 8'h83);     // CHECK
444 11 ns32kum
        assign str_op = (OPCODE[7:4] == 4'h5) & (OPCODE[3:2] == 2'b0) & ~kurz_st;       // String-"S" opcodes : F-Flag to 0, at start always
445 9 ns32kum
        assign abs_op = (OPCODE          == 8'h6C);     // ABSi : Carry is not affected !
446
        assign rwv_op = (OPCODE[7:4] == 4'hE) & (OPCODE[3:1] == 3'b0);  // RDVAL + WRVAL
447
 
448
        always @(bwd_daten1 or bwd_daten2 or addsub_q)  // SRC1 > SRC2 ?
449
                case ({bwd_daten2[31],bwd_daten1[31]})
450
                  2'b00 : nl_int = {addsub_q[31],addsub_q[31]}; // MSB = N , LSB = L
451
                  2'b01 : nl_int = {   1'b0     ,    1'b1    };
452
                  2'b10 : nl_int = {   1'b1     ,    1'b0    };
453
                  2'b11 : nl_int = {addsub_q[31],addsub_q[31]};
454
                endcase
455
 
456
        assign ACB_ZERO = (addsub_q == 32'h0);  // is used for ACBi opcode too
457 11 ns32kum
        assign f_flag = str_op ? 1'b0 : (rwv_op ? RWVFLAG : (bit_op ? SRC2[selbits] : (acb_reg ? PSR[5] : over_flow)));
458 9 ns32kum
        assign fp_nz  = FL ? SP_CMP[1:0] : DP_CMP[1:0];
459
        assign z_flag =   OPCODE[1] ?  fp_nz[0] : ACB_ZERO;
460
        assign nl_flags = OPCODE[1] ? {fp_nz[1],1'b0} : nl_int;
461
 
462
        always @(*)     // Bits : N Z F V - L T C
463
                casex ({cmp_op,bcd_op,bit_op,(ffs_op | chk_op)})
464 11 ns32kum
                  4'b0000 : psr_new = {PSR[7:6],          f_flag,PSR[4:1],((acb_reg | abs_op) ? PSR[0] : cy_out)};       // arithmetic Op : CY and F
465 9 ns32kum
                  4'b0001 : psr_new = {PSR[7:6],(ffs_op ? ffs_flag : chk_flag),PSR[4:0]};                // FFS or CHECK
466
                  4'b001x : psr_new = (cmps_op & str_op) ?
467
                                                          {2'b01,             f_flag,PSR[4:3],1'b0,PSR[1:0]}             // Init CMPS
468
                                                        : {PSR[7:6],          f_flag,PSR[4:0]};                                          // Bit opcode
469
                  4'b01xx : psr_new = {PSR[7:6],          1'b0,  PSR[4:1],bcd_carry};                   // BCD opcode
470
                  4'b1xxx : psr_new = ph_match ?
471
                                                          {PSR[7:6], ~(ACB_ZERO ^ until), PSR[4:0]}                                      // Until/While Option at String-"S" opcodes
472
                                                        : {nl_flags[1],z_flag,PSR[5:3],   nl_flags[0],PSR[1:0]};  // CMP f or i
473
                endcase
474
 
475
        always @(save_psr or pop_psr or OPCODE or PSR or SRC1)
476
                casex ({save_psr,pop_psr,OPCODE[6],OPCODE[2]})
477 11 ns32kum
                  4'b10xx : calc_psr = PSR & {~OPCODE[0],11'h0ED};       // clear P S U V T and the I-Bit at Interrupt & ABORT
478 9 ns32kum
                  4'b11xx : calc_psr = SRC1[27:16];
479
                  4'b0x00 : calc_psr = PSR & ~SRC1[11:0];        // BICPSR : Opcode = h32
480
                  4'b0x01 : calc_psr = PSR |  SRC1[11:0];        // BISPSR                        h36
481
                  default : calc_psr = SRC1[11:0];                       // LPR PSR                       h76
482
                endcase
483
 
484
        // Special case Exception Handling : Code x'89-x'8F
485
        assign save_psr = (OPCODE[7:3] == 5'b1000_1);
486
        assign pop_psr  = (OPCODE[2:0] == 3'b000);
487
 
488
        always @(posedge BCLK or negedge BRESET)        // central memory for PSR low
489
                if (!BRESET) psr_low <= 8'h0;
490
                  else
491
                  begin
492
                        if (ld_psr_l || save_psr) psr_low <= calc_psr[7:0];
493
                          else
494
                                if (up_psr) psr_low <= psr_new; // the Status result of a normal opcode
495
                  end
496
 
497
        always @(posedge BCLK or negedge BRESET)        // central memory for PSR high
498
                if (!BRESET) psr_high <= 4'h0;
499
                  else
500
                  begin
501
                        if (ld_psr_h || save_psr)  psr_high <= calc_psr[11:8];  // only at WORD access
502
                          else  // t2p : copy T-Bit into P-Bit at the beginning of opcode
503
                                if (t2p) psr_high <= {psr_high[3],psr_low[1],psr_high[1:0]};
504
                  end
505
 
506
        // Register for storage of PSR at Entry of Exception
507 11 ns32kum
        always @(posedge BCLK) if (save_psr) push_psr <= {PSR[11],(~OPCODE[1] & PSR[10]),PSR[9:0]};      // P-Flag modified
508 9 ns32kum
 
509
        assign PSR = {psr_high,psr_low};
510
 
511
        // ++++++++++++++  Overflow Detection  ++++++++++++++++++++++++++++++++++++++
512
 
513 29 ns32kum
        reg                             ovf_ash;
514 9 ns32kum
        wire    [31:0]   shdat;
515
 
516
        always @(posedge BCLK or negedge BRESET)
517
                if (!BRESET) OV_FLAG <= 1'b0;
518
                  else
519
                        if (OVF_BCD[3]) OV_FLAG <= OVF_BCD[2];  // DEI,QUO,DIV
520
                          else
521
                                if (LD_OUT)
522
                                  case (OPCODE)
523 29 ns32kum
                                         8'h78 : OV_FLAG <= MRESULT[32];
524 9 ns32kum
                                         8'h61 : OV_FLAG <= ovf_ash;
525
                                         8'h40 : OV_FLAG <= over_flow & acb_reg;        // ADD Opcode at ACB
526
                                   default : OV_FLAG <= 1'b0;
527
                                  endcase
528
 
529
        always @(BWD or SRC2 or shdat)
530
                casex (BWD)
531
                        2'b00 : ovf_ash = (SRC2[7]  != shdat[7]);
532
                        2'b01 : ovf_ash = (SRC2[15] != shdat[15]);
533
                  default : ovf_ash = (SRC2[31] != shdat[31]);
534
                endcase
535
 
536
        // ++++++++++++++ Format 4 Opcodes : Basic Integer Opcodes, MOVi is special case  +++++++++++++
537
 
538
        reg                             cy_in;
539 15 ns32kum
        reg                             get_psr,rd_psr,rd_dsr,get_mod;
540 9 ns32kum
        wire                    add_flag;
541
 
542
        always @(BWD or SRC1)
543
                casex (BWD)
544
                        2'b00 : bwd_daten1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Sign Extension
545
                        2'b01 : bwd_daten1 = {{16{SRC1[15]}},SRC1[15:0]};
546
                  default : bwd_daten1 = SRC1;
547
                endcase
548
 
549 11 ns32kum
        assign add_flag = ~OPCODE[3] & ~OPCODE[1] & ~OPCODE[0];  // Only ADDi and ADDCi otherwise subtract in SCHALE
550 9 ns32kum
 
551
        always @(PSR or OPCODE) // more effort due to ABSi und NEGi : Format 6
552
                casex ({OPCODE[5],OPCODE[3:2]})
553
                   3'b000 : cy_in = OPCODE[0];   // ADD + CMP
554
                   3'b001 : cy_in =  PSR[0];     // ADDC
555
                   3'b011 : cy_in = ~PSR[0];     // SUBC
556
                  default : cy_in = 1'b1;               // SUB + ABS + NEG : BORROW must be 1 for normal Adder 
557
                endcase
558
 
559 11 ns32kum
        SCHALE     addsub_ipfad  (.dataa(bwd_daten2), .datab(bwd_daten1), .cin(cy_in), .add_sub(add_flag), .bwd(BWD),
560 9 ns32kum
                                                          .result(addsub_q), .cout(cy_out), .overflow(over_flow) );
561
 
562 11 ns32kum
        always @(posedge BCLK) get_psr <= (RDAA == 8'h9D) | (RDAA == 8'h90) | (RDAA == 8'h93);  // PSR or US or DSR is read
563 9 ns32kum
        always @(posedge BCLK) rd_psr  <= (RDAA[1:0] == 2'b01);
564
        always @(posedge BCLK) rd_dsr  <= (RDAA[1:0] == 2'b11);
565 15 ns32kum
        always @(posedge BCLK) get_mod <= (RDAA == 8'h9F);
566 9 ns32kum
 
567 15 ns32kum
        always @(OPCODE or SRC1 or SRC2 or get_psr or rd_psr or rd_dsr or get_mod or DSR or PSR or ADDR)
568 9 ns32kum
                casex (OPCODE[3:1])
569
                   3'b001 : pfad_4a = SRC2 & ~SRC1;     // BIC
570 15 ns32kum
                   3'bx10 : pfad_4a = get_psr ? {({4{rd_dsr}} & DSR),16'd0,({4{rd_psr}} & PSR[11:8]),({8{~rd_dsr}} & PSR[7:0])}  // MOV
571
                                                                          : (get_mod ? {16'd0,SRC1[15:0]} : SRC1);
572 9 ns32kum
                   3'b011 : pfad_4a = SRC2 |  SRC1;     // OR
573
                   3'b101 : pfad_4a = SRC2 &  SRC1;     // AND
574
                   3'b111 : pfad_4a = SRC2 ^  SRC1;     // XOR
575
                  default : pfad_4a = ADDR;                     // ADDR, comes from ADDR_UNIT
576
                endcase
577
 
578
        assign pfad_4 = (OPCODE[1:0] == 2'b00) ? addsub_q : pfad_4a;     // ADD,ADDC,SUB,SUBC have extra path
579
 
580
        // ++++++++++++++ Format 5 Opcodes : Strings MOVS , CMPS und SKPS  +++++++++++++++++++++++++++++++
581
 
582
        reg             [11:0]   spointer,dpointer;
583
        reg              [9:0]   todo;
584
        reg              [9:4]  todo_reg;
585 13 ns32kum
        reg                             dis_opt;
586
        wire    [31:0]   diff_poi;
587 9 ns32kum
        wire                    mehr,weiter,op_str,no_opt;
588
 
589
        assign op_str = (OPCODE[7:3] == 5'b0101_0);
590
 
591 13 ns32kum
        assign diff_poi = SRC2 - SRC1;  // Special Case
592
 
593
        always @(posedge BCLK) if (op_str && OPCODE[2]) dis_opt <= (diff_poi[31:3] == 29'd0);
594
 
595 11 ns32kum
        // This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is not possible
596 9 ns32kum
        always @(posedge BCLK)
597
                if (op_str)
598
                        begin
599
                                spointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8'h00,todo[3:0]});      // Source
600
                                dpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8'h00,todo[3:0]});      // Destination
601
                        end
602
 
603
        assign no_opt = OPCODE[1] | ((spointer[11:3] == 9'h1FF) & (spointer[2:0] != 3'b000))
604 13 ns32kum
                                   | kill_opt | ((dpointer[11:3] == 9'h1FF) & (dpointer[2:0] != 3'b000))
605
                                   | dis_opt;
606 9 ns32kum
 
607 13 ns32kum
        assign pfad_5 = SRC1 - {28'h0,todo_reg[7:4]};
608 9 ns32kum
 
609
        assign mehr = (pfad_5[31:4] != 28'h0);
610
 
611
        always @(no_opt or BWD or mehr or pfad_5)
612
                casex ({no_opt,BWD,mehr,pfad_5[3:0]})
613
                  8'b000_1xxxx : todo = 10'h388; // Byte
614
                  8'b000_01xxx : todo = 10'h388;
615
                  8'b000_001xx : todo = 10'h244;
616
                  8'b000_0001x : todo = 10'h122;
617
                  8'b000_00001 : todo = 10'h011;
618
                //
619
                  8'b001_1xxxx : todo = 10'h348; // Word
620
                  8'b001_01xxx : todo = 10'h348;
621
                  8'b001_001xx : todo = 10'h348;
622
                  8'b001_0001x : todo = 10'h224;
623
                  8'b001_00001 : todo = 10'h112;
624
                //
625
                  8'b01x_1xxxx : todo = 10'h328; // DWord
626
                  8'b01x_01xxx : todo = 10'h328;
627
                  8'b01x_001xx : todo = 10'h328;
628
                  8'b01x_0001x : todo = 10'h328;
629
                  8'b01x_00001 : todo = 10'h214;
630
                //
631
                  8'b100_xxxxx : todo = 10'h011; // the opcodes CMPS and SKPS work on a single element
632
                  8'b101_xxxxx : todo = 10'h112;
633
                  8'b11x_xxxxx : todo = 10'h214;
634
                  default          : todo = 10'hxxx;
635
                endcase
636
 
637 13 ns32kum
        always @(posedge BCLK) if (op_str) todo_reg <= {todo[9:8],(OPCODE[2] ? 4'd0 : todo[7:4])};      // store for next phase 51
638 9 ns32kum
 
639
        assign weiter = mehr | (pfad_5[3:0] != 4'h0);
640
 
641 11 ns32kum
        assign STRING = {1'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )};  // ACB_ZERO is delayed 1 cycle extern
642 9 ns32kum
 
643
        // +++++++++++++  Format 6 opcodes : ADDP + SUBP are done in DP_FPU  ++++++++++++++++++++
644
 
645
        wire                    rot,ash,lsh,eis_op;
646
        wire     [7:0]   sh_count;
647
        wire     [4:0]   shcode;         // comes from SHIFTER
648
 
649
        reg              [4:0]   disp_reg;       // for EXT/INS
650
        reg              [2:0]   offs_reg;       // for INSS
651
        wire                    exin_op,exin_op2;
652
        wire     [4:0]   shval_ei;
653
        wire     [7:0]   sh_exin;
654
 
655
        assign rot = (OPCODE[3:0] == 4'h0);
656
        assign ash = (OPCODE[3:0] == 4'h1);
657 11 ns32kum
        assign lsh = (OPCODE[3:1] == 3'b010);   // 5 is LSH , but 4 is Trap(UND) and is used for right-shift of Offset !
658 9 ns32kum
 
659 11 ns32kum
        assign eis_op = (OPCODE == 8'h73) | (OPCODE[7] & ~OPCODE[1] & inss_op); // EXTSi | INSSi at OPCODE=80h
660 9 ns32kum
        assign exin_op  = exin_cmd & (OPCODE[7:4] == 4'h8);                             // identifies EXT/INS
661
        assign exin_op2 = (exin_cmd | inss_op) & (OPCODE[7:4] == 4'h6); // identifies LSH
662
 
663
        always @(posedge BCLK) disp_reg <= DISP;        // at EXT the path via ADDR is already used for DEST !!!
664
        always @(posedge BCLK) if (OPCODE[7]) offs_reg <= SRC1[7:5];    // for INSS , OPCODE=80h
665
 
666
        // Byte for external Bit source, Double for Register
667
        assign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2'b00,BITSEL};
668
 
669
        assign shval_ei = inss_op ? {2'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2'b00,SRC1[2:0]});
670 23 ns32kum
        assign sh_exin[4:0] = ({5{extract}} ^ shval_ei) + {4'd0,extract};        // EXT : right shift, INS : left shift
671 11 ns32kum
        assign sh_exin[7:5] = (shval_ei == 5'd0) ? 3'b000 : {3{extract}};       // Special case : 0 has no negativ sign !
672 9 ns32kum
 
673
        // LSH shift by 16 bit to right
674
        assign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);
675
 
676 11 ns32kum
        assign BMCODE = (bit_op | eis_op | exin_op) ? {(eis_op | exin_op),(bit_op | exin_op),selbits} : {2'b00,shcode};
677 9 ns32kum
 
678 11 ns32kum
        SHIFTER  shift_inst (.MASKE(BMASKE), .ROT(rot), .ASH(ash), .LSH(lsh), .SH_DAT(SRC2), .SH_VAL(sh_count),
679 9 ns32kum
                                                 .MASK_SEL(shcode), .SIZE(BWD), .SH_OUT(shdat) );
680
 
681
        always @(BWD or SRC2 or neg_op or dw_info)
682
                casex ({neg_op,(dw_info | BWD[1]),BWD[0]})                               // special case ADJSPi
683
                   3'b000 : bwd_daten2 = {{24{SRC2[7]}}, SRC2[7:0]};     // Sign Extension
684
                   3'b001 : bwd_daten2 = {{16{SRC2[15]}},SRC2[15:0]};
685
                   3'b1xx : bwd_daten2 = 32'h0;                                                 // is used for ABSi and NEGi
686
                  default : bwd_daten2 = SRC2;
687
                endcase
688
 
689
        always @(OPCODE or SRC2 or BMASKE or addsub_q or bwd_daten1 or SRC1 or shdat or DP_OUT)
690
                casex (OPCODE[3:0])
691
                  4'b001x : pfad_6 = SRC2 & ~BMASKE;            // CBIT & CBITI
692
                  4'b011x : pfad_6 = SRC2 |  BMASKE;            // SBIT & SBITI
693
                  4'b1000 : pfad_6 = addsub_q;                          // NEG
694
                  4'b1001 : pfad_6 = {SRC1[31:1],~SRC1[0]};      // NOT
695
                  4'b1010 : pfad_6 = SRC1;                                      // Special case 6A : not used normal -> op_lmr !
696
                  4'b1100 : pfad_6 = bwd_daten1[31] ? addsub_q : SRC1;  // ABS
697
                  4'b1101 : pfad_6 = ~SRC1;                                     // COM
698 23 ns32kum
                  4'b111x : pfad_6 = SRC2 ^  BMASKE;            // IBIT
699 9 ns32kum
                  default : pfad_6 = shdat;                                     // Result of Barrelshifter
700
                endcase
701
 
702
        // ++++++++++++++  Format 7 : MUL  +++++++++++++++++++++++
703
 
704
        // This Condition-Code Decoder is written twice ... see DECODER
705
 
706
        reg                             sc_bit;
707
        wire                    sc_negativ,sc_zero,sc_flag,sc_larger,sc_carry_psr;
708
 
709
        assign sc_negativ       = PSR[7];
710
        assign sc_zero      = PSR[6];
711
        assign sc_flag          = PSR[5];
712
        assign sc_larger        = PSR[2];
713
        assign sc_carry_psr = PSR[0];
714
 
715
        always @(SRC1 or sc_zero or sc_carry_psr or sc_larger or sc_negativ or sc_flag)
716
                case (SRC1[3:0])
717
                  4'h0 : sc_bit =  sc_zero;                     // EQual
718
                  4'h1 : sc_bit = ~sc_zero;                     // Not Equal
719
                  4'h2 : sc_bit =  sc_carry_psr;        // Carry Set
720
                  4'h3 : sc_bit = ~sc_carry_psr;        // Carry Clear
721
                  4'h4 : sc_bit =  sc_larger;           // Higher
722
                  4'h5 : sc_bit = ~sc_larger;           // Lower or Same
723
                  4'h6 : sc_bit =  sc_negativ;          // Greater Than
724
                  4'h7 : sc_bit = ~sc_negativ;          // Less or Equal
725
                  4'h8 : sc_bit =  sc_flag;                     // Flag Set
726
                  4'h9 : sc_bit = ~sc_flag;                     // Flag Clear
727
                  4'hA : sc_bit = ~sc_larger  & ~sc_zero;       // LOwer
728
                  4'hB : sc_bit =  sc_larger  |  sc_zero;       // Higher or Same
729
                  4'hC : sc_bit = ~sc_negativ & ~sc_zero;       // Less Than
730
                  4'hD : sc_bit =  sc_negativ |  sc_zero;       // Greater or Equal
731
                  4'hE : sc_bit = 1'b1;                         // True
732
                  4'hF : sc_bit = 1'b0;                         // False
733
                endcase
734
 
735
        reg              [3:0]  bytes2anz;
736
        wire    [23:0]   and_src1;
737
        wire    [31:0]   movxz_dat;
738
        wire     [4:0]   kurz_anz;
739
        wire    [31:0]   ext_sh4,ext_sh2;
740
 
741
        assign and_src1  = {{16{BWD[1]}},{8{BWD[0]}}} & SRC1[31:8];      // for MOVZ
742
 
743
        assign movxz_dat = (OPCODE[1] ^ OPCODE[0]) ? {and_src1,SRC1[7:0]} : bwd_daten1;   // MOVZ.. ?
744
 
745
        always @(ADDR or BWD)
746
                casex (BWD[1:0])
747
                  2'b00 : bytes2anz = ADDR[3:0];
748
                  2'b01 : bytes2anz = {1'b0,ADDR[3:1]};
749
                  2'b1x : bytes2anz = {2'b0,ADDR[3:2]};
750
                endcase
751
 
752
        assign kurz_anz = {1'b0,bytes2anz} + 5'h01;     // count for MOVM/CMPM
753
 
754
        assign ext_sh4 = SRC1[7] ? {4'h0,SRC2[31:4]}    : SRC2;         // EXTSi
755
        assign ext_sh2 = SRC1[6] ? {2'b0,ext_sh4[31:2]} : ext_sh4;
756
 
757
        always @(*)
758
                casex (OPCODE[3:0])
759
                  4'b0011 : pfad_7 = (SRC1[5] ? {1'b0,ext_sh2[31:1]} : ext_sh2) & BMASKE;       // EXTSi
760
                  4'b01xx : pfad_7 = movxz_dat;                 // MOVXBW, MOVZBW, MOVZiD, MOVXiD
761
                  4'b1000 : pfad_7 = MRESULT[31:0];              // MULi
762
                  4'b1010 : pfad_7 = {27'h0,(kurz_st ? kurz_anz : {4'h0,sc_bit})};      // SCond or start of MOVM/CMPM
763
                  default : pfad_7 = DP_OUT;                    // DIV etc.
764
                endcase
765
 
766
        // ++++++++++++++  Format 8 : multiple opcodes  +++++++++++++++++++++++
767
 
768
        reg                             chk_p1;
769
        reg             [31:0]   ins_maske;
770
 
771
        wire     [4:0]   ffs_out;
772
        wire    [15:0]   low_bou,upp_bou,zeiger,chk_upp,chk_low;
773
        wire                    flag_up,flag_lo;
774
 
775
        FFS_LOGIK ffs_unit (.SRC1(SRC1), .SRC2(SRC2[4:0]), .BWD(BWD), .FLAG(ffs_flag), .DOUT(ffs_out) );
776
 
777
        // CHECK : SRC1 are the Bounds
778
        assign low_bou = BWD[0] ? SRC1[31:16] : {{8{SRC1[15]}},SRC1[15:8]};
779
        assign upp_bou = BWD[0] ? SRC1[15:0]  : {{8{SRC1[7]}}, SRC1[7:0]};
780
        assign zeiger  = BWD[0] ? SRC2[15:0]  : {{8{SRC2[7]}}, SRC2[7:0]};
781
 
782
        assign chk_upp = upp_bou - zeiger;      // F=1 if upp_bou < zeiger
783
        assign chk_low = zeiger - low_bou;      // F=1 if zeiger < low_bou
784
 
785
        assign flag_up = (upp_bou[15] == zeiger[15]) ? chk_upp[15] : upp_bou[15];       // See NL Definition
786
        assign flag_lo = (low_bou[15] == zeiger[15]) ? chk_low[15] : zeiger[15];
787
 
788
        always @(posedge BCLK) chk_p1 <= chk_op & BWD[1];       // CHECKD needs 2 cycles to execute
789
 
790
        assign chk_flag = BWD[1] ? (chk_p1 ? (nl_int[1] | psr_low[5]) : nl_int[1]) : (flag_up | flag_lo);
791
 
792
        always @(posedge BCLK) ins_maske <= shdat;      // expensive solution in terms of LEs ! 
793
 
794
        always @(*)
795
                casex (OPCODE[3:0])              // CVTP (81) has no OPCODE !
796 11 ns32kum
                  4'b000x : pfad_8 = (extract ? SRC2 : 32'hFFFF_FFFF) & BMASKE; // EXT, the other form is for INS to get the mask
797
                  4'b0010 : pfad_8 = (SRC1 & ins_maske) | (SRC2 & ~ins_maske);  // INS ins_maske[] ? SRC1[] : SRC2[]
798 9 ns32kum
                  4'b0011 : pfad_8 = BWD[1] ? addsub_q : {16'h0,chk_low};
799
                  4'b0101 : pfad_8 = {24'hxx_xxxx,3'b000,ffs_out};
800 11 ns32kum
                  default : pfad_8 = {4'hx,push_psr,SRC1[15:0]}; // Opcode x'87-x'8F is used at CXP and therefore in Exception-Processing
801 9 ns32kum
                endcase
802
 
803
        // ++++++++++++++ Format 11 : Floating-Point Datapath  +++++++++++++++++++++++++++++++
804
 
805
        assign pfad_11 = (OPCODE[1:0] == 2'b01) ?
806
                                                {((OPCODE[3:2] == 2'b11) ? 1'b0 : (SRC1[31] ^ OPCODE[2])),SRC1[30:0]}    // ABSf , NEGf + MOVf
807
                                                                                        : DP_OUT;
808
 
809
endmodule

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