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[/] [neo430/] [trunk/] [neo430/] [rtl/] [core/] [neo430_addr_gen.vhd] - Blame information for rev 198

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1 198 zero_gravi
-- #################################################################################################
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-- #  << NEO430 - Address Generator Unit >>                                                        #
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-- # ********************************************************************************************* #
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-- # Address computation and memory address register (MAR).                                        #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430                                    #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_addr_gen is
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  port (
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    -- global control --
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    clk_i      : in  std_ulogic; -- global clock, rising edge
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    -- data input --
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    reg_i      : in  std_ulogic_vector(15 downto 0); -- reg file input
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    mem_i      : in  std_ulogic_vector(15 downto 0); -- memory input
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    imm_i      : in  std_ulogic_vector(15 downto 0); -- branch offset
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    irq_sel_i  : in  std_ulogic_vector(01 downto 0); -- IRQ vector
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    -- control --
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    ctrl_i     : in  std_ulogic_vector(ctrl_width_c-1 downto 0);
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    -- data output --
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    mem_addr_o : out std_ulogic_vector(15 downto 0); -- memory address
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    dwb_o      : out std_ulogic_vector(15 downto 0)  -- data write back output
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  );
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end neo430_addr_gen;
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architecture neo430_addr_gen_rtl of neo430_addr_gen is
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  signal mem_addr_reg : std_ulogic_vector(15 downto 0); -- memory address register
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  signal addr_add     : std_ulogic_vector(15 downto 0); -- result from address adder
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begin
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  -- Memory Address Adder -----------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  memory_addr_adder: process(ctrl_i, mem_i, imm_i, reg_i)
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    variable offset_v : std_ulogic_vector(15 downto 0);
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  begin
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    case ctrl_i(ctrl_adr_off2_c downto ctrl_adr_off0_c) is
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      when "000"  => offset_v := imm_i;
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      when "001"  => offset_v := x"0001"; -- +1
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      when "010"  => offset_v := x"0002"; -- +2
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      when "011"  => offset_v := x"FFFE"; -- -2
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      when others => offset_v := mem_i;
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    end case;
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    addr_add <= std_ulogic_vector(unsigned(reg_i) + unsigned(offset_v));
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  end process memory_addr_adder;
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  -- output for write back --
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  dwb_o <= addr_add;
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  -- Memory Address Register --------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  memory_addr_reg: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      if (ctrl_i(ctrl_adr_mar_wr_c) = '1') then
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        if (ctrl_i(ctrl_adr_mar_sel_c) = '0') then
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          mem_addr_reg <= reg_i;
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        else
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          mem_addr_reg <= addr_add;
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        end if;
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      end if;
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    end if;
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  end process memory_addr_reg;
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  -- Memory Address Output ----------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  memory_addr_out: process(ctrl_i, irq_sel_i, reg_i, mem_addr_reg)
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  begin
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    if (ctrl_i(ctrl_adr_bp_en_c) = '1') then
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      if (ctrl_i(ctrl_adr_ivec_oe_c) = '1') then -- interrupt handler call
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        mem_addr_o <= dmem_base_c; -- IRQ vectors are located at the beginning of DMEM
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        mem_addr_o(2 downto 0) <= irq_sel_i & '0'; -- select according word-aligned entry
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      else -- direct output of reg file
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        mem_addr_o <= reg_i;
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      end if;
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    else
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      mem_addr_o <= mem_addr_reg;
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    end if;
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  end process memory_addr_out;
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end neo430_addr_gen_rtl;

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