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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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-- # Top entity of the NEO430 CPU. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_cpu is
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generic (
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BOOTLD_USE : boolean := true; -- implement and use bootloader?
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IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rst_i : in std_ulogic; -- global reset, low-active, async
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-- memory interface --
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mem_rd_o : out std_ulogic; -- memory read enable
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mem_imwe_o : out std_ulogic; -- allow writing to IMEM
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mem_wr_o : out std_ulogic_vector(01 downto 0); -- byte memory write enable
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mem_addr_o : out std_ulogic_vector(15 downto 0); -- address
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mem_data_o : out std_ulogic_vector(15 downto 0); -- write data
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mem_data_i : in std_ulogic_vector(15 downto 0); -- read data
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-- interrupt system --
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irq_i : in std_ulogic_vector(03 downto 0) -- interrupt requests
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);
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end neo430_cpu;
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architecture neo430_cpu_rtl of neo430_cpu is
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-- local signals --
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signal mem_addr : std_ulogic_vector(15 downto 0); -- memory address
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signal mdi : std_ulogic_vector(15 downto 0); -- memory data_in
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signal mdi_gate : std_ulogic_vector(15 downto 0); -- memory data_in power gate
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signal mdo_gate : std_ulogic_vector(15 downto 0); -- memory data_out power gate
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signal ctrl_bus : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control spine
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signal sreg : std_ulogic_vector(15 downto 0); -- current status register
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signal alu_flags : std_ulogic_vector(04 downto 0); -- new ALU flags
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signal imm : std_ulogic_vector(15 downto 0); -- branch offset
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signal rf_read : std_ulogic_vector(15 downto 0); -- RF read data
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signal alu_res : std_ulogic_vector(15 downto 0); -- ALU result
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signal addr_fb : std_ulogic_vector(15 downto 0); -- address feedback
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signal irq_sel : std_ulogic_vector(01 downto 0); -- IRQ vector
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signal dio_swap : std_ulogic; -- data in/out swap
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signal bw_ff : std_ulogic; -- byte/word access flag
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signal rd_ff : std_ulogic; -- is read access
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begin
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-- Control Unit -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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neo430_control_inst: neo430_control
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port map (
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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rst_i => rst_i, -- global reset, low-active, async
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-- memory interface --
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instr_i => mem_data_i, -- instruction word from memory
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-- control --
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sreg_i => sreg, -- current status register
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ctrl_o => ctrl_bus, -- control signals
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irq_vec_o => irq_sel, -- irq channel address
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imm_o => imm, -- branch offset
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-- irq lines --
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irq_i => irq_i -- IRQ lines
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);
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-- Register File ------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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neo430_reg_file_inst: neo430_reg_file
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generic map (
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BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader?
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IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
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)
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port map (
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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rst_i => rst_i, -- global reset, low-active, async
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-- data input --
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alu_i => alu_res, -- data from alu
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addr_i => addr_fb, -- data from addr unit
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flag_i => alu_flags, -- new ALU flags
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-- control --
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ctrl_i => ctrl_bus, -- control signals
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-- data output --
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data_o => rf_read, -- read data
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sreg_o => sreg -- current SR
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);
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-- ALU ----------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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neo430_alu_inst: neo430_alu
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port map (
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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-- operands --
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reg_i => rf_read, -- data from reg file
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mem_i => mdi, -- data from memory
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sreg_i => sreg, -- current SR
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-- control --
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ctrl_i => ctrl_bus, -- control signals
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-- results --
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data_o => alu_res, -- result
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flag_o => alu_flags -- new ALU flags
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);
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-- Address Generator --------------------------------------------------------
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-- -----------------------------------------------------------------------------
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neo430_addr_gen_inst: neo430_addr_gen
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port map(
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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-- data input --
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reg_i => rf_read, -- reg file input
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mem_i => mdi, -- memory input
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imm_i => imm, -- branch offset
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irq_sel_i => irq_sel, -- IRQ vector
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-- control --
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ctrl_i => ctrl_bus, -- control signals
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-- data output --
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mem_addr_o => mem_addr, -- memory address
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dwb_o => addr_fb -- data write back output
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);
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-- Memory Access ------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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memory_control: process(clk_i)
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begin
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if rising_edge(clk_i) then
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bw_ff <= ctrl_bus(ctrl_alu_bw_c);
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dio_swap <= ctrl_bus(ctrl_alu_bw_c) and mem_addr(0);
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rd_ff <= ctrl_bus(ctrl_mem_rd_c);
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end if;
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end process memory_control;
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-- Memory R/W interface --
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mem_rd_o <= ctrl_bus(ctrl_mem_rd_c);
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-- activate both WE lines when in word mode, use corresponding WE line when in byte mode
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mem_wr_o(0) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and (not mem_addr(0)));
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mem_wr_o(1) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and mem_addr(0) );
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-- only allow write-access to IMEM when r-flag is set --
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mem_imwe_o <= sreg(sreg_r_c);
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-- data in/out swap --
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mdi_gate <= mem_data_i when ((rd_ff = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
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mdi <= mdi_gate when (dio_swap = '0') else mdi_gate(7 downto 0) & mdi_gate(15 downto 8);
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mdo_gate <= alu_res when (dio_swap = '0') else alu_res(7 downto 0) & alu_res(15 downto 8);
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mem_data_o <= mdo_gate when ((ctrl_bus(ctrl_mem_wr_c) = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
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-- address output --
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mem_addr_o <= mem_addr(15 downto 1) & '0'; -- word-aligned addresses only beyond this point
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end neo430_cpu_rtl;
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