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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - Arbitrary Frequency Generator >> #
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-- # ********************************************************************************************* #
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-- # Number controlled oscillator-based frequency generator with three independent channels. Each #
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-- # channel has its enable flag, 16-bit tuning word register and prescaler selector. The phase #
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-- # accumulator of each channel is 17 bit wide. #
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-- # f_out(x) = ((f_cpu / nco_prsc(x)) * tuning_word(x)) / 2^17 for channels x = 0,1,2 #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_freq_gen is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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addr_i : in std_ulogic_vector(15 downto 0); -- address
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data_i : in std_ulogic_vector(15 downto 0); -- data in
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data_o : out std_ulogic_vector(15 downto 0); -- data out
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- frequency generator --
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freq_gen_o : out std_ulogic_vector(02 downto 0) -- programmable frequency output
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);
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end neo430_freq_gen;
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architecture neo430_freq_gen_rtl of neo430_freq_gen is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(freq_gen_size_c); -- low address boundary bit
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-- control reg bits --
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constant ctrl_en_ch0_c : natural := 0; -- r/w: enable NCO channel 0
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constant ctrl_en_ch1_c : natural := 1; -- r/w: enable NCO channel 1
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constant ctrl_en_ch2_c : natural := 2; -- r/w: enable NCO channel 2
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constant ctrl_ch0_prsc0_c : natural := 3; -- r/w: prescaler select bit 0 for channel 0
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constant ctrl_ch0_prsc1_c : natural := 4; -- r/w: prescaler select bit 1 for channel 0
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constant ctrl_ch0_prsc2_c : natural := 5; -- r/w: prescaler select bit 2 for channel 0
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constant ctrl_ch1_prsc0_c : natural := 6; -- r/w: prescaler select bit 0 for channel 1
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constant ctrl_ch1_prsc1_c : natural := 7; -- r/w: prescaler select bit 1 for channel 1
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constant ctrl_ch1_prsc2_c : natural := 8; -- r/w: prescaler select bit 2 for channel 1
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constant ctrl_ch2_prsc0_c : natural := 9; -- r/w: prescaler select bit 0 for channel 2
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constant ctrl_ch2_prsc1_c : natural := 10; -- r/w: prescaler select bit 1 for channel 2
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constant ctrl_ch2_prsc2_c : natural := 11; -- r/w: prescaler select bit 2 for channel 2
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(15 downto 0); -- access address
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- word read enable
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-- accessible regs --
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signal ctrl : std_ulogic_vector(11 downto 0); -- r/w: control register
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type tuning_word_t is array (0 to 2) of std_ulogic_vector(15 downto 0);
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signal tuning_word : tuning_word_t; -- -/w: tuning word channel 0,1,2
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-- nco core --
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type phase_accu_t is array (0 to 2) of std_ulogic_vector(16 downto 0);
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signal nco_phase_accu : phase_accu_t;
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signal nco_prsc_tick : std_ulogic_vector(2 downto 0);
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begin
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-- Access Control -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = freq_gen_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= freq_gen_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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-- Write access -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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wr_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wren = '1') then
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if (addr = freq_gen_ctrl_addr_c) then
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ctrl(ctrl_en_ch0_c) <= data_i(ctrl_en_ch0_c);
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ctrl(ctrl_en_ch1_c) <= data_i(ctrl_en_ch1_c);
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ctrl(ctrl_en_ch2_c) <= data_i(ctrl_en_ch2_c);
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ctrl(ctrl_ch0_prsc0_c) <= data_i(ctrl_ch0_prsc0_c);
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ctrl(ctrl_ch0_prsc1_c) <= data_i(ctrl_ch0_prsc1_c);
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ctrl(ctrl_ch0_prsc2_c) <= data_i(ctrl_ch0_prsc2_c);
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ctrl(ctrl_ch1_prsc0_c) <= data_i(ctrl_ch1_prsc0_c);
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ctrl(ctrl_ch1_prsc1_c) <= data_i(ctrl_ch1_prsc1_c);
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ctrl(ctrl_ch1_prsc2_c) <= data_i(ctrl_ch1_prsc2_c);
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ctrl(ctrl_ch2_prsc0_c) <= data_i(ctrl_ch2_prsc0_c);
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ctrl(ctrl_ch2_prsc1_c) <= data_i(ctrl_ch2_prsc1_c);
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ctrl(ctrl_ch2_prsc2_c) <= data_i(ctrl_ch2_prsc2_c);
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end if;
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if (addr = freq_gen_tw_ch0_addr_c) then
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tuning_word(0) <= data_i;
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end if;
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if (addr = freq_gen_tw_ch1_addr_c) then
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tuning_word(1) <= data_i;
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end if;
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if (addr = freq_gen_tw_ch2_addr_c) then
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tuning_word(2) <= data_i;
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end if;
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end if;
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end if;
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end process wr_access;
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-- NCO core (number controlled oscillator) ----------------------------------
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-- -----------------------------------------------------------------------------
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nco_core: process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- enable external clock generator --
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clkgen_en_o <= ctrl(ctrl_en_ch0_c) or ctrl(ctrl_en_ch1_c) or ctrl(ctrl_en_ch2_c);
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-- NCOs --
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for i in 0 to 2 loop
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-- NCO clock enable --
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nco_prsc_tick(i) <= clkgen_i(to_integer(unsigned(ctrl(ctrl_ch0_prsc2_c + 3*i downto ctrl_ch0_prsc0_c + 3*i))));
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-- phase accu --
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if (ctrl(ctrl_en_ch0_c + i) = '0') then -- disabled
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nco_phase_accu(i) <= (others => '0');
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elsif (nco_prsc_tick(i) = '1') then -- enabled; wait for clock enable tick
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nco_phase_accu(i) <= std_ulogic_vector(unsigned(nco_phase_accu(i)) + unsigned('0' & tuning_word(i)));
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end if;
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-- output --
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freq_gen_o(i) <= nco_phase_accu(i)(16); -- MSB (carry_out) is output
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end loop; -- i - NCO channel
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end if;
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end process nco_core;
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-- Read access --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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rd_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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data_o <= (others => '0');
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if (rden = '1') then
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-- if (addr = freq_gen_ctrl_addr_c) then
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data_o(ctrl_en_ch0_c) <= ctrl(ctrl_en_ch0_c);
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data_o(ctrl_en_ch1_c) <= ctrl(ctrl_en_ch1_c);
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data_o(ctrl_en_ch2_c) <= ctrl(ctrl_en_ch2_c);
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data_o(ctrl_ch0_prsc0_c) <= ctrl(ctrl_ch0_prsc0_c);
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data_o(ctrl_ch0_prsc1_c) <= ctrl(ctrl_ch0_prsc1_c);
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data_o(ctrl_ch0_prsc2_c) <= ctrl(ctrl_ch0_prsc2_c);
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data_o(ctrl_ch1_prsc0_c) <= ctrl(ctrl_ch1_prsc0_c);
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data_o(ctrl_ch1_prsc1_c) <= ctrl(ctrl_ch1_prsc1_c);
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data_o(ctrl_ch1_prsc2_c) <= ctrl(ctrl_ch1_prsc2_c);
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data_o(ctrl_ch2_prsc0_c) <= ctrl(ctrl_ch2_prsc0_c);
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data_o(ctrl_ch2_prsc1_c) <= ctrl(ctrl_ch2_prsc1_c);
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data_o(ctrl_ch2_prsc2_c) <= ctrl(ctrl_ch2_prsc2_c);
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-- end if;
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end if;
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end if;
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end process rd_access;
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end neo430_freq_gen_rtl;
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