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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - High-Precision Timer >> #
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-- # ********************************************************************************************* #
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-- # This timer uses a configurable prescaler to increment an internal 16-bit counter. When the #
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-- # counter value reaches the programmable threshold an interrupt can be triggered. Optionally, #
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-- # the counter can be automatically reset when reaching the threshold value to restart counting. #
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-- # Configure THRES before enabling the timer to prevent false interrupt requests. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_timer is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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addr_i : in std_ulogic_vector(15 downto 0); -- address
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data_i : in std_ulogic_vector(15 downto 0); -- data in
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data_o : out std_ulogic_vector(15 downto 0); -- data out
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- interrupt --
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irq_o : out std_ulogic -- interrupt request
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);
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end neo430_timer;
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architecture neo430_timer_rtl of neo430_timer is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(timer_size_c); -- low address boundary bit
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-- control reg bits --
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constant ctrl_en_c : natural := 0; -- r/w: timer enable
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constant ctrl_arst_c : natural := 1; -- r/w: auto reset on match
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constant ctrl_irq_en_c : natural := 2; -- r/w: interrupt enable
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constant ctrl_run_c : natural := 3; -- r/w: start/stop timer
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constant ctrl_prsc0_c : natural := 4; -- r/w: prescaler select bit 0
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constant ctrl_prsc1_c : natural := 5; -- r/w: prescaler select bit 1
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constant ctrl_prsc2_c : natural := 6; -- r/w: prescaler select bit 2
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(15 downto 0); -- access address
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signal wr_en : std_ulogic; -- word write enable
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-- timer regs --
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signal ctrl : std_ulogic_vector(06 downto 0); -- r/w: control register
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signal thres : std_ulogic_vector(15 downto 0); -- -/w: threshold register
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signal cnt : std_ulogic_vector(15 downto 0); -- r/-: counter register
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-- prescaler clock generator --
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signal prsc_tick : std_ulogic;
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-- timer control --
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signal match : std_ulogic; -- set if thres == cnt
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signal irq_fire : std_ulogic;
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signal irq_fire_ff : std_ulogic;
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begin
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-- Access Control -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = timer_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= timer_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
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wr_en <= acc_en and wren_i;
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-- Write access -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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wr_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wr_en = '1') then
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if (addr = timer_thres_addr_c) then
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thres <= data_i;
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end if;
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if (addr = timer_ctrl_addr_c) then
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ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
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ctrl(ctrl_arst_c) <= data_i(ctrl_arst_c);
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ctrl(ctrl_irq_en_c) <= data_i(ctrl_irq_en_c);
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ctrl(ctrl_run_c) <= data_i(ctrl_run_c);
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ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
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ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
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ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
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end if;
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end if;
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end if;
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end process wr_access;
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-- enable external clock generator --
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clkgen_en_o <= ctrl(ctrl_en_c);
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-- Counter update -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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timer_cnt_core: process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- clock_enable buffer --
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prsc_tick <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
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-- irq edge detector --
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irq_fire_ff <= irq_fire;
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-- counter update --
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if (ctrl(ctrl_en_c) = '0') then -- timer disabled
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cnt <= (others => '0');
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elsif (ctrl(ctrl_run_c) = '1') then -- timer enabled, but is it started?
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if (match = '1') and (ctrl(ctrl_arst_c) = '1') then -- threshold match and auto reset?
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cnt <= (others => '0');
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elsif (match = '0') and (prsc_tick = '1') then -- count++
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cnt <= std_ulogic_vector(unsigned(cnt) + 1);
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end if;
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end if;
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end if;
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end process timer_cnt_core;
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-- match --
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match <= '1' when (cnt = thres) else '0';
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-- interrupt line --
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irq_fire <= match and ctrl(ctrl_en_c) and ctrl(ctrl_irq_en_c); -- and ctrl(ctrl_run_c);
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-- edge detector --
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irq_o <= irq_fire and (not irq_fire_ff);
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-- Read access --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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rd_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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data_o <= (others => '0');
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if (rden_i = '1') and (acc_en = '1') then
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if (addr = timer_ctrl_addr_c) then
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data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
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data_o(ctrl_arst_c) <= ctrl(ctrl_arst_c);
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data_o(ctrl_irq_en_c) <= ctrl(ctrl_irq_en_c);
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data_o(ctrl_run_c) <= ctrl(ctrl_run_c);
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data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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else--if (addr = timer_cnt_addr_c) then
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data_o <= cnt;
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-- else -- (addr = timer_thres_addr_c) then
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-- data_o <= thres;
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end if;
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end if;
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end if;
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end process rd_access;
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end neo430_timer_rtl;
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