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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - Two Wire Serial Interface Master (I2C) >> #
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-- # ********************************************************************************************* #
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-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
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-- # Supports ACKs by the master. No multi-master support and no slave mode support yet! #
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-- # Interrupt: TWI_transfer_done #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_twi is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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addr_i : in std_ulogic_vector(15 downto 0); -- address
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data_i : in std_ulogic_vector(15 downto 0); -- data in
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data_o : out std_ulogic_vector(15 downto 0); -- data out
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- com lines --
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twi_sda_io : inout std_logic; -- serial data line
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twi_scl_io : inout std_logic; -- serial clock line
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-- interrupt --
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twi_irq_o : out std_ulogic -- transfer done IRQ
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);
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end neo430_twi;
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architecture neo430_twi_rtl of neo430_twi is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit
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-- control reg bits --
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constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI unit is busy
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constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
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constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
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constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
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constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
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constant ctrl_twi_mack_c : natural := 8; -- r/w: generate ACK by master for transmission
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-- data register flags --
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constant data_twi_ack_c : natural := 15; -- r/-: Set if ACK received
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(15 downto 0); -- access address
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signal wr_en : std_ulogic; -- word write enable
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signal rd_en : std_ulogic; -- read enable
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-- twi clocking --
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signal twi_clk : std_ulogic;
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signal twi_phase_gen : std_ulogic_vector(3 downto 0);
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signal twi_clk_phase : std_ulogic_vector(3 downto 0);
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-- twi clock stretching --
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signal twi_clk_halt : std_ulogic;
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-- twi transceiver core --
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signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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-- tri-state I/O --
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signal twi_sda_i_ff0, twi_sda_i_ff1 : std_ulogic; -- sda input sync
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signal twi_scl_i_ff0, twi_scl_i_ff1 : std_ulogic; -- sda input sync
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signal twi_sda_i, twi_sda_o : std_ulogic;
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signal twi_scl_i, twi_scl_o : std_ulogic;
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begin
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-- Access Control -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= twi_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
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wr_en <= acc_en and wren_i;
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rd_en <= acc_en and rden_i;
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-- Write access -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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wr_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wr_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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ctrl <= data_i(ctrl'left downto 0);
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end if;
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end if;
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end if;
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end process wr_access;
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-- Clock Generation ---------------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- clock generator enable --
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clkgen_en_o <= ctrl(ctrl_twi_en_c);
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-- main twi clock select --
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twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
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-- generate four non-overlapping clock ticks at twi_clk/4 --
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clock_phase_gen: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
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twi_phase_gen <= "0001"; -- make sure to start with a new phase, 0,1,2,3 stepping
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elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
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twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
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end if;
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end if;
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end process clock_phase_gen;
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twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
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twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
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twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
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twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
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-- TWI transceiver ----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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twi_rtx_unit: process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- input synchronizer & sampler --
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twi_sda_i_ff0 <= twi_sda_i;
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twi_sda_i_ff1 <= twi_sda_i_ff0;
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twi_scl_i_ff0 <= twi_scl_i;
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twi_scl_i_ff1 <= twi_scl_i_ff0;
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-- defaults --
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twi_irq_o <= '0';
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arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
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-- arbiter FSM --
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-- TWI bus signals are set/sampled using 4 clock phases
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case arbiter is
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when "100" => -- IDLE: waiting for requests, bus might be still claimed by this master if no STOP condition was generated
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twi_bitcnt <= (others => '0');
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if (wr_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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if (data_i(ctrl_twi_start_c) = '1') then -- issue START condition
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arbiter(1 downto 0) <= "01";
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elsif (data_i(ctrl_twi_stop_c) = '1') then -- issue STOP condition
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arbiter(1 downto 0) <= "10";
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end if;
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elsif (addr = twi_rtx_addr_c) then -- start a data transmission
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-- one bit extra for ack, issued by master if ctrl_twi_mack_c is set,
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-- sampled from slave if ctrl_twi_mack_c is cleared
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twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
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arbiter(1 downto 0) <= "11";
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end if;
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end if;
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when "101" => -- START: generate START condition
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if (twi_clk_phase(0) = '1') then
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twi_sda_o <= '1';
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elsif (twi_clk_phase(1) = '1') then
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twi_sda_o <= '0';
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end if;
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if (twi_clk_phase(0) = '1') then
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twi_scl_o <= '1';
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elsif (twi_clk_phase(3) = '1') then
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twi_scl_o <= '0';
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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when "110" => -- STOP: generate STOP condition
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if (twi_clk_phase(0) = '1') then
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twi_sda_o <= '0';
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elsif (twi_clk_phase(3) = '1') then
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twi_sda_o <= '1';
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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end if;
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if (twi_clk_phase(0) = '1') then
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twi_scl_o <= '0';
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elsif (twi_clk_phase(1) = '1') then
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twi_scl_o <= '1';
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end if;
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when "111" => -- TRANSMISSION: transmission in progress
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if (twi_clk_phase(0) = '1') then
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twi_bitcnt <= std_ulogic_vector(unsigned(twi_bitcnt) + 1);
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twi_scl_o <= '0';
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twi_sda_o <= twi_rtx_sreg(8); -- MSB first
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elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe
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twi_scl_o <= '1';
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elsif (twi_clk_phase(3) = '1') then
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twi_rtx_sreg <= twi_rtx_sreg(7 downto 0) & twi_sda_i_ff1; -- sample and shift left
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twi_scl_o <= '0';
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end if;
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if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled
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end if;
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when others => -- "0--" OFFLINE: TWI deactivated
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twi_sda_o <= '1';
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twi_scl_o <= '1';
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arbiter <= ctrl(ctrl_twi_en_c) & "00"; -- stay here, go to idle when activated
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end case;
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end if;
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end process twi_rtx_unit;
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-- Clock Stretching Detector ------------------------------------------------
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-- -----------------------------------------------------------------------------
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clock_stretching: process(arbiter, twi_scl_o, twi_scl_i_ff1)
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begin
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-- clock stretching by the slave can happen at "any time"
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if (arbiter(2) = '1') and -- module enabled
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(twi_scl_o = '1') and -- master wants to pull scl high
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(twi_scl_i_ff1 = '0') then -- but scl is pulled low by slave
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twi_clk_halt <= '1';
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else
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twi_clk_halt <= '0';
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end if;
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end process clock_stretching;
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-- Read access --------------------------------------------------------------
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269 |
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-- -----------------------------------------------------------------------------
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rd_access: process(clk_i)
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begin
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272 |
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if rising_edge(clk_i) then
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data_o <= (others => '0');
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if (rd_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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data_o(ctrl_twi_en_c) <= ctrl(ctrl_twi_en_c);
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data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
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data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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else -- twi_rtx_addr_c =>
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data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
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data_o(data_twi_ack_c) <= not twi_rtx_sreg(0);
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end if;
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end if;
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end if;
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289 |
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end process rd_access;
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290 |
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291 |
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292 |
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-- Tri-State Driver ---------------------------------------------------------
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293 |
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-- -----------------------------------------------------------------------------
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294 |
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-- SDA and SCL need to be of type std_logic to be correctly resolved in simulation
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295 |
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twi_sda_io <= '0' when (twi_sda_o = '0') else 'Z';
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296 |
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twi_scl_io <= '0' when (twi_scl_o = '0') else 'Z';
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297 |
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298 |
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-- read-back --
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299 |
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twi_sda_i <= std_ulogic(twi_sda_io);
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300 |
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twi_scl_i <= std_ulogic(twi_scl_io);
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301 |
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302 |
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|
303 |
|
|
end neo430_twi_rtl;
|