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[/] [neo430/] [trunk/] [neo430/] [rtl/] [core/] [neo430_twi.vhd] - Blame information for rev 198

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1 198 zero_gravi
-- #################################################################################################
2
-- #  << NEO430 - Two Wire Serial Interface Master (I2C) >>                                        #
3
-- # ********************************************************************************************* #
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-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching.     #
5
-- # Supports ACKs by the master. No multi-master support and no slave mode support yet!           #
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-- # Interrupt: TWI_transfer_done                                                                  #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
11
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430                                    #
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-- #################################################################################################
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39
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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43
library neo430;
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use neo430.neo430_package.all;
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46
entity neo430_twi is
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  port (
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    -- host access --
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    clk_i       : in  std_ulogic; -- global clock line
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    rden_i      : in  std_ulogic; -- read enable
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    wren_i      : in  std_ulogic; -- write enable
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    addr_i      : in  std_ulogic_vector(15 downto 0); -- address
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    data_i      : in  std_ulogic_vector(15 downto 0); -- data in
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    data_o      : out std_ulogic_vector(15 downto 0); -- data out
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    -- clock generator --
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    clkgen_en_o : out std_ulogic; -- enable clock generator
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    clkgen_i    : in  std_ulogic_vector(07 downto 0);
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    -- com lines --
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    twi_sda_io  : inout std_logic; -- serial data line
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    twi_scl_io  : inout std_logic; -- serial clock line
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    -- interrupt --
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    twi_irq_o   : out std_ulogic -- transfer done IRQ
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  );
64
end neo430_twi;
65
 
66
architecture neo430_twi_rtl of neo430_twi is
67
 
68
  -- IO space: module base address --
69
  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
70
  constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit
71
 
72
  -- control reg bits --
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  constant ctrl_twi_en_c     : natural := 0; -- r/w: TWI enable
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  constant ctrl_twi_start_c  : natural := 1; -- -/w: Generate START condition
75
  constant ctrl_twi_stop_c   : natural := 2; -- -/w: Generate STOP condition
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  constant ctrl_twi_busy_c   : natural := 3; -- r/-: Set if TWI unit is busy
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  constant ctrl_twi_prsc0_c  : natural := 4; -- r/w: CLK prsc bit 0
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  constant ctrl_twi_prsc1_c  : natural := 5; -- r/w: CLK prsc bit 1
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  constant ctrl_twi_prsc2_c  : natural := 6; -- r/w: CLK prsc bit 2
80
  constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
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  constant ctrl_twi_mack_c   : natural := 8; -- r/w: generate ACK by master for transmission
82
 
83
  -- data register flags --
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  constant data_twi_ack_c    : natural := 15; -- r/-: Set if ACK received
85
 
86
  -- access control --
87
  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(15 downto 0); -- access address
89
  signal wr_en  : std_ulogic; -- word write enable
90
  signal rd_en  : std_ulogic; -- read enable
91
 
92
  -- twi clocking --
93
  signal twi_clk        : std_ulogic;
94
  signal twi_phase_gen  : std_ulogic_vector(3 downto 0);
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  signal twi_clk_phase  : std_ulogic_vector(3 downto 0);
96
 
97
  -- twi clock stretching --
98
  signal twi_clk_halt : std_ulogic;
99
 
100
  -- twi transceiver core --
101
  signal ctrl         : std_ulogic_vector(8 downto 0); -- unit's control register
102
  signal arbiter      : std_ulogic_vector(2 downto 0);
103
  signal twi_bitcnt   : std_ulogic_vector(3 downto 0);
104
  signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
105
 
106
  -- tri-state I/O --
107
  signal twi_sda_i_ff0, twi_sda_i_ff1 : std_ulogic; -- sda input sync
108
  signal twi_scl_i_ff0, twi_scl_i_ff1 : std_ulogic; -- sda input sync
109
  signal twi_sda_i,     twi_sda_o     : std_ulogic;
110
  signal twi_scl_i,     twi_scl_o     : std_ulogic;
111
 
112
begin
113
 
114
  -- Access Control -----------------------------------------------------------
115
  -- -----------------------------------------------------------------------------
116
  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0';
117
  addr   <= twi_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
118
  wr_en  <= acc_en and wren_i;
119
  rd_en  <= acc_en and rden_i;
120
 
121
 
122
  -- Write access -------------------------------------------------------------
123
  -- -----------------------------------------------------------------------------
124
  wr_access: process(clk_i)
125
  begin
126
    if rising_edge(clk_i) then
127
      if (wr_en = '1') then
128
        if (addr = twi_ctrl_addr_c) then
129
          ctrl <= data_i(ctrl'left downto 0);
130
        end if;
131
      end if;
132
    end if;
133
  end process wr_access;
134
 
135
 
136
  -- Clock Generation ---------------------------------------------------------
137
  -- -----------------------------------------------------------------------------
138
  -- clock generator enable --
139
  clkgen_en_o <= ctrl(ctrl_twi_en_c);
140
 
141
  -- main twi clock select --
142
  twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
143
 
144
  -- generate four non-overlapping clock ticks at twi_clk/4 --
145
  clock_phase_gen: process(clk_i)
146
  begin
147
    if rising_edge(clk_i) then
148
      if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
149
        twi_phase_gen <= "0001"; -- make sure to start with a new phase, 0,1,2,3 stepping
150
      elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
151
        twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
152
      end if;
153
    end if;
154
  end process clock_phase_gen;
155
 
156
  twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
157
  twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
158
  twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
159
  twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
160
 
161
 
162
  -- TWI transceiver ----------------------------------------------------------
163
  -- -----------------------------------------------------------------------------
164
  twi_rtx_unit: process(clk_i)
165
  begin
166
    if rising_edge(clk_i) then
167
      -- input synchronizer & sampler --
168
      twi_sda_i_ff0 <= twi_sda_i;
169
      twi_sda_i_ff1 <= twi_sda_i_ff0;
170
      twi_scl_i_ff0 <= twi_scl_i;
171
      twi_scl_i_ff1 <= twi_scl_i_ff0;
172
 
173
      -- defaults --
174
      twi_irq_o  <= '0';
175
      arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
176
 
177
      -- arbiter FSM --
178
      -- TWI bus signals are set/sampled using 4 clock phases
179
      case arbiter is
180
 
181
        when "100" => -- IDLE: waiting for requests, bus might be still claimed by this master if no STOP condition was generated
182
          twi_bitcnt <= (others => '0');
183
          if (wr_en = '1') then
184
            if (addr = twi_ctrl_addr_c) then
185
              if (data_i(ctrl_twi_start_c) = '1') then -- issue START condition
186
                arbiter(1 downto 0) <= "01";
187
              elsif (data_i(ctrl_twi_stop_c) = '1') then  -- issue STOP condition
188
                arbiter(1 downto 0) <= "10";
189
              end if;
190
            elsif (addr = twi_rtx_addr_c) then -- start a data transmission
191
              -- one bit extra for ack, issued by master if ctrl_twi_mack_c is set,
192
              -- sampled from slave if ctrl_twi_mack_c is cleared
193
              twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
194
              arbiter(1 downto 0) <= "11";
195
            end if;
196
          end if;
197
 
198
        when "101" => -- START: generate START condition
199
          if (twi_clk_phase(0) = '1') then
200
            twi_sda_o <= '1';
201
          elsif (twi_clk_phase(1) = '1') then
202
            twi_sda_o <= '0';
203
          end if;
204
 
205
          if (twi_clk_phase(0) = '1') then
206
            twi_scl_o <= '1';
207
          elsif (twi_clk_phase(3) = '1') then
208
            twi_scl_o <= '0';
209
            arbiter(1 downto 0) <= "00"; -- go back to IDLE
210
          end if;
211
 
212
        when "110" => -- STOP: generate STOP condition
213
          if (twi_clk_phase(0) = '1') then
214
            twi_sda_o <= '0';
215
          elsif (twi_clk_phase(3) = '1') then
216
            twi_sda_o <= '1';
217
            arbiter(1 downto 0) <= "00"; -- go back to IDLE
218
          end if;
219
 
220
          if (twi_clk_phase(0) = '1') then
221
            twi_scl_o <= '0';
222
          elsif (twi_clk_phase(1) = '1') then
223
            twi_scl_o <= '1';
224
          end if;
225
 
226
        when "111" => -- TRANSMISSION: transmission in progress
227
          if (twi_clk_phase(0) = '1') then
228
            twi_bitcnt   <= std_ulogic_vector(unsigned(twi_bitcnt) + 1);
229
            twi_scl_o    <= '0';
230
            twi_sda_o    <= twi_rtx_sreg(8); -- MSB first
231
          elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe
232
            twi_scl_o    <= '1';
233
          elsif (twi_clk_phase(3) = '1') then
234
            twi_rtx_sreg <= twi_rtx_sreg(7 downto 0) & twi_sda_i_ff1; -- sample and shift left
235
            twi_scl_o    <= '0';
236
          end if;
237
 
238
          if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
239
            arbiter(1 downto 0) <= "00"; -- go back to IDLE
240
            twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled
241
          end if;
242
 
243
        when others => -- "0--" OFFLINE: TWI deactivated
244
          twi_sda_o <= '1';
245
          twi_scl_o <= '1';
246
          arbiter   <= ctrl(ctrl_twi_en_c) & "00"; -- stay here, go to idle when activated
247
 
248
      end case;
249
    end if;
250
  end process twi_rtx_unit;
251
 
252
 
253
  -- Clock Stretching Detector ------------------------------------------------
254
  -- -----------------------------------------------------------------------------
255
  clock_stretching: process(arbiter, twi_scl_o, twi_scl_i_ff1)
256
  begin
257
    -- clock stretching by the slave can happen at "any time"
258
    if (arbiter(2) = '1') and     -- module enabled
259
       (twi_scl_o = '1') and      -- master wants to pull scl high
260
       (twi_scl_i_ff1 = '0') then -- but scl is pulled low by slave
261
      twi_clk_halt <= '1';
262
    else
263
      twi_clk_halt <= '0';
264
    end if;
265
  end process clock_stretching;
266
 
267
 
268
  -- Read access --------------------------------------------------------------
269
  -- -----------------------------------------------------------------------------
270
  rd_access: process(clk_i)
271
  begin
272
    if rising_edge(clk_i) then
273
      data_o <= (others => '0');
274
      if (rd_en = '1') then
275
        if (addr = twi_ctrl_addr_c) then
276
          data_o(ctrl_twi_en_c)     <= ctrl(ctrl_twi_en_c);
277
          data_o(ctrl_twi_prsc0_c)  <= ctrl(ctrl_twi_prsc0_c);
278
          data_o(ctrl_twi_prsc1_c)  <= ctrl(ctrl_twi_prsc1_c);
279
          data_o(ctrl_twi_prsc2_c)  <= ctrl(ctrl_twi_prsc2_c);
280
          data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
281
          data_o(ctrl_twi_busy_c)   <= arbiter(1) or arbiter(0);
282
          data_o(ctrl_twi_mack_c)   <= ctrl(ctrl_twi_mack_c);
283
        else -- twi_rtx_addr_c =>
284
          data_o(7 downto 0)        <= twi_rtx_sreg(8 downto 1);
285
          data_o(data_twi_ack_c)    <= not twi_rtx_sreg(0);
286
        end if;
287
      end if;
288
    end if;
289
  end process rd_access;
290
 
291
 
292
  -- Tri-State Driver ---------------------------------------------------------
293
  -- -----------------------------------------------------------------------------
294
  -- SDA and SCL need to be of type std_logic to be correctly resolved in simulation
295
  twi_sda_io <= '0' when (twi_sda_o = '0') else 'Z';
296
  twi_scl_io <= '0' when (twi_scl_o = '0') else 'Z';
297
 
298
  -- read-back --
299
  twi_sda_i <= std_ulogic(twi_sda_io);
300
  twi_scl_i <= std_ulogic(twi_scl_io);
301
 
302
 
303
end neo430_twi_rtl;

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