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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - 32-bit Wishbone Bus Interface Adapter >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_wb_interface is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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addr_i : in std_ulogic_vector(15 downto 0); -- address
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data_i : in std_ulogic_vector(15 downto 0); -- data in
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data_o : out std_ulogic_vector(15 downto 0); -- data out
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-- wishbone interface --
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_ack_i : in std_ulogic -- transfer acknowledge
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);
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end neo430_wb_interface;
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architecture neo430_wb_interface_rtl of neo430_wb_interface is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(wb32_size_c); -- low address boundary bit
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-- control reg bits --
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constant ctrl_byte_en0_c : natural := 0; -- -/w: wishbone data byte enable bit 0
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constant ctrl_byte_en1_c : natural := 1; -- -/w: wishbone data byte enable bit 1
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constant ctrl_byte_en2_c : natural := 2; -- -/w: wishbone data byte enable bit 2
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constant ctrl_byte_en3_c : natural := 3; -- -/w: wishbone data byte enable bit 3
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constant ctrl_pending_c : natural := 15; -- r/-: pending wb transfer
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(15 downto 0); -- access address
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signal wr_en : std_ulogic;
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-- accessible regs --
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signal wb_addr : std_ulogic_vector(31 downto 0);
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signal wb_rdata : std_ulogic_vector(31 downto 0);
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signal wb_wdata : std_ulogic_vector(31 downto 0);
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signal pending : std_ulogic; -- pending transfer?
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signal byte_en : std_ulogic_vector(03 downto 0);
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-- misc --
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signal enable : std_ulogic;
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begin
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-- Access control -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wb32_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= wb32_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
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wr_en <= acc_en and wren_i;
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-- Write access -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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wr_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wr_en = '1') then -- valid word write
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if (addr = wb32_rd_adr_lo_addr_c) then
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wb_addr(15 downto 0) <= data_i;
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wb_we_o <= '0';
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end if;
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if (addr = wb32_rd_adr_hi_addr_c) then
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wb_addr(31 downto 16) <= data_i;
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wb_we_o <= '0';
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end if;
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if (addr = wb32_wr_adr_lo_addr_c) then
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wb_addr(15 downto 0) <= data_i;
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wb_we_o <= '1';
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end if;
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if (addr = wb32_wr_adr_hi_addr_c) then
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wb_addr(31 downto 16) <= data_i;
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wb_we_o <= '1';
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end if;
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if (addr = wb32_data_lo_addr_c) then
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wb_wdata(15 downto 0) <= data_i;
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end if;
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if (addr = wb32_data_hi_addr_c) then
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wb_wdata(31 downto 16) <= data_i;
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end if;
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if (addr = wb32_ctrl_addr_c) then
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byte_en(0) <= data_i(ctrl_byte_en0_c);
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byte_en(1) <= data_i(ctrl_byte_en1_c);
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byte_en(2) <= data_i(ctrl_byte_en2_c);
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byte_en(3) <= data_i(ctrl_byte_en3_c);
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end if;
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end if;
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end if;
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end process wr_access;
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-- direct output --
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wb_adr_o <= wb_addr; -- address
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wb_dat_o <= wb_wdata; -- write data
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wb_sel_o <= byte_en; -- byte enable
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-- Access arbiter -------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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arbiter: process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- trigger transfer --
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if (pending = '0') or (enable = '0') then
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wb_stb_o <= '0';
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pending <= '0';
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if (wr_en = '1') and (enable = '1') and ((addr_i = wb32_rd_adr_hi_addr_c) or (addr_i = wb32_wr_adr_hi_addr_c)) then
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wb_stb_o <= '1';
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pending <= '1';
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end if;
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else -- transfer in progress
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wb_stb_o <= '0'; -- use ONLY standard/classic cycle with single-cycle STB assertion!!
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-- waiting for ACK
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if (wb_ack_i = '1') then
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wb_rdata <= wb_dat_i; -- sample input data
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wb_stb_o <= '0';
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pending <= '0';
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end if;
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end if;
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end if;
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end process arbiter;
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-- device actually in use? --
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enable <= or_all_f(byte_en);
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-- valid cycle signal --
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wb_cyc_o <= pending;
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-- Read access --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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rd_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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data_o <= (others => '0');
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if (rden_i = '1') and (acc_en = '1') then
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if (addr = wb32_data_lo_addr_c) then
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data_o <= wb_rdata(15 downto 00);
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elsif (addr = wb32_data_hi_addr_c) then
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data_o <= wb_rdata(31 downto 16);
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else -- when wb32_ctrl_addr_c =>
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data_o(ctrl_pending_c) <= pending;
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end if;
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end if;
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end if;
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end process rd_access;
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end neo430_wb_interface_rtl;
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