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zero_gravi |
-- #################################################################################################
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-- # << NEO430 - Data memory ("DMEM") for Lattice ice40 UltraPlus >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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library iCE40UP;
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use iCE40UP.components.all;
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entity neo430_dmem is
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generic (
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DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic_vector(01 downto 0); -- write enable
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addr_i : in std_ulogic_vector(15 downto 0); -- address
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data_i : in std_ulogic_vector(15 downto 0); -- data in
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data_o : out std_ulogic_vector(15 downto 0) -- data out
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);
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end neo430_dmem;
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architecture neo430_dmem_rtl of neo430_dmem is
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-- local signals --
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signal acc_en : std_ulogic;
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signal rdata : std_ulogic_vector(15 downto 0);
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signal rden : std_ulogic;
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signal addr : integer;
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-- RAM --
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type dmem_file_t is array (0 to DMEM_SIZE/2-1) of std_ulogic_vector(7 downto 0);
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signal dmem_file_l : dmem_file_t;
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signal dmem_file_h : dmem_file_t;
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-- RAM attribute to inhibit bypass-logic - Intel only! --
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attribute ramstyle : string;
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attribute ramstyle of dmem_file_l : signal is "no_rw_check";
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attribute ramstyle of dmem_file_h : signal is "no_rw_check";
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-- RAM attribute to inhibit bypass-logic - Lattice ICE40up only! --
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attribute syn_ramstyle : string;
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attribute syn_ramstyle of dmem_file_l : signal is "no_rw_check";
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attribute syn_ramstyle of dmem_file_h : signal is "no_rw_check";
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-- SPRAM signals --
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signal spram_clk : std_logic;
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signal spram_addr : std_logic_vector(13 downto 0);
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signal spram_di : std_logic_vector(15 downto 0);
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signal spram_do : std_logic_vector(15 downto 0);
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signal spram_be : std_logic_vector(03 downto 0);
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signal spram_we : std_logic;
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begin
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-- Access Control -----------------------------------------------------------
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-- -----------------------------------------------------------------------------
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acc_en <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + DMEM_SIZE)) else '0';
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addr <= to_integer(unsigned(addr_i(index_size_f(DMEM_SIZE/2) downto 1))); -- word aligned
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-- Memory Access ------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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dmem_spram_inst : SP256K
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port map (
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AD => spram_addr, -- I
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DI => spram_di, -- I
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MASKWE => spram_be, -- I
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WE => spram_we, -- I
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CS => '1', -- I
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CK => spram_clk, -- I
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STDBY => '0', -- I
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SLEEP => '0', -- I
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PWROFF_N => '1', -- I
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DO => spram_do -- O
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);
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-- signal type conversion --
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spram_clk <= std_logic(clk_i);
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spram_addr <= std_logic_vector(addr_i(13+1 downto 0+1));
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spram_di <= std_logic_vector(data_i(15 downto 0));
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spram_we <= '1' when ((acc_en and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
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rdata <= std_ulogic_vector(spram_do);
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spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
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spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable
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buffer_ff: process(clk_i)
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begin
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-- sanity check
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if (DMEM_SIZE > 12*1024) then
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assert false report "D-mem size out of range! Max 12kB!" severity error;
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end if;
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-- buffer --
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if rising_edge(clk_i) then
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rden <= rden_i and acc_en;
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end if;
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end process buffer_ff;
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-- output gate --
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data_o <= rdata when (rden = '1') else (others => '0');
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end neo430_dmem_rtl;
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