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## Alternative Top Entities for the NEO430 Processor
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This folder provides several *alternative* TOP ENTITIES of the NEO430 processor.
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### Default Top Entity
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The default top entity of the processor is rtl/core/neo430_top.vhd. That entity propagates ALL signals
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to the outer world and features a Wishbone bus interface. The type of all entity ports is
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**std_ulogic** and **std_ulogic_vector**.
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### Test Setup Top Entity
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If you want to have a quick setup (that is also used for the implementation tutorial in the
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project's documentary) you can use the *rlt/top_templates/neo430_test.vhd* as top entity. This entity only propagates
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a minimal set of signals to the outer world (8 GPIO output signals and the UART lines). The test
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setup is intended to be some kind of "hello world" demo.
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### Top Entity with Resolved Signals
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If you need resolved port signals instead of the default's top unresolved signals, you can use the
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*rtl/top_templates/neo430_top_std_logic.vhd* as top entity. This entity uses **std_logic** and
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**std_logic_vector** as interface types.
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### Top Entity with Avalon Memory Mapped Master
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*-> still experimental <-*
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If you want to use the Avalon bus protocol instead of the default Wishbone bus connectivity, you
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can use the *rtl/top_templates/neo430_top_avm.vhd* as top entity. This unit provides the same ports as the default top
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entity, but it implements an Avalon-compatible master interface instead of a Wishbone master interface.
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From a software point of view, the Avalon bus interface is used by calling the default Wishbone transfer
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functions, since the native Wishbone interface is internally transformed to Avalon by a simple
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combinatorial bridging logic.
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Note: This setup also uses **std_logic** and **std_logic_vector** as port signal types to be compatible with
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Quartus QSYS.
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### Top Entity with AXI4-Lite Memory Mapped Master
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*-> still experimental <-*
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The *rtl/top_templates/neo430_top_axi4lite.vhd* top entity converts the processor's Wishbone bus to an AXI4-lite master compatible
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interface. From a software point of view, the AXI4-lite interface is used by calling the default Wishbone
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transfer functions.
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Note: This setup also uses **std_logic** and **std_logic_vector** as port signal types.

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