OpenCores
URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

[/] [neo430/] [trunk/] [neo430/] [rtl/] [top_templates/] [neo430_test.vhd] - Blame information for rev 198

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 198 zero_gravi
-- #################################################################################################
2
-- #  << NEO430 - Processor Test Implementation (neo430_test.vhd) >>                               #
3
-- # ********************************************************************************************* #
4
-- #  If you do not have an own design (yet), you can use this unit as top entity to play with     #
5
-- #  the NEO430 processor. Take a look at the project's documentary (chapter "Let's Get It        #
6
-- #  Started!") to get more information.                                                          #
7
-- # ********************************************************************************************* #
8
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
11
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEO430 Processor - https://github.com/stnolting/neo430                                    #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
 
43
library neo430;
44
use neo430.neo430_package.all;
45
 
46
entity neo430_test is
47
  port (
48
    -- global control --
49
    clk_i      : in  std_ulogic; -- global clock, rising edge
50
    rst_i      : in  std_ulogic; -- global reset, async, LOW-active
51
    -- parallel io --
52
    gpio_o     : out std_ulogic_vector(07 downto 0); -- parallel output
53
    -- serial com --
54
    uart_txd_o : out std_ulogic; -- UART send data
55
    uart_rxd_i : in  std_ulogic  -- UART receive data
56
  );
57
end neo430_test;
58
 
59
architecture neo430_test_rtl of neo430_test is
60
 
61
  -- local signals --
62
  signal gpio_out : std_ulogic_vector(15 downto 0);
63
  signal rst_int  : std_ulogic;
64
  signal twi_sda  : std_logic;
65
  signal twi_scl  : std_logic;
66
 
67
begin
68
 
69
  -- The Core of the Problem --------------------------------------------------
70
  -- -----------------------------------------------------------------------------
71
  neo430_top_test_inst: neo430_top
72
  generic map (
73
    -- general configuration --
74
    CLOCK_SPEED  => 100000000,        -- main clock in Hz
75
    IMEM_SIZE    => 4*1024,           -- internal IMEM size in bytes, max 48kB (default=4kB)
76
    DMEM_SIZE    => 2*1024,           -- internal DMEM size in bytes, max 12kB (default=2kB)
77
    -- additional configuration --
78
    USER_CODE    => x"CAFE",          -- custom user code
79
    -- module configuration --
80
    MULDIV_USE   => true,             -- implement multiplier/divider unit? (default=true)
81
    WB32_USE     => true,             -- implement WB32 unit? (default=true)
82
    WDT_USE      => true,             -- implement WDT? (default=true)
83
    GPIO_USE     => true,             -- implement GPIO unit? (default=true)
84
    TIMER_USE    => true,             -- implement timer? (default=true)
85
    UART_USE     => true,             -- implement UART? (default=true)
86
    CRC_USE      => true,             -- implement CRC unit? (default=true)
87
    CFU_USE      => false,            -- implement custom functions unit? (default=false)
88
    PWM_USE      => true,             -- implement PWM controller? (default=true)
89
    TWI_USE      => true,             -- implement two wire serial interface? (default=true)
90
    SPI_USE      => true,             -- implement SPI? (default=true)
91
    TRNG_USE     => false,            -- implement TRNG? (default=false)
92
    EXIRQ_USE    => true,             -- implement EXIRQ? (default=true)
93
    FREQ_GEN_USE => true,             -- implement FREQ_GEN? (default=true)
94
    -- boot configuration --
95
    BOOTLD_USE   => true,             -- implement and use bootloader? (default=true)
96
    IMEM_AS_ROM  => false             -- implement IMEM as read-only memory? (default=false)
97
  )
98
  port map (
99
    -- global control --
100
    clk_i      => clk_i,              -- global clock, rising edge
101
    rst_i      => rst_int,            -- global reset, async, low-active
102
    -- gpio --
103
    gpio_o     => gpio_out,           -- parallel output
104
    gpio_i     => x"0000",            -- parallel input
105
    -- pwm channels --
106
    pwm_o      => open,               -- pwm channels
107
    -- arbitrary frequency generator --
108
    freq_gen_o => open,               -- programmable frequency output
109
    -- serial com --
110
    uart_txd_o => uart_txd_o,         -- UART send data
111
    uart_rxd_i => uart_rxd_i,         -- UART receive data
112
    spi_sclk_o => open,               -- serial clock line
113
    spi_mosi_o => open,               -- serial data line out
114
    spi_miso_i => '0',                -- serial data line in
115
    spi_cs_o   => open,               -- SPI CS
116
    twi_sda_io => twi_sda,            -- twi serial data line
117
    twi_scl_io => twi_scl,            -- twi serial clock line
118
    -- 32-bit wishbone interface --
119
    wb_adr_o   => open,               -- address
120
    wb_dat_i   => x"00000000",        -- read data
121
    wb_dat_o   => open,               -- write data
122
    wb_we_o    => open,               -- read/write
123
    wb_sel_o   => open,               -- byte enable
124
    wb_stb_o   => open,               -- strobe
125
    wb_cyc_o   => open,               -- valid cycle
126
    wb_ack_i   => '0',                -- transfer acknowledge
127
    -- external interrupts --
128
    ext_irq_i  => "00000000",         -- external interrupt request lines
129
    ext_ack_o  => open                -- external interrupt request acknowledges
130
  );
131
 
132
  -- constrain output signals --
133
  gpio_o <= gpio_out(7 downto 0);
134
 
135
  -- internal reset (must be low-active!) --
136
  rst_int <= rst_i; -- invert me?!
137
 
138
  -- twi --
139
  twi_sda <= 'H';
140
  twi_scl <= 'H';
141
 
142
 
143
end neo430_test_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.