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-- #################################################################################################
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-- # << NEO430 - Processor Test Implementation (neo430_test.vhd) >> #
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-- # ********************************************************************************************* #
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-- # If you do not have an own design (yet), you can use this unit as top entity to play with #
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-- # the NEO430 processor. Take a look at the project's documentary (chapter "Let's Get It #
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-- # Started!") to get more information. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neo430;
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use neo430.neo430_package.all;
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entity neo430_test is
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rst_i : in std_ulogic; -- global reset, async, LOW-active
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-- parallel io --
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gpio_o : out std_ulogic_vector(07 downto 0); -- parallel output
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-- serial com --
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uart_txd_o : out std_ulogic; -- UART send data
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uart_rxd_i : in std_ulogic -- UART receive data
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);
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end neo430_test;
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architecture neo430_test_rtl of neo430_test is
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-- local signals --
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signal gpio_out : std_ulogic_vector(15 downto 0);
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signal rst_int : std_ulogic;
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signal twi_sda : std_logic;
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signal twi_scl : std_logic;
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begin
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-- The Core of the Problem --------------------------------------------------
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-- -----------------------------------------------------------------------------
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neo430_top_test_inst: neo430_top
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generic map (
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-- general configuration --
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CLOCK_SPEED => 100000000, -- main clock in Hz
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IMEM_SIZE => 4*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
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DMEM_SIZE => 2*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
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-- additional configuration --
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USER_CODE => x"CAFE", -- custom user code
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-- module configuration --
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MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
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WB32_USE => true, -- implement WB32 unit? (default=true)
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WDT_USE => true, -- implement WDT? (default=true)
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GPIO_USE => true, -- implement GPIO unit? (default=true)
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TIMER_USE => true, -- implement timer? (default=true)
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UART_USE => true, -- implement UART? (default=true)
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CRC_USE => true, -- implement CRC unit? (default=true)
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CFU_USE => false, -- implement custom functions unit? (default=false)
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PWM_USE => true, -- implement PWM controller? (default=true)
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TWI_USE => true, -- implement two wire serial interface? (default=true)
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SPI_USE => true, -- implement SPI? (default=true)
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TRNG_USE => false, -- implement TRNG? (default=false)
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EXIRQ_USE => true, -- implement EXIRQ? (default=true)
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FREQ_GEN_USE => true, -- implement FREQ_GEN? (default=true)
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-- boot configuration --
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BOOTLD_USE => true, -- implement and use bootloader? (default=true)
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IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
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)
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port map (
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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rst_i => rst_int, -- global reset, async, low-active
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-- gpio --
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gpio_o => gpio_out, -- parallel output
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gpio_i => x"0000", -- parallel input
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-- pwm channels --
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pwm_o => open, -- pwm channels
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-- arbitrary frequency generator --
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freq_gen_o => open, -- programmable frequency output
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-- serial com --
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uart_txd_o => uart_txd_o, -- UART send data
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uart_rxd_i => uart_rxd_i, -- UART receive data
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spi_sclk_o => open, -- serial clock line
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spi_mosi_o => open, -- serial data line out
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spi_miso_i => '0', -- serial data line in
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spi_cs_o => open, -- SPI CS
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twi_sda_io => twi_sda, -- twi serial data line
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twi_scl_io => twi_scl, -- twi serial clock line
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-- 32-bit wishbone interface --
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wb_adr_o => open, -- address
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wb_dat_i => x"00000000", -- read data
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wb_dat_o => open, -- write data
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wb_we_o => open, -- read/write
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wb_sel_o => open, -- byte enable
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wb_stb_o => open, -- strobe
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wb_cyc_o => open, -- valid cycle
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wb_ack_i => '0', -- transfer acknowledge
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-- external interrupts --
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ext_irq_i => "00000000", -- external interrupt request lines
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ext_ack_o => open -- external interrupt request acknowledges
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);
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-- constrain output signals --
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gpio_o <= gpio_out(7 downto 0);
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-- internal reset (must be low-active!) --
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rst_int <= rst_i; -- invert me?!
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-- twi --
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twi_sda <= 'H';
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twi_scl <= 'H';
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end neo430_test_rtl;
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