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[/] [next186_soc_pc/] [trunk/] [HW/] [ddr_186.ucf] - Blame information for rev 5

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1 2 ndumitrach 
#NET "cntrl0_ddr2_a<15>" LOC = "W3" | IOSTANDARD = SSTL18_II;
2 
#NET "cntrl0_ddr2_a<14>" LOC = "V4" | IOSTANDARD = SSTL18_II;
3 
#NET "cntrl0_ddr2_a<13>" LOC = "V3" | IOSTANDARD = SSTL18_II;
4 
NET "cntrl0_ddr2_a<12>" LOC = Y2 |IOSTANDARD = "SSTL18_II";
5 
NET "cntrl0_ddr2_a<11>" LOC = V1 |IOSTANDARD = "SSTL18_II";
6 
NET "cntrl0_ddr2_a<10>" LOC = T3 |IOSTANDARD = "SSTL18_II";
7 
NET "cntrl0_ddr2_a<9>" LOC = W2 |IOSTANDARD = "SSTL18_II";
8 
NET "cntrl0_ddr2_a<8>" LOC = W1 |IOSTANDARD = "SSTL18_II";
9 
NET "cntrl0_ddr2_a<7>" LOC = Y1 |IOSTANDARD = "SSTL18_II";
10 
NET "cntrl0_ddr2_a<6>" LOC = U1 |IOSTANDARD = "SSTL18_II";
11 
NET "cntrl0_ddr2_a<5>" LOC = U4 |IOSTANDARD = "SSTL18_II";
12 
NET "cntrl0_ddr2_a<4>" LOC = U2 |IOSTANDARD = "SSTL18_II";
13 
NET "cntrl0_ddr2_a<3>" LOC = U3 |IOSTANDARD = "SSTL18_II";
14 
NET "cntrl0_ddr2_a<2>" LOC = R1 |IOSTANDARD = "SSTL18_II";
15 
NET "cntrl0_ddr2_a<1>" LOC = T4 |IOSTANDARD = "SSTL18_II";
16 
NET "cntrl0_ddr2_a<0>" LOC = R2 |IOSTANDARD = "SSTL18_II";
17 
 
18 
NET "cntrl0_ddr2_dq<15>" LOC = F3 |IOSTANDARD = "SSTL18_II";
19 
NET "cntrl0_ddr2_dq<14>" LOC = G3 |IOSTANDARD = "SSTL18_II";
20 
NET "cntrl0_ddr2_dq<13>" LOC = F1 |IOSTANDARD = "SSTL18_II";
21 
NET "cntrl0_ddr2_dq<12>" LOC = H5 |IOSTANDARD = "SSTL18_II";
22 
NET "cntrl0_ddr2_dq<11>" LOC = H6 |IOSTANDARD = "SSTL18_II";
23 
NET "cntrl0_ddr2_dq<10>" LOC = G1 |IOSTANDARD = "SSTL18_II";
24 
NET "cntrl0_ddr2_dq<9>" LOC = G4 |IOSTANDARD = "SSTL18_II";
25 
NET "cntrl0_ddr2_dq<8>" LOC = F2 |IOSTANDARD = "SSTL18_II";
26 
NET "cntrl0_ddr2_dq<7>" LOC = H2 |IOSTANDARD = "SSTL18_II";
27 
NET "cntrl0_ddr2_dq<6>" LOC = K4 |IOSTANDARD = "SSTL18_II";
28 
NET "cntrl0_ddr2_dq<5>" LOC = L1 |IOSTANDARD = "SSTL18_II";
29 
NET "cntrl0_ddr2_dq<4>" LOC = L5 |IOSTANDARD = "SSTL18_II";
30 
NET "cntrl0_ddr2_dq<3>" LOC = L3 |IOSTANDARD = "SSTL18_II";
31 
NET "cntrl0_ddr2_dq<2>" LOC = K1 |IOSTANDARD = "SSTL18_II";
32 
NET "cntrl0_ddr2_dq<1>" LOC = K5 |IOSTANDARD = "SSTL18_II";
33 
NET "cntrl0_ddr2_dq<0>" LOC = H1 |IOSTANDARD = "SSTL18_II";
34 
 
35 
#NET "cntrl0_ddr2_ba<2>" LOC = "P5" | IOSTANDARD = SSTL18_II;
36 
NET "cntrl0_ddr2_ba<1>" LOC = R3 |IOSTANDARD = "SSTL18_II";
37 
NET "cntrl0_ddr2_ba<0>" LOC = P3 |IOSTANDARD = "SSTL18_II";
38 
NET "cntrl0_ddr2_ras_n" LOC = M3 |IOSTANDARD = "SSTL18_II";
39 
NET "cntrl0_ddr2_cas_n" LOC = M4 |IOSTANDARD = "SSTL18_II";
40 
NET "cntrl0_ddr2_we_n" LOC = N4 |IOSTANDARD = "SSTL18_II";
41 
NET "cntrl0_ddr2_ck_n" LOC = M2 |IOSTANDARD = "DIFF_SSTL18_II";
42 
NET "cntrl0_ddr2_ck" LOC = M1 |IOSTANDARD = "DIFF_SSTL18_II";
43 
NET "cntrl0_ddr2_cke" LOC = N3 |IOSTANDARD = "SSTL18_II";
44 
NET "cntrl0_ddr2_cs_n" LOC = M5 |IOSTANDARD = "SSTL18_II";
45 
NET "cntrl0_ddr2_dm<1>" LOC = E3 |IOSTANDARD = "SSTL18_II";
46 
NET "cntrl0_ddr2_dqs_n<1>" LOC = J5 |IOSTANDARD = "DIFF_SSTL18_II";
47 
NET "cntrl0_ddr2_dqs<1>" LOC = K6 |IOSTANDARD = "DIFF_SSTL18_II";
48 
NET "cntrl0_ddr2_dm<0>" LOC = J3 |IOSTANDARD = "SSTL18_II";
49 
NET "cntrl0_ddr2_dqs_n<0>" LOC = K2 |IOSTANDARD = "DIFF_SSTL18_II";
50 
NET "cntrl0_ddr2_dqs<0>" LOC = K3 |IOSTANDARD = "DIFF_SSTL18_II";
51 
NET "cntrl0_ddr2_odt" LOC = P1 |IOSTANDARD = "SSTL18_II";
52 
NET "cntrl0_rst_dqs_div_in" LOC = H4 |IOSTANDARD = "SSTL18_II";
53 
NET "cntrl0_rst_dqs_div_out" LOC = H3 |IOSTANDARD = "SSTL18_II";
54 
 
55 
NET "sys_clk_in" LOC = V12 |IOSTANDARD = "LVCMOS33";
56 
NET "CLK_50MHZ" LOC = E12 |IOSTANDARD = LVCMOS33;// | PERIOD = 20.0ns HIGH 40%;
57 
CONFIG PROHIBIT = H7;
58 
CONFIG PROHIBIT = J1;
59 
CONFIG PROHIBIT = J8;
60 
CONFIG PROHIBIT = L8;
61 
CONFIG PROHIBIT = N1;
62 
CONFIG PROHIBIT = R6;
63 
CONFIG PROHIBIT = T1;
64 
CONFIG PROHIBIT = T6;
65 
 
66 
#NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
67 
#NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
68 
#NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
69 
#NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
70 
#NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
71 
#NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
72 
#NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
73 
#NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
74 
NET "VGA_R<3>" LOC = "C8" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
75 
NET "VGA_R<2>" LOC = "B8" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
76 
NET "VGA_R<1>" LOC = "B3" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
77 
NET "VGA_R<0>" LOC = "A3" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
78 
NET "VGA_G<3>" LOC = "D6" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
79 
NET "VGA_G<2>" LOC = "C6" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
80 
NET "VGA_G<1>" LOC = "D5" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
81 
NET "VGA_G<0>" LOC = "C5" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
82 
NET "VGA_B<3>" LOC = "C9" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
83 
NET "VGA_B<2>" LOC = "B9" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
84 
NET "VGA_B<1>" LOC = "D7" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
85 
NET "VGA_B<0>" LOC = "C7" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
86 
NET "VGA_HSYNC" LOC = "C11" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
87 
NET "VGA_VSYNC" LOC = "B11" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST ;
88 
 
89 
#NET "BTN_EAST" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
90 
#NET "BTN_NORTH" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
91 
NET "BTN_SOUTH" LOC = "T15" |IOSTANDARD = LVCMOS33 |PULLDOWN ;
92 
NET "BTN_WEST" LOC = "U15" |IOSTANDARD = LVCMOS33 |PULLDOWN ;
93 
 
94 
# PS/2 connection
95 
NET "PS2_CLK1" LOC = "W12" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW |PULLUP;
96 
NET "PS2_DATA1" LOC = "V11" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW  |PULLUP;
97 
NET "PS2_CLK2" LOC = "U11" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW  |PULLUP;
98 
NET "PS2_DATA2" LOC = "Y12" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW  |PULLUP;
99 
 
100 
# RS232 connection
101 
#NET "RS232_DTE_RXD" LOC = "F16" | IOSTANDARD = LVCMOS33;
102 
#NET "RS232_DTE_TXD" LOC = "E15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
103 
NET "RS232_DCE_RXD" LOC = "E16" |IOSTANDARD = LVCMOS33;
104 
NET "RS232_DCE_TXD" LOC = "F15" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW ;
105 
 
106 
CONFIG ENABLE_SUSPEND = NO ;
107 
NET "FPGA_AWAKE" LOC = "AB15" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
108 
 
109 
NET "SD_CS" LOC = "AA21" |IOSTANDARD = LVCMOS33 |SLEW = FAST |DRIVE = 8 ;
110 
NET "SD_DI" LOC = "AB21" |IOSTANDARD = LVCMOS33 |SLEW = FAST |DRIVE = 8 ;
111 
NET "SD_CK" LOC = "AA19" |IOSTANDARD = LVCMOS33 |SLEW = FAST |DRIVE = 8 ;
112 
NET "SD_DO" LOC = "AB19" |IOSTANDARD = LVCMOS33 |PULLUP;
113 
 
114 
NET "AUD_L" LOC = "Y10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
115 
NET "AUD_R" LOC = "V10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
116 
#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
117 
NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
118 5 ndumitrach 
TIMESPEC TS_CLK_50MHZ = PERIOD "CLK_50MHZ" 55 ns HIGH 50%;
119 2 ndumitrach 
#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
120 
NET "sys_clk_in" TNM_NET = sys_clk_in;
121 5 ndumitrach 
TIMESPEC TS_sys_clk_in = PERIOD "sys_clk_in" 9 ns HIGH 50%;

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