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                    Core Name: Xilinx LogiCORE FIFO Generator
                    Version: 8.4
                    Release: 13.4
                    Release Date: January 18, 2012
 
 
================================================================================
 
This document contains the following sections:
 
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
 
================================================================================
 
1. INTRODUCTION
 
For installation instructions for this release, please go to:
 
   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
 
For system requirements:
 
   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
 
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.4
solution. For the latest core updates, see the product page at:
 
   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
 
 
2. NEW FEATURES
 
   - ISE 13.4 software support
   - Packet FIFO feature addition
 
3. SUPPORTED DEVICES
 
The following device families are supported by the core for this release.
 
Virtex-7
Virtex-7 -2L
Virtex-7 -2G
Virtex-7 XT
 
Kintex-7
Kintex-7 -2L
 
Artix-7
 
Zynq-7000*
 
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
Virtex-6 -1L XQ LXT/SXT
 
Spartan-6 XC LX/LXT
Spartan-6 XA LX/LXT
Spartan-6 XQ LX/LXT
Spartan-6 -1L XC LX
Spartan-6 -1L XQ LX
 
Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/LXT/SXT/FXT
 
Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX
 
Spartan-3 XC
Spartan-3 XA
Spartan-3A XC 3A / 3A DSP / 3AN
Spartan-3A XA 3A / 3A DSP
Spartan-3E XC
Spartan-3E XA
 
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
 
4. RESOLVED ISSUES
 
 
5. KNOWN ISSUES
 
The following are known issues for v8.4 of this core at the time of release:
 
   - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
     into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
     page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
     - CR 467240
     - AR 31379
 
   - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
     correct behavior of the FIFO status flags cannot be guaranteed after the first write.
 
     Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
     For more information and additional workaround see Answer Record 41099.
 
   - The FIFO Generator GUI is allowing the user to select the FULL Threshold Assert Value lesser than EMPTY
     Threshold Assert Value for AXI FIFO.
     - CR 613264
 
     Workaround: To work around this issue, select FULL Threshold Assert Value greater than EMPTY Threshold
     Assert Value
 
 
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
 
   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
 
 
6. TECHNICAL SUPPORT
 
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
 
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
 
 
7. CORE RELEASE HISTORY
 
Date        By            Version      Description
================================================================================
01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition
10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
================================================================================
 
8. Legal Disclaimer
 
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
 
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
 
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
 
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
 
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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[/] [next186_soc_pc/] [trunk/] [HW/] [ipcore_dir/] [fifo_generator_v8_4_readme.txt] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ndumitrach	`Core Name: Xilinx LogiCORE FIFO Generator`
2			`Version: 8.4`
3			`Release: 13.4`
4			`Release Date: January 18, 2012`
5
6
7			`================================================================================`
8
9			`This document contains the following sections:`
10
11			`1. Introduction`
12			`2. New Features`
13			`3. Supported Devices`
14			`4. Resolved Issues`
15			`5. Known Issues`
16			`6. Technical Support`
17			`7. Core Release History`
18			`8. Legal Disclaimer`
19
20			`================================================================================`
21
22			`1. INTRODUCTION`
23
24			`For installation instructions for this release, please go to:`
25
26			`http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm`
27
28			`For system requirements:`
29
30			`http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm`
31
32			`This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.4`
33			`solution. For the latest core updates, see the product page at:`
34
35			`http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm`
36
37
38			`2. NEW FEATURES`
39
40			`- ISE 13.4 software support`
41			`- Packet FIFO feature addition`
42
43			`3. SUPPORTED DEVICES`
44
45			`The following device families are supported by the core for this release.`
46
47			`Virtex-7`
48			`Virtex-7 -2L`
49			`Virtex-7 -2G`
50			`Virtex-7 XT`
51
52			`Kintex-7`
53			`Kintex-7 -2L`
54
55			`Artix-7`
56
57			`Zynq-7000*`
58
59			`Virtex-6 XC CXT/LXT/SXT/HXT`
60			`Virtex-6 XQ LXT/SXT`
61			`Virtex-6 -1L XC LXT/SXT`
62			`Virtex-6 -1L XQ LXT/SXT`
63
64			`Spartan-6 XC LX/LXT`
65			`Spartan-6 XA LX/LXT`
66			`Spartan-6 XQ LX/LXT`
67			`Spartan-6 -1L XC LX`
68			`Spartan-6 -1L XQ LX`
69
70			`Virtex-5 XC LX/LXT/SXT/TXT/FXT`
71			`Virtex-5 XQ LX/LXT/SXT/FXT`
72
73			`Virtex-4 XC LX/SX/FX`
74			`Virtex-4 XQ LX/SX/FX`
75			`Virtex-4 XQR LX/SX/FX`
76
77			`Spartan-3 XC`
78			`Spartan-3 XA`
79			`Spartan-3A XC 3A / 3A DSP / 3AN`
80			`Spartan-3A XA 3A / 3A DSP`
81			`Spartan-3E XC`
82			`Spartan-3E XA`
83
84			`*To access these devices in the ISE Design Suite, contact your Xilinx FAE.`
85
86			`4. RESOLVED ISSUES`
87
88
89			`5. KNOWN ISSUES`
90
91			`The following are known issues for v8.4 of this core at the time of release:`
92
93			`- In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)`
94			`into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,`
95			`page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.`
96			`- CR 467240`
97			`- AR 31379`
98
99			`- When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,`
100			`correct behavior of the FIFO status flags cannot be guaranteed after the first write.`
101
102			`Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.`
103			`For more information and additional workaround see Answer Record 41099.`
104
105			`- The FIFO Generator GUI is allowing the user to select the FULL Threshold Assert Value lesser than EMPTY`
106			`Threshold Assert Value for AXI FIFO.`
107			`- CR 613264`
108
109			`Workaround: To work around this issue, select FULL Threshold Assert Value greater than EMPTY Threshold`
110			`Assert Value`
111
112
113			`The most recent information, including known issues, workarounds, and`
114			`resolutions for this version is provided in the IP Release Notes User Guide`
115			`located at`
116
117			`www.xilinx.com/support/documentation/user_guides/xtp025.pdf`
118
119
120			`6. TECHNICAL SUPPORT`
121
122			`To obtain technical support, create a WebCase at www.xilinx.com/support.`
123			`Questions are routed to a team with expertise using this product.`
124
125			`Xilinx provides technical support for use of this product when used`
126			`according to the guidelines described in the core documentation, and`
127			`cannot guarantee timing, functionality, or support of this product for`
128			`designs that do not follow specified guidelines.`
129
130
131			`7. CORE RELEASE HISTORY`
132
133			`Date By Version Description`
134			`================================================================================`
135			`01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition`
136			`10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support`
137			`06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support`
138			`03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support`
139			`10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support`
140			`09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support`
141			`07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support`
142			`06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support`
143			`04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support`
144			`12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support`
145			`09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support`
146			`06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support`
147			`04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support`
148			`09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes`
149			`03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes`
150			`10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs`
151			`08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO`
152			`04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support`
153			`09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support`
154			`07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support`
155			`01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3`
156			`08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2`
157			`04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1`
158			`11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0`
159			`05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support`
160			`04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release`
161			`================================================================================`
162
163			`8. Legal Disclaimer`
164
165			`(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.`
166
167			`This file contains confidential and proprietary information`
168			`of Xilinx, Inc. and is protected under U.S. and`
169			`international copyright and other intellectual property`
170			`laws.`
171
172			`DISCLAIMER`
173			`This disclaimer is not a license and does not grant any`
174			`rights to the materials distributed herewith. Except as`
175			`otherwise provided in a valid license issued to you by`
176			`Xilinx, and to the maximum extent permitted by applicable`
177			`law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
178			`WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
179			`AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
180			`BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
181			`INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
182			`(2) Xilinx shall not be liable (whether in contract or tort,`
183			`including negligence, or under any other theory of`
184			`liability) for any loss or damage of any kind or nature`
185			`related to, arising under or in connection with these`
186			`materials, including for any direct, or any indirect,`
187			`special, incidental, or consequential loss or damage`
188			`(including loss of data, profits, goodwill, or any type of`
189			`loss or damage suffered as a result of any action brought`
190			`by a third party) even if such damage or loss was`
191			`reasonably foreseeable or Xilinx had been advised of the`
192			`possibility of the same.`
193
194			`CRITICAL APPLICATIONS`
195			`Xilinx products are not designed or intended to be fail-`
196			`safe, or for use in any application requiring fail-safe`
197			`performance, such as life-support or safety devices or`
198			`systems, Class III medical devices, nuclear facilities,`
199			`applications related to the deployment of airbags, or any`
200			`other applications that could lead to death, personal`
201			`injury, or severe property or environmental damage`
202			`(individually and collectively, "Critical`
203			`Applications"). Customer assumes the sole risk and`
204			`liability of any use of Xilinx products in Critical`
205			`Applications, subject only to applicable laws and`
206			`regulations governing limitations on product liability.`
207
208			`THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
209			`PART OF THIS FILE AT ALL TIMES.`