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[/] [opb_usblite/] [trunk/] [pcores/] [opb_usblite_v1_00_a/] [hdl/] [vhdl/] [usb_pkg.vhdl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 rehnmaak 
--
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--  USB 2.0 VHDL package
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--
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library ieee;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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package usb_pkg is
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    -- Initialization, handshake, reset.
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    component usb_init is
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        generic (
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            HSSUPPORT : boolean := false );         -- Support high speed mode
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        port (
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            CLK :           in  std_logic;          -- 60 MHz UTMI clock
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            RESET :         in  std_logic;          -- Synchronous reset
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            I_USBRST :      out std_logic;          -- High when bus reset signal detected
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            I_HIGHSPEED :   out std_logic;          -- High when attached at high speed
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            I_SUSPEND :     out std_logic;          -- High when suspended
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            P_CHIRPK :      out std_logic;
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            PHY_RESET :     out std_logic;
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            PHY_LINESTATE : in  std_logic_vector(1 downto 0);
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            PHY_OPMODE :    out std_logic_vector(1 downto 0);
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            PHY_XCVRSELECT : out std_logic;
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            PHY_TERMSELECT : out std_logic );
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    end component usb_init;
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    -- Packet-level logic and CRC handling.
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    component usb_packet is
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        port (
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            CLK :           in  std_logic;          -- 60 MHz UTMI clock
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            RESET :         in  std_logic;          -- Synchronous reset of this entity
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            P_CHIRPK :      in  std_logic;          -- High to force chirp K transmission
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            P_RXACT :       out std_logic;          -- High while receiving a packet
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            P_RXRDY :       out std_logic;          -- Indicates arrival of a byte
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            P_RXFIN :       out std_logic;          -- Indicates successfull completion
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            P_RXDAT :       out std_logic_vector(7 downto 0);   -- Received byte value
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            P_TXACT :       in  std_logic;          -- High while transmitting a packet
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            P_TXRDY :       out std_logic;          -- Request for next data byte
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            P_TXDAT :       in  std_logic_vector(7 downto 0);   -- Data byte to transmit
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            PHY_DATAIN :    in  std_logic_vector(7 downto 0);
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            PHY_DATAOUT :   out std_logic_vector(7 downto 0);
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            PHY_TXVALID :   out std_logic;
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            PHY_TXREADY :   in  std_logic;
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            PHY_RXACTIVE :  in  std_logic;
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            PHY_RXVALID :   in  std_logic;
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            PHY_RXERROR :   in  std_logic );
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    end component usb_packet;
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    -- Transaction-level logic.
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    component usb_transact is
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        generic (
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            HSSUPPORT : boolean := false );         -- Support high speed mode
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        port (
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            CLK :       in  std_logic;              -- 60 MHz UTMI clock
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            RESET :     in  std_logic;              -- Synchronous reset of this entity
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            T_IN :      out std_logic;              -- High during IN transactions
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            T_OUT :     out std_logic;              -- High during OUT transactions
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            T_SETUP :   out std_logic;              -- High during SETUP transactions
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            T_PING :    out std_logic;              -- High during PING transactions
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            T_FIN :     out std_logic;              -- Indicates successfull completion
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            T_ADDR :    in  std_logic_vector(6 downto 0);   -- Device address
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            T_ENDPT :   out std_logic_vector(3 downto 0);   -- Endpoint number
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            T_NAK :     in  std_logic;              -- Triggers a NAK response to IN/OUT
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            T_STALL :   in  std_logic;              -- Triggers a STALL response to IN/OUT
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            T_NYET :    in  std_logic;              -- Triggers a NYET response to OUT
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            T_SEND :    in  std_logic;              -- High while application has data to send
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            T_ISYNC :   in  std_logic;              -- Sync bit to use for IN transactions
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            T_OSYNC :   out std_logic;              -- Sync bit used in the OUT transaction
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            T_RXRDY :   out std_logic;              -- Indicates arrival of received byte
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            T_RXDAT :   out std_logic_vector(7 downto 0);   -- Received data
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            T_TXRDY :   out std_logic;              -- Requests next data byte to transmit
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            T_TXDAT :   in  std_logic_vector(7 downto 0);   -- Data to transmit
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            I_HIGHSPEED : in std_logic;
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            P_RXACT :   in  std_logic;
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            P_RXRDY :   in  std_logic;
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            P_RXFIN :   in  std_logic;
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            P_RXDAT :   in  std_logic_vector(7 downto 0);
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            P_TXACT :   out std_logic;
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            P_TXRDY :   in  std_logic;
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            P_TXDAT :   out std_logic_vector(7 downto 0) );
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    end component usb_transact;
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    -- Default control endpoint.
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    component usb_control is
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        generic (
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            NENDPT :    integer range 1 to 15 );    -- Highest endpoint number in use
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        port (
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            CLK :       in  std_logic;              -- 60 MHz UTMI clock
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            RESET :     in  std_logic;              -- Synchronous reset of this entity
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            C_ADDR :    out std_logic_vector(6 downto 0);   -- Current device address
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            C_CONFD :   out std_logic;              -- High when in Configured state
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            C_CLRIN :   out std_logic_vector(1 to NENDPT);  -- Trigger clearing of sync bit for IN endpoint
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            C_CLROUT :  out std_logic_vector(1 to NENDPT);  -- Trigger clearing of sync bit for OUT endpoint
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            C_HLTIN :   in  std_logic_vector(1 to NENDPT);  -- Current status of halt bit for IN endpoint
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            C_HLTOUT :  in  std_logic_vector(1 to NENDPT);  -- Current status of halt bit for OUT endpoint
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            C_SHLTIN :  out std_logic_vector(1 to NENDPT);  -- Trigger setting of halt bit for IN endpoint
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            C_SHLTOUT : out std_logic_vector(1 to NENDPT);  -- Trigger setting of halt bit for OUT endpoint
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            C_DSCBUSY : out std_logic;              -- High when accessing descriptor memory
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            C_DSCRD :   out std_logic;              -- Descriptor read enable
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            C_DSCTYP :  out std_logic_vector(2 downto 0);   -- Requested descriptor type
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            C_DSCINX :  out std_logic_vector(7 downto 0);   -- Requested descriptor index
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            C_DSCOFF :  out std_logic_vector(7 downto 0);   -- Offset within requested descriptor
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            C_DSCLEN :  in  std_logic_vector(7 downto 0);   -- Length of selected descriptor
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            C_SELFPOWERED : in std_logic;           -- High if the device is not drawing bus power
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            T_IN :      in  std_logic;
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            T_OUT :     in  std_logic;
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            T_SETUP :   in  std_logic;
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            T_PING :    in  std_logic;
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            T_FIN :     in  std_logic;
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            T_NAK :     out std_logic;
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            T_STALL :   out std_logic;
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            T_NYET :    out std_logic;
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            T_SEND :    out std_logic;
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            T_ISYNC :   out std_logic;
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            T_OSYNC :   in  std_logic;
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            T_RXRDY :   in  std_logic;
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            T_RXDAT :   in  std_logic_vector(7 downto 0);
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            T_TXRDY :   in  std_logic;
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            T_TXDAT :   out std_logic_vector(7 downto 0) );
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    end component usb_control;
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    -- Serial data transfer core.
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    component usb_serial is
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        generic (
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            VENDORID :      std_logic_vector(15 downto 0);  -- Vendor ID
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            PRODUCTID :     std_logic_vector(15 downto 0);  -- Product ID
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            VERSIONBCD :    std_logic_vector(15 downto 0);  -- Product version
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            HSSUPPORT :     boolean := false;               -- Support high speed mode
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            SELFPOWERED :   boolean := false;               -- Device does not use bus power
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            RXBUFSIZE_BITS: integer range 7 to 12 := 11;    -- Size of receive buffer
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            TXBUFSIZE_BITS: integer range 7 to 12 := 10 );  -- Size of transmit buffer
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        port (
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            CLK :           in  std_logic;          -- 60 MHz UTMI clock
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            RESET :         in  std_logic;          -- Synchronous reset
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            USBRST :        out std_logic;          -- Reset signal detected on bus
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            HIGHSPEED :     out std_logic;          -- Device operating in high speed mode
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            SUSPEND :       out std_logic;          -- Device is suspended
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            ONLINE :        out std_logic;          -- Device is in Configured state
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            RXVAL :         out std_logic;          -- Received byte available on RXDAT
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            RXDAT :         out std_logic_vector(7 downto 0);
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            RXRDY :         in  std_logic;          -- Application ready for next byte
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            RXLEN :         out std_logic_vector(RXBUFSIZE_BITS-1 downto 0);
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            TXVAL :         in  std_logic;          -- Application has data to send
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            TXDAT :         in  std_logic_vector(7 downto 0);
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            TXRDY :         out std_logic;          -- Entity ready to accept next byte
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            TXROOM :        out std_logic_vector(TXBUFSIZE_BITS-1 downto 0);
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            TXCORK :        in  std_logic;          -- Suppress data transmission
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            PHY_DATAIN :    in  std_logic_vector(7 downto 0);
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            PHY_DATAOUT :   out std_logic_vector(7 downto 0);
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            PHY_TXVALID :   out std_logic;
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            PHY_TXREADY :   in  std_logic;
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            PHY_RXACTIVE :  in  std_logic;
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            PHY_RXVALID :   in  std_logic;
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            PHY_RXERROR :   in  std_logic;
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            PHY_LINESTATE : in  std_logic_vector(1 downto 0);
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            PHY_OPMODE :    out std_logic_vector(1 downto 0);
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            PHY_XCVRSELECT: out std_logic;
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            PHY_TERMSELECT: out std_logic;
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            PHY_RESET :     out std_logic );
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    end component usb_serial;
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end package usb_pkg;

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