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[/] [opb_usblite/] [trunk/] [refdesign/] [system.mhs] - Blame information for rev 4

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
# Wed Jun 02 12:30:45 2010
# Target Board:  Xilinx Spartan-3E Starter Board Rev D
# Family:    spartan3e
# Device:    XC3S500e
# Package:   FG320
# Speed Grade:  -4
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 50.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7]
 PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]
 PORT fpga_0_Buttons_4Bit_GPIO_IO_I_pin = fpga_0_Buttons_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0]
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT opb_usblite_0_txdp_pin = opb_usblite_0_txdp, DIR = O
 PORT opb_usblite_0_txdn_pin = opb_usblite_0_txdn, DIR = O
 PORT opb_usblite_0_txdoe_pin = opb_usblite_0_txoe, DIR = O
 PORT opb_usblite_0_rxd_pin = opb_usblite_0_rxd, DIR = I
 PORT opb_usblite_0_rxdp_pin = opb_usblite_0_rxdp, DIR = I
 PORT opb_usblite_0_rxdn_pin = opb_usblite_0_rxdn, DIR = I
 
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_AREA_OPTIMIZED = 1
 PARAMETER C_INTERCONNECT = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0x44000000
 PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0x44000000
 PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER HW_VER = 7.20.d
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_USE_DCACHE = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
END
 
BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_50_0000MHz
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_50_0000MHz
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_50_0000MHz
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_4Bit
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = Buttons_4Bit
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_IO_I = fpga_0_Buttons_4Bit_GPIO_IO_I_pin
END
 
BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_SPECIAL_BOARD = S3E_STKIT
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_MEM_PARTNO = MT46V32M16-6
 PARAMETER C_MEM_BANKADDR_WIDTH = 2
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_DM_WIDTH = 2
 PARAMETER C_MEM_DQS_WIDTH = 2
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_XCL0_B_IN_USE = 1
 PARAMETER HW_VER = 5.04.a
 PARAMETER C_MPMC_BASEADDR = 0x44000000
 PARAMETER C_MPMC_HIGHADDR = 0x47ffffff
 BUS_INTERFACE XCL0 = microblaze_0_IXCL
 BUS_INTERFACE XCL0_B = microblaze_0_DXCL
 PORT MPMC_Clk0 = clk_100_0000MHzDCM0
 PORT MPMC_Clk90 = clk_100_0000MHz90DCM0
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
 PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin
 PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin
END
 
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 90
 PARAMETER C_CLKOUT0_GROUP = DCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 50000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PARAMETER C_CLKOUT3_FREQ = 48000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = NONE
 PARAMETER C_CLKOUT3_BUF = TRUE
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHz90DCM0
 PORT CLKOUT1 = clk_100_0000MHzDCM0
 PORT CLKOUT2 = clk_50_0000MHz
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
 PORT CLKOUT3 = clk_48_0000MHz
END
 
BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END
 
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a
 PORT Slowest_sync_clk = clk_50_0000MHz
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END
 
BEGIN opb_usblite
 PARAMETER INSTANCE = opb_usblite_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SOPB = opb_v20_0
 PORT txdp = opb_usblite_0_txdp
 PORT txdn = opb_usblite_0_txdn
 PORT txoe = opb_usblite_0_txoe
 PORT rxd = opb_usblite_0_rxd
 PORT rxdp = opb_usblite_0_rxdp
 PORT rxdn = opb_usblite_0_rxdn
 PORT USB_Clk = clk_48_0000MHz
END
 
BEGIN opb_v20
 PARAMETER INSTANCE = opb_v20_0
 PARAMETER HW_VER = 1.10.c
 PORT OPB_Clk = clk_50_0000MHz
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN plbv46_opb_bridge
 PARAMETER INSTANCE = plbv46_opb_bridge_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_RNG0_BASEADDR = 0xFFFF0000
 PARAMETER C_RNG0_HIGHADDR = 0xFFFF7FFF
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MOPB = opb_v20_0
END
 

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Subversion Repositories opb_usblite

[/] [opb_usblite/] [trunk/] [refdesign/] [system.mhs] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	rehnmaak
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68`
4			`# Wed Jun 02 12:30:45 2010`
5			`# Target Board: Xilinx Spartan-3E Starter Board Rev D`
6			`# Family: spartan3e`
7			`# Device: XC3S500e`
8			`# Package: FG320`
9			`# Speed Grade: -4`
10			`# Processor number: 1`
11			`# Processor 1: microblaze_0`
12			`# System clock frequency: 50.0`
13			`# Debug Interface: On-Chip HW Debug Module`
14			`# ##############################################################################`
15			`PARAMETER VERSION = 2.1.0`
16
17
18			`PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7]`
19			`PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]`
20			`PORT fpga_0_Buttons_4Bit_GPIO_IO_I_pin = fpga_0_Buttons_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]`
21			`PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O`
22			`PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O`
23			`PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O`
24			`PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O`
25			`PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O`
26			`PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O`
27			`PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O`
28			`PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]`
29			`PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0]`
30			`PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0]`
31			`PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0]`
32			`PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0]`
33			`PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO`
34			`PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000`
35			`PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1`
36			`PORT opb_usblite_0_txdp_pin = opb_usblite_0_txdp, DIR = O`
37			`PORT opb_usblite_0_txdn_pin = opb_usblite_0_txdn, DIR = O`
38			`PORT opb_usblite_0_txdoe_pin = opb_usblite_0_txoe, DIR = O`
39			`PORT opb_usblite_0_rxd_pin = opb_usblite_0_rxd, DIR = I`
40			`PORT opb_usblite_0_rxdp_pin = opb_usblite_0_rxdp, DIR = I`
41			`PORT opb_usblite_0_rxdn_pin = opb_usblite_0_rxdn, DIR = I`
42
43
44			`BEGIN microblaze`
45			`PARAMETER INSTANCE = microblaze_0`
46			`PARAMETER C_AREA_OPTIMIZED = 1`
47			`PARAMETER C_INTERCONNECT = 1`
48			`PARAMETER C_DEBUG_ENABLED = 1`
49			`PARAMETER C_ICACHE_BASEADDR = 0x44000000`
50			`PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff`
51			`PARAMETER C_CACHE_BYTE_SIZE = 8192`
52			`PARAMETER C_ICACHE_ALWAYS_USED = 1`
53			`PARAMETER C_DCACHE_BASEADDR = 0x44000000`
54			`PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff`
55			`PARAMETER C_DCACHE_BYTE_SIZE = 8192`
56			`PARAMETER C_DCACHE_ALWAYS_USED = 1`
57			`PARAMETER HW_VER = 7.20.d`
58			`PARAMETER C_USE_ICACHE = 1`
59			`PARAMETER C_USE_DCACHE = 1`
60			`BUS_INTERFACE DPLB = mb_plb`
61			`BUS_INTERFACE IPLB = mb_plb`
62			`BUS_INTERFACE DXCL = microblaze_0_DXCL`
63			`BUS_INTERFACE IXCL = microblaze_0_IXCL`
64			`BUS_INTERFACE DEBUG = microblaze_0_mdm_bus`
65			`BUS_INTERFACE DLMB = dlmb`
66			`BUS_INTERFACE ILMB = ilmb`
67			`PORT MB_RESET = mb_reset`
68			`END`
69
70			`BEGIN plb_v46`
71			`PARAMETER INSTANCE = mb_plb`
72			`PARAMETER HW_VER = 1.04.a`
73			`PORT PLB_Clk = clk_50_0000MHz`
74			`PORT SYS_Rst = sys_bus_reset`
75			`END`
76
77			`BEGIN lmb_v10`
78			`PARAMETER INSTANCE = ilmb`
79			`PARAMETER HW_VER = 1.00.a`
80			`PORT LMB_Clk = clk_50_0000MHz`
81			`PORT SYS_Rst = sys_bus_reset`
82			`END`
83
84			`BEGIN lmb_v10`
85			`PARAMETER INSTANCE = dlmb`
86			`PARAMETER HW_VER = 1.00.a`
87			`PORT LMB_Clk = clk_50_0000MHz`
88			`PORT SYS_Rst = sys_bus_reset`
89			`END`
90
91			`BEGIN lmb_bram_if_cntlr`
92			`PARAMETER INSTANCE = dlmb_cntlr`
93			`PARAMETER HW_VER = 2.10.b`
94			`PARAMETER C_BASEADDR = 0x00000000`
95			`PARAMETER C_HIGHADDR = 0x00001fff`
96			`BUS_INTERFACE SLMB = dlmb`
97			`BUS_INTERFACE BRAM_PORT = dlmb_port`
98			`END`
99
100			`BEGIN lmb_bram_if_cntlr`
101			`PARAMETER INSTANCE = ilmb_cntlr`
102			`PARAMETER HW_VER = 2.10.b`
103			`PARAMETER C_BASEADDR = 0x00000000`
104			`PARAMETER C_HIGHADDR = 0x00001fff`
105			`BUS_INTERFACE SLMB = ilmb`
106			`BUS_INTERFACE BRAM_PORT = ilmb_port`
107			`END`
108
109			`BEGIN bram_block`
110			`PARAMETER INSTANCE = lmb_bram`
111			`PARAMETER HW_VER = 1.00.a`
112			`BUS_INTERFACE PORTA = ilmb_port`
113			`BUS_INTERFACE PORTB = dlmb_port`
114			`END`
115
116			`BEGIN xps_gpio`
117			`PARAMETER INSTANCE = LEDs_8Bit`
118			`PARAMETER C_ALL_INPUTS = 0`
119			`PARAMETER C_GPIO_WIDTH = 8`
120			`PARAMETER C_INTERRUPT_PRESENT = 0`
121			`PARAMETER C_IS_DUAL = 0`
122			`PARAMETER HW_VER = 2.00.a`
123			`PARAMETER C_BASEADDR = 0x81400000`
124			`PARAMETER C_HIGHADDR = 0x8140ffff`
125			`BUS_INTERFACE SPLB = mb_plb`
126			`PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin`
127			`END`
128
129			`BEGIN xps_gpio`
130			`PARAMETER INSTANCE = DIP_Switches_4Bit`
131			`PARAMETER C_ALL_INPUTS = 1`
132			`PARAMETER C_GPIO_WIDTH = 4`
133			`PARAMETER C_INTERRUPT_PRESENT = 0`
134			`PARAMETER C_IS_DUAL = 0`
135			`PARAMETER HW_VER = 2.00.a`
136			`PARAMETER C_BASEADDR = 0x81420000`
137			`PARAMETER C_HIGHADDR = 0x8142ffff`
138			`BUS_INTERFACE SPLB = mb_plb`
139			`PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin`
140			`END`
141
142			`BEGIN xps_gpio`
143			`PARAMETER INSTANCE = Buttons_4Bit`
144			`PARAMETER C_ALL_INPUTS = 1`
145			`PARAMETER C_GPIO_WIDTH = 4`
146			`PARAMETER C_INTERRUPT_PRESENT = 0`
147			`PARAMETER C_IS_DUAL = 0`
148			`PARAMETER HW_VER = 2.00.a`
149			`PARAMETER C_BASEADDR = 0x81440000`
150			`PARAMETER C_HIGHADDR = 0x8144ffff`
151			`BUS_INTERFACE SPLB = mb_plb`
152			`PORT GPIO_IO_I = fpga_0_Buttons_4Bit_GPIO_IO_I_pin`
153			`END`
154
155			`BEGIN mpmc`
156			`PARAMETER INSTANCE = DDR_SDRAM`
157			`PARAMETER C_NUM_PORTS = 1`
158			`PARAMETER C_SPECIAL_BOARD = S3E_STKIT`
159			`PARAMETER C_MEM_TYPE = DDR`
160			`PARAMETER C_MEM_PARTNO = MT46V32M16-6`
161			`PARAMETER C_MEM_BANKADDR_WIDTH = 2`
162			`PARAMETER C_MEM_DATA_WIDTH = 16`
163			`PARAMETER C_MEM_DM_WIDTH = 2`
164			`PARAMETER C_MEM_DQS_WIDTH = 2`
165			`PARAMETER C_PIM0_BASETYPE = 1`
166			`PARAMETER C_XCL0_B_IN_USE = 1`
167			`PARAMETER HW_VER = 5.04.a`
168			`PARAMETER C_MPMC_BASEADDR = 0x44000000`
169			`PARAMETER C_MPMC_HIGHADDR = 0x47ffffff`
170			`BUS_INTERFACE XCL0 = microblaze_0_IXCL`
171			`BUS_INTERFACE XCL0_B = microblaze_0_DXCL`
172			`PORT MPMC_Clk0 = clk_100_0000MHzDCM0`
173			`PORT MPMC_Clk90 = clk_100_0000MHz90DCM0`
174			`PORT MPMC_Rst = sys_periph_reset`
175			`PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin`
176			`PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin`
177			`PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin`
178			`PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin`
179			`PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin`
180			`PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin`
181			`PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin`
182			`PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin`
183			`PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin`
184			`PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin`
185			`PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin`
186			`PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin`
187			`PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin`
188			`PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin`
189			`END`
190
191			`BEGIN clock_generator`
192			`PARAMETER INSTANCE = clock_generator_0`
193			`PARAMETER C_EXT_RESET_HIGH = 1`
194			`PARAMETER C_CLKIN_FREQ = 50000000`
195			`PARAMETER C_CLKOUT0_FREQ = 100000000`
196			`PARAMETER C_CLKOUT0_PHASE = 90`
197			`PARAMETER C_CLKOUT0_GROUP = DCM0`
198			`PARAMETER C_CLKOUT0_BUF = TRUE`
199			`PARAMETER C_CLKOUT1_FREQ = 100000000`
200			`PARAMETER C_CLKOUT1_PHASE = 0`
201			`PARAMETER C_CLKOUT1_GROUP = DCM0`
202			`PARAMETER C_CLKOUT1_BUF = TRUE`
203			`PARAMETER C_CLKOUT2_FREQ = 50000000`
204			`PARAMETER C_CLKOUT2_PHASE = 0`
205			`PARAMETER C_CLKOUT2_GROUP = NONE`
206			`PARAMETER C_CLKOUT2_BUF = TRUE`
207			`PARAMETER HW_VER = 3.02.a`
208			`PARAMETER C_CLKOUT3_FREQ = 48000000`
209			`PARAMETER C_CLKOUT3_PHASE = 0`
210			`PARAMETER C_CLKOUT3_GROUP = NONE`
211			`PARAMETER C_CLKOUT3_BUF = TRUE`
212			`PORT CLKIN = dcm_clk_s`
213			`PORT CLKOUT0 = clk_100_0000MHz90DCM0`
214			`PORT CLKOUT1 = clk_100_0000MHzDCM0`
215			`PORT CLKOUT2 = clk_50_0000MHz`
216			`PORT RST = sys_rst_s`
217			`PORT LOCKED = Dcm_all_locked`
218			`PORT CLKOUT3 = clk_48_0000MHz`
219			`END`
220
221			`BEGIN mdm`
222			`PARAMETER INSTANCE = mdm_0`
223			`PARAMETER C_MB_DBG_PORTS = 1`
224			`PARAMETER C_USE_UART = 1`
225			`PARAMETER C_UART_WIDTH = 8`
226			`PARAMETER HW_VER = 1.00.g`
227			`PARAMETER C_BASEADDR = 0x84400000`
228			`PARAMETER C_HIGHADDR = 0x8440ffff`
229			`BUS_INTERFACE SPLB = mb_plb`
230			`BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus`
231			`PORT Debug_SYS_Rst = Debug_SYS_Rst`
232			`END`
233
234			`BEGIN proc_sys_reset`
235			`PARAMETER INSTANCE = proc_sys_reset_0`
236			`PARAMETER C_EXT_RESET_HIGH = 1`
237			`PARAMETER HW_VER = 2.00.a`
238			`PORT Slowest_sync_clk = clk_50_0000MHz`
239			`PORT Ext_Reset_In = sys_rst_s`
240			`PORT MB_Debug_Sys_Rst = Debug_SYS_Rst`
241			`PORT Dcm_locked = Dcm_all_locked`
242			`PORT MB_Reset = mb_reset`
243			`PORT Bus_Struct_Reset = sys_bus_reset`
244			`PORT Peripheral_Reset = sys_periph_reset`
245			`END`
246
247			`BEGIN opb_usblite`
248			`PARAMETER INSTANCE = opb_usblite_0`
249			`PARAMETER HW_VER = 1.00.a`
250			`BUS_INTERFACE SOPB = opb_v20_0`
251			`PORT txdp = opb_usblite_0_txdp`
252			`PORT txdn = opb_usblite_0_txdn`
253			`PORT txoe = opb_usblite_0_txoe`
254			`PORT rxd = opb_usblite_0_rxd`
255			`PORT rxdp = opb_usblite_0_rxdp`
256			`PORT rxdn = opb_usblite_0_rxdn`
257			`PORT USB_Clk = clk_48_0000MHz`
258			`END`
259
260			`BEGIN opb_v20`
261			`PARAMETER INSTANCE = opb_v20_0`
262			`PARAMETER HW_VER = 1.10.c`
263			`PORT OPB_Clk = clk_50_0000MHz`
264			`PORT SYS_Rst = sys_bus_reset`
265			`END`
266
267			`BEGIN plbv46_opb_bridge`
268			`PARAMETER INSTANCE = plbv46_opb_bridge_0`
269			`PARAMETER HW_VER = 1.01.a`
270			`PARAMETER C_RNG0_BASEADDR = 0xFFFF0000`
271			`PARAMETER C_RNG0_HIGHADDR = 0xFFFF7FFF`
272			`BUS_INTERFACE SPLB = mb_plb`
273			`BUS_INTERFACE MOPB = opb_v20_0`
274			`END`
275