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/*

  Or1K instruction set-specific decoding and analysis functions.

  Julius Baxter, julius.baxter@orsoc.se

*/

// Struct for information about the register to be confugred

// Set to 1 to enable

struct or1k_32_instruction_properties

{

  int has_jumptarg;

  int has_branchtarg;

  int has_imm;

  int has_split_imm;

  int has_rD;

  int has_rA;

  int has_rB;

  char *insn_string;

};

// OpenRISC 1000 32-bit instruction defines, helping us

// extract fields of the instructions

// Instruction decode/set its options

int or1k_32_analyse_insn(uint32_t insn,

                         struct or1k_32_instruction_properties *insn_props);

// Stat collection entry-oint

void or1k_32_collect_stats(uint32_t insn,

                           struct or1k_32_instruction_properties  * insn_props);

// List management/analysis functions

// Reset lists

void or1k_32_insn_lists_init(void);

// Check for an instruction

int or1k_32_insn_lists_check(uint32_t insn,

                             struct or1k_32_instruction_properties *insn_props);

// Add a unique instruction

int or1k_32_insn_lists_add_unique_insn(uint32_t insn,

                           struct or1k_32_instruction_properties *insn_props);

// Add the stats for this one

void or1k_32_insn_lists_add(int index, uint32_t insn,

                            struct or1k_32_instruction_properties *insn_props);

// Print out some useful information

void or1k_32_generate_stats(FILE * stream);

// Free lists

void or1k_32_insn_lists_free(void);

#define JUMPTARG_MASK 0x3ffffff

#define insn_or1k_opcode(x) (x>>26 & 0x3f)

#define insn_or1k_32_rD(x) (((x>>21)&0x1f))

#define insn_or1k_32_rA(x) (((x>>16)&0x1f))

#define insn_or1k_32_rB(x) (((x>>11)&0x1f))

#define insn_or1k_32_imm(x) (x&0xffff)

#define insn_or1k_32_split_imm(x) ((((x>>21)&0x1f)<<11)|(x&0x7ff))

#define insn_or1k_opcode_0x00_get_jumptarg(x) (x&JUMPTARG_MASK)

#define insn_or1k_opcode_0x01_get_jumptarg(x) (x&JUMPTARG_MASK)

#define insn_or1k_opcode_0x03_get_branchoff(x) (x&JUMPTARG_MASK)

#define insn_or1k_opcode_0x04_get_branchoff(x) (x&JUMPTARG_MASK)

#define insn_or1k_opcode_0x05_get_noop_id(x) ((x>>24) & 0x3)

#define insn_or1k_opcode_0x05_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x06_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x06_get_id(x) ((x>>16) & 0x1)

#define insn_or1k_opcode_0x06_get_imm(x) insn_or1k_32_imm(x)

/* N/A: opcode 0x7 */

#define insn_or1k_opcode_0x08_get_id(x) ((x>>23)&0x7)

#define insn_or1k_opcode_0x08_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x0a_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x0a_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x0a_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x0a_get_op_hi(x) ((x>>4)&0xf)

#define insn_or1k_opcode_0x0a_get_op_lo(x) (x&0xf)

/* N/A: opcodes 0xb,c,d,e,f,10 */

#define insn_or1k_opcode_0x11_get_rB(x)  insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x12_get_rB(x)  insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x13_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x13_get_imm(x) insn_or1k_32_split_imm(x)

/* N/A: opcodes 0x14,15, 16, 17, 18, 19, 1a, 1b */

#define insn_or1k_opcode_0x20_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x20_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x20_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x21_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x21_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x21_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x22_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x22_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x22_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x23_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x23_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x23_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x24_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x24_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x24_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x25_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x25_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x25_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x26_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x26_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x26_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x27_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x27_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x27_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x28_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x28_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x28_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x29_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x29_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x29_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x2a_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2a_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2a_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x2b_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2b_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2b_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x2c_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2c_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2c_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x2d_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2d_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2d_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x2e_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2e_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2e_get_op(x) ((x>>6)&0x3)

#define insn_or1k_opcode_0x2e_get_imm(x) ((x&3f))

#define insn_or1k_opcode_0x2f_get_op(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x2f_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x2f_get_imm(x) insn_or1k_32_imm(x)

#define insn_or1k_opcode_0x30_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x30_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x30_get_imm(x) insn_or1k_32_split_imm(x)

#define insn_or1k_opcode_0x31_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x31_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x31_get_op(x) (x&0xf)

#define insn_or1k_opcode_0x32_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x32_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x32_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x32_get_op_hi(x) ((x>>4)&0xf)

#define insn_or1k_opcode_0x32_get_op_lo(x) ((x&0xf))

/* N/A: opcodes 0x33 */

#define insn_or1k_opcode_0x34_get_rD(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x34_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x34_get_imm(x) insn_or1k_32_split_imm(x)

#define insn_or1k_opcode_0x35_get_rD(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x35_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x35_get_imm(x) insn_or1k_32_split_imm(x)

#define insn_or1k_opcode_0x36_get_rD(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x36_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x36_get_imm(x) insn_or1k_32_split_imm(x)

#define insn_or1k_opcode_0x37_get_rD(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x37_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x37_get_imm(x) insn_or1k_32_split_imm(x)

#define insn_or1k_opcode_0x38_get_rD(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x38_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x38_get_rB(x) insn_or1k_32_rB(x)

#define insn_or1k_opcode_0x38_get_op_hi_2bit(x) ((x>>8)&0x3)

#define insn_or1k_opcode_0x38_get_op_hi_4bit(x) ((x>>6)&0xf)

#define insn_or1k_opcode_0x38_get_op_lo(x) ((x&0xf))

#define insn_or1k_opcode_0x39_get_op(x) insn_or1k_32_rD(x)

#define insn_or1k_opcode_0x39_get_rA(x) insn_or1k_32_rA(x)

#define insn_or1k_opcode_0x39_get_rB(x) insn_or1k_32_rB(x)

/* N/A: opcodes 0x3a,3b */