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[/] [ov7670-sccb/] [trunk/] [hdl/] [turkish/] [hdl/] [SCCBMaster.vhd] - Blame information for rev 4

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1 4 ibrahimvar
---------------------------------------------------------------------------------------------------------------------------------------------
2
--  OV7670 kamera modulu ayarlarinin yapilmasi icin SCCB protokolunu kullanir. Bu protokol I2C uyumludur. 
3
--  SCCB protokolu I2C'den farkli olarak lojik-1 durumuna da sahiptir.
4
--  High - Low - High Impedance
5
--
6
--  Bu protokolun en onemli noktasi; ACK ve NACK bitleri yazma islemi icin gereksizdir. Bu bitler yerine
7
--  "Don't Care" isimli lojik-0 biti kullanılır. Asagida ornek bir yazma isleminin veri paketi gorulmektedir:
8
--
9
--      |A6|A5|A4|A3|A2|A1|A0|R/W|DC|-|R7|R6|R5|R4|R3|R2|R1|R0|DC|-|D7|D6|D5|D4|D3|D2|D1|D0|DC|
10
--             7-bit Address               8-Bit Register/Data             8-bit Data
11
--         R => lojik-1
12
--         W => lojik-0
13
--  
14
--  SCCB hattindan sadece veri gonderileceginden sadece WRITE islemi eklenmistir. OV7670 kamera modulu paralel
15
--  8-bit kamera veri hatti bulunduruyor. Bu noktada READ adimi eklenmedi!
16
--  
17
--  Kullanilan kaynaklar : OV7670 Datasheet
18
--                       : OmniVision SCCB Specification
19
--                       : http://www.dejazzer.com/hardware.html (Face detection on FPGA: OV7670 CMOS camera + DE2-115 FPGA board)
20
--                       : http://www.dejazzer.com/eigenpi/digital_camera/digital_camera.html
21
--
22
--  TODO => Aciklamalari Ingilizce yap!
23
--
24
---------------------------------------------------------------------------------------------------------------------------------------------
25
 
26
 
27
library IEEE;
28
use IEEE.STD_LOGIC_1164.all;
29
use IEEE.STD_LOGIC_UNSIGNED.all;
30
use IEEE.NUMERIC_STD.all;
31
 
32
entity SCCBMaster is
33
    generic(
34
        GInputClock :   integer := 50_000_000;                  --  FPGA' nin ana clock hizi
35
        GBusClock   :   integer := 400_000                      --  SCCB hattinin calistirilmasi icin belirlenecek hiz (400 kHz SCCB fast mode)
36
    );
37
        port(
38
                PIClock     :   in      std_logic;                      --  Sistem clock girisi
39
        PIReset     :   in      std_logic;                      --  Reset(active low) girisi
40
        PIEnable    :   in      std_logic;                      --  SCCB hattini aktif edecek enable girisi
41
        PIAddress   :   in      std_logic_vector(6 downto 0);   --  SCCB hattina bagli olan slave cihazlarinin ana adreslerini isaret eden giris
42
        PIRegister  :   in      std_logic_vector(7 downto 0);   --  Slave birimin islem yapilacak register adresini belirten giris
43
        PIWriteData :   in      std_logic_vector(7 downto 0);   --  Master -> Slave yonunde yazilacak data
44
        PIStart     :   in      std_logic;                      --  SCCB master backend calistirma girisi
45
        PODone      :   out     std_logic;                      --  SCCB arayuzunun yazma islemini bitirdigini belirten cikis
46
        POReady     :   out     std_logic;                      --  SCCB arayuzunun islem yapmaya hazir oldugunu belirten cikis
47
        PIOSIOD     :   inout   std_logic;                      --  SCCB seri data cikisi - girisi
48
        POSIOC      :   out     std_logic                       --  SCCB seri clock cikisi
49
        );
50
end SCCBMaster;
51
 
52
architecture Behavioral of SCCBMaster is
53
 
54
------------------------------------------------------------------------------------------------------------------
55
--  Bu adimda sistemin calisacagi durum makinesinin durumlari, giris ve cikis portlarina baglanacak sinyaller,
56
--  durumlar icin gerekli olacak counter ve busy bitleri gibi sinyaller olusturulmustur.
57
------------------------------------------------------------------------------------------------------------------
58
 
59
    type        TStatesWrite        is  (idle, start_condition, send_addr, addr_dc, send_reg, reg_dc, send_data, data_dc, stop);
60
    signal      SStateWriteBase     :   TStatesWrite                        :=  idle;
61
 
62
    constant    CClockCountMax      :   integer                             :=  (GInputClock / GBusClock);
63
 
64
    signal      SStart              :   std_logic                           :=  '0';
65
    signal      SStartReg           :   std_logic                           :=  '0';
66
    signal      SStartedWrite       :   std_logic                           :=  '0';
67
 
68
    signal      SEnable             :   std_logic                           :=  '0';
69
    signal      SAddress            :   std_logic_vector(6 downto 0)        :=  (others => '0');
70
    signal      SRegister           :   std_logic_vector(7 downto 0)        :=  (others => '0');
71
    signal      SWriteData          :   std_logic_vector(7 downto 0)        :=  (others => '0');
72
    signal      SBusy               :   std_logic                           :=  '0';
73
    signal      SBusy2              :   std_logic                           :=  '0';
74
    signal      SDone               :   std_logic                           :=  '0';
75
    signal      SReady              :   std_logic                           :=  '0';
76
 
77
    signal      SDataClockRef       :   std_logic                           :=  '0';
78
    signal      SDataClockRefPrev   :   std_logic                           :=  '0';
79
 
80
    -- signal      SSIODClock          :   std_logic                        :=    '0';   --  DEBUG AMACLIDIR!
81
    -- signal      SSIODClockPrev      :   std_logic;                                    --  DEBUG AMACLIDIR!
82
    signal      SSIOCClock          :   std_logic                           :=  '1';
83
    signal      SSIOCClockPrev      :   std_logic;
84
 
85
    signal      SSIODWrite          :   std_logic                           :=  '0';
86
    signal      SSIODRead           :   std_logic                           :=  '0';
87
    signal      SSIOCWrite          :   std_logic                           :=  '0';
88
    signal      SSIOCRead           :   std_logic                           :=  '0';
89
 
90
    signal      SAddr               :   std_logic_vector(6 downto 0)        :=  (others => '0');
91
    signal      SReg                :   std_logic_vector(7 downto 0)        :=  (others => '0');
92
    signal      SData               :   std_logic_vector(7 downto 0)        :=  (others => '0');
93
 
94
    signal      SAddrReg            :   std_logic_vector(6 downto 0)        :=  (others => '0');
95
    signal      SRegReg             :   std_logic_vector(7 downto 0)        :=  (others => '0');
96
    signal      SDataReg            :   std_logic_vector(7 downto 0)        :=  (others => '0');
97
    signal      SCounter            :   integer range 0 to 8                :=  0;
98
 
99
    signal      SCounterSCCB        :   integer range 0 to CClockCountMax   :=  0;
100
    signal          SCounter2           :       integer range 0 to 3                :=  0;
101
 
102
 
103
begin
104
 
105
------------------------------------------------------------------------
106
--  Bu adimda giris ve cikis portlari sinyallere yonlendirilmistir.
107
------------------------------------------------------------------------
108
    SStart      <=  PIStart;
109
    SEnable     <=  PIEnable;
110
    SAddress    <=  PIAddress;
111
    SRegister   <=  PIRegister;
112
    SWriteData  <=  PIWriteData;
113
    PODone      <=  SDone;
114
    POReady     <=  SReady;
115
 
116
    POSIOC      <=  SSIOCWrite when (SStateWriteBase = idle or SStateWriteBase = start_condition or SStateWriteBase = stop ) else
117
                    SSIOCClock;
118
 
119
    PIOSIOD     <=  SSIODWrite when SEnable = '1' else 'Z';
120
 
121
    SStartReg   <=  '1' when SStart = '1' and SEnable = '1' else
122
                    '0' when (SSIOCClock = '0' and SSIOCClockPrev = '1') or PIReset = '0' or SEnable = '0' else
123
                    SStartReg;
124
 
125
-------------------------------------------------------------------------------------------------------------------------------
126
--  READY prosesi; eger yazma islemi bittiyse(SDone == '1') ve yazma durum makinesi baslangictaysa(SStateWriteBase == idle)
127
--  SReady sinyalini lojik-1 yapar. Ayrica sistem durdurulduysa(PIReset == '0') SReady sinyalini lojik-0 yapar.
128
-------------------------------------------------------------------------------------------------------------------------------
129
    READY : process(PIClock, PIReset)
130
    begin
131
        if PIReset = '0' then
132
            SReady      <= '0';
133
        elsif rising_edge(PIClock) then
134
            if SStateWriteBase = idle then
135
                SReady  <= '1';
136
            else
137
                SReady  <= '0';
138
            end if;
139
        end if;
140
    end process;
141
 
142
-------------------------------------------------------------------------------------------------------------------------------
143
--  Backend tarafina gelen baslatma sinyaline gore(SStart == '1') address, register ve data bilgilerini olusturulan register 
144
--  sinyallerine atar. Sistemin resetlenme durumuna gore bu sinyaller temizlenir.
145
-------------------------------------------------------------------------------------------------------------------------------
146
 
147
    DATA_CAPTURE : process(PIClock, PIReset)
148
    begin
149
        if PIReset = '0' then
150
            SAddrReg        <= (others => '0');
151
            SRegReg         <= (others => '0');
152
            SDataReg        <= (others => '0');
153
        elsif rising_edge(PIClock) then
154
            if SStart = '1' then
155
                SAddrReg    <= SAddress;
156
                SRegReg     <= SRegister;
157
                SDataReg    <= SWriteData;
158
            elsif SSIOCClock = '0' and SSIOCClockPrev = '1' then
159
                SAddrReg    <= SAddrReg;
160
                SRegReg     <= SRegReg;
161
                SDataReg    <= SDataReg;
162
            else
163
                SAddrReg    <= SAddrReg;
164
                SRegReg     <= SRegReg;
165
                SDataReg    <= SDataReg;
166
            end if;
167
        end if;
168
    end process;
169
 
170
-------------------------------------------------------------------------------------------------------------------------------
171
--  CLKGEN prosesi; SCCB arayuzu icin gerekli olan REFERANS saat sinyallerini uretir. Bu noktada onemli olan durum sudur:
172
--  OV7670 datasheeti incelendiginde gonderilecek veriler SIOC cikisinin lojik-0 olduğu durumun tam ortasında degistirilir. 
173
--  Bu nedenden dolayi SIOC cikisi icin ek olarak bu cikisin yari periyoduna sahip ikincil bir saat sinyali uretilir.
174
--  
175
--  |¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______    =====>>>    SIOC Referans Saat
176
--              |               |               |               |               |
177
--              |               |               |               |               |
178
--  |¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_    =====>>>    DATA Referans Saat
179
--  
180
-------------------------------------------------------------------------------------------------------------------------------
181
    CLKGEN : process(PIClock)
182
        variable    VCounter        : integer range 0 to CClockCountMax     := 0;
183
    begin
184
        if rising_edge(PIClock) then
185
            --SSIODClockPrev      <= SSIODClock;
186
            SSIOCClockPrev      <= SSIOCClock;
187
            SDataClockRefPrev   <=  SDataClockRef;
188
 
189
                                if SCounterSCCB = (CClockCountMax / 4) - 1 then
190
                                        SDataClockRef   <= not SDataClockRef;
191
                                        if SCounter2 = 1 then
192
                                                --SSIODClock  <= not SSIODClock;
193
                                                SSIOCClock   <= not SSIOCClock;
194
                                                SCounter2 <= 0;
195
                                        else
196
                                                SCounter2 <= SCounter2 + 1;
197
                                        end if;
198
                                        SCounterSCCB    <= 0;
199
                                else
200
                                        SCounterSCCB    <= SCounterSCCB +1;
201
                                end if;
202
 
203
        end if;
204
    end process;
205
 
206
-------------------------------------------------------------------------------------------------------------------------------------------
207
--  DATA_WRITE prosesi; SCCB arayuzune uygun olarak yazma islemi yapacak olan durum makinesini icerir. Aktif 0 olarak ca-
208
--  lisan PIReset, aktif oldugu durumda butun islemleri, sayicilari, cikislari ve registerleri temizler.
209
-- 
210
--                                                              !!!!ONEMLI!!!!
211
--  SCCB arayuzu, idle durumundayken SIOD hattini yuksek empedans('Z'), SIOC hattini ise lojik-1 seviyesinde tutar. Baslangic kosulu,
212
--  SIOD hattini 'Z' durumundan lojik-1 durumuna getirir, ardindan SIOC hattini referans saatin yarı periyodu kadar bekledikten sonra
213
--  lojik-0 yaparak haberlesmeyi baslatir. Bitme kosulu ise, eger baska veri yazilmayacaksa ilk olarak SIOC'yi lojik-1, ardindan SIOD
214
--  hattini yarim periyot bekledikten sonra 'Z' yapar. Ancak baska veri yazilmaya devam edecek ise SIOD hattini 'Z' yerine lojik-1 yapar.
215
--
216
--
217
--  SIOD     -------¯¯¯¯¯¯¯|                               |¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|               |¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|
218
--                         |_______________________________|               |_______________|                               |______
219
--                         |               |               |               |               |               |               |
220
--                         |               |               |               |               |               |               |
221
--                         |               |               |               |               |               |               |  
222
--  SIOC     ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|               |¯¯¯¯¯¯¯|   |   |¯¯¯¯¯¯¯|   |   |¯¯¯¯¯¯¯|   |   |¯¯¯¯¯¯¯|   |   |¯¯¯¯¯¯¯|   |    
223
--                             |_______________|       |_______|       |_______|       |_______|       |_______|       |___|______
224
--                         |               |               |               |               |               |               |
225
--                         |               |               |               |               |               |               |
226
--  SIOC Ref   |¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______ 
227
--                         |               |               |               |               |               |               |
228
--                         |               |               |               |               |               |               |
229
--  SIOD Ref   |¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_            
230
--
231
-------------------------------------------------------------------------------------------------------------------------------------------
232
 
233
    DATA_WRITE : process(PIClock, PIReset)
234
        variable VCounter : integer range 0 to 16 := 0;
235
    begin
236
        if PIReset = '0' then
237
            SStateWriteBase <= idle;
238
            SStartedWrite   <= '0';
239
            SAddr           <= (others => '0');
240
            SReg            <= (others => '0');
241
            SData           <= (others => '0');
242
            SSIODWrite      <= 'Z';
243
            SSIOCWrite      <= '1';
244
            SBusy           <= '0';
245
            SDone           <= '0';
246
            SBusy2          <= '0';
247
            VCounter        := 0;
248
            SCounter        <=  7;
249
        elsif rising_edge(PIClock) then
250
            case SStateWriteBase is
251
-------------------------------------------------------------------------------------------------------------------------------------------
252
--  "idle" durumu; SStartReg tetiklendiginde address, register ve data bilgilerini registerlerden toplar ve SIOC referans
253
--  saatinin yukselen kenarinda "start_condition" durumuna gecer.
254
--  SStartReg'in tetiklenmedigi durumda sistem reset (SIOD = 'Z' - SIOC = '1') durumunda kalir.
255
-------------------------------------------------------------------------------------------------------------------------------------------
256
                when idle =>
257
                    if SSIOCClock = '0' and SSIOCClockPrev = '1' then
258
                        if SStartReg = '1' then
259
                            SSIODWrite   <= '1';
260
                            SSIOCWrite   <= '1';
261
                            SStartedWrite    <= '1';
262
                            SDone       <= '0';
263
                            SAddr       <= SAddrReg;
264
                            SReg        <= SRegReg;
265
                            SData       <= SDataReg;
266
                        else
267
                            SAddr       <= (others => '0');
268
                            SReg        <= (others => '0');
269
                            SData       <= (others => '0');
270
                            SStateWriteBase      <= idle;
271
                            SSIODWrite   <= 'Z';
272
                            SSIOCWrite   <= '1';
273
                            SStartedWrite    <= '0';
274
                            SDone       <= '1';
275
                        end if;
276
                    elsif SSIOCClock = '1' and SSIOCClockPrev = '0' and SStartedWrite = '1' then
277
                        SSIODWrite   <= '0';
278
 
279
                        SStartedWrite    <= '0';
280
                        SStateWriteBase <= start_condition;
281
                    end if;
282
-------------------------------------------------------------------------------------------------------------------------------------------
283
--  "start_condition" durumu; 2 SIOC referans clock darbesinden sonra SIOD referansinin yukselen kenari ve SIOC referansinin
284
--  lojik-0 oldugu anda cache olarak alinan address verisinin ilk bitini sola 1 kere kaydirarak SIOD hattina yazar ve "send_addr" 
285
--  durumuna gecer.
286
-------------------------------------------------------------------------------------------------------------------------------------------
287
                when start_condition =>
288
                    if SSIOCClock = '0' and SSIOCClockPrev = '1' then
289
                        SBusy <= '1';
290
                        if SBusy = '1' then
291
                            SBusy2 <= '1';
292
                        end if;
293
                        SSIOCWrite   <= '0';
294
                    elsif SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' and SBusy2 = '1' then
295
                        if SAddr(6) = '1' then
296
                            SSIODWrite <= '1';
297
                            SAddr <= std_logic_vector(shift_left(unsigned(SAddr), 1));
298
                        elsif SAddr(6) = '0' then
299
                            SSIODWrite <= '0';
300
                            SAddr <= std_logic_vector(shift_left(unsigned(SAddr), 1));
301
                        end if;
302
                        SBusy   <= '0';
303
                        SBusy2   <= '0';
304
                        SStateWriteBase      <= send_addr;
305
 
306
 
307
                    else
308
                        SStateWriteBase      <= start_condition;
309
                    end if;
310
-------------------------------------------------------------------------------------------------------------------------------------------
311
--  "send_addr" durumu; SIOD referansinin yukselen kenari ve SIOC referansinin lojik-0 oldugu anda address verisinin geri kalanini
312
--  SIOD hattina yazar. Ardindan "Don't Care" bit durumuna gecer ve gecerken SIOD hattini lojik-0 tutar. 
313
-------------------------------------------------------------------------------------------------------------------------------------------                    
314
                when send_addr =>
315
                    if SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' then
316
                        if VCounter <= 5 then
317
                            VCounter    := VCounter + 1;
318
                            if(SAddr(6) = '1') then
319
                                SSIODWrite   <= '1';
320
                                SAddr       <= std_logic_vector(shift_left(unsigned(SAddr), 1));
321
                            elsif (SAddr(6) = '0') then
322
                                SSIODWrite   <= '0';
323
                                SAddr       <= std_logic_vector(shift_left(unsigned(SAddr), 1));
324
                            end if;
325
                        else
326
                            VCounter    := 0;
327
                            SSIODWrite   <= '0'; ---->>>> Don't Care Bit!
328
                            SStateWriteBase      <= addr_dc;
329
                            SBusy       <= '0';
330
                        end if;
331
                    else
332
                        SStateWriteBase      <= send_addr;
333
                    end if;
334
 
335
                when addr_dc =>
336
                    if SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' then
337
                        SAddr   <=  (others => '0');
338
                    elsif SDataClockRef = '0' and SDataClockRefPrev = '1' and SSIOCClock = '0' then
339
                        SStateWriteBase      <= send_reg;
340
                    end if;
341
-------------------------------------------------------------------------------------------------------------------------------------------
342
--  "send_reg" durumu; SIOD referansinin yukselen kenari ve SIOC referansinin lojik-0 oldugu anda register verisini SIOD hattina yazar.
343
--  Ardindan "Don't Care" bit durumuna gecer ve gecerken SIOD hattini lojik-0 tutar. 
344
-------------------------------------------------------------------------------------------------------------------------------------------   
345
                when send_reg =>
346
                    if SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' then
347
                        SBusy <= '1';
348
                        if SBusy = '1' then
349
                            if VCounter <= 7 then
350
                                VCounter    := VCounter + 1;
351
                                if(SReg(7) = '1') then
352
                                    SSIODWrite   <= '1';
353
                                    SReg        <= std_logic_vector(shift_left(unsigned(SReg), 1));
354
                                elsif (SReg(7) = '0') then
355
                                    SSIODWrite   <= '0';
356
                                    SReg        <= std_logic_vector(shift_left(unsigned(SReg), 1));
357
                                end if;
358
                            else
359
                                SBusy <= '0';
360
                                VCounter    := 0;
361
                                SSIODWrite   <= '0'; ---->>>> Don't Care Bit!
362
                                SStateWriteBase      <= reg_dc;
363
                            end if;
364
                        end if;
365
                    end if;
366
-------------------------------------------------------------------------------------------------------------------------------------------
367
--  "reg_dc" durumu; "Don't Care" biti yazildiktan sonra diger durumlarda oldugu gibi SIOD ve SIOC referans saat sinyallerine
368
--  gore islem yapar. Bu sefer data verisinin ilk bitini sola kaydirarak SIOD hattina yazar ve "send_data" durumuna gecer.
369
-------------------------------------------------------------------------------------------------------------------------------------------   
370
                when reg_dc =>
371
                    if SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' then
372
                        SReg   <=  (others => '0');
373
                        SStateWriteBase      <= send_data;
374
                        if(SData(7) = '1') then
375
                            SSIODWrite   <= '1';
376
                            SData       <= std_logic_vector(shift_left(unsigned(SData), 1));
377
                            SBusy <= '0';
378
                        elsif (SData(7) = '0') then
379
                            SSIODWrite   <= '0';
380
                            SData       <= std_logic_vector(shift_left(unsigned(SData), 1));
381
                            SBusy <= '0';
382
                        end if;
383
                    end if;
384
-------------------------------------------------------------------------------------------------------------------------------------------
385
--  "reg_dc" durumu; gonderilmek istenen verinin ilk biti yazdirildiktan sonra geri kalan bitler sola kaydirilarak SIOD hattina
386
--  yazilir. Ardindan "Don't Care" biti yazilir, 1 SIOD ve SIOC referans saati beklenir ve "data_dc" durumuna gecilir. 
387
-------------------------------------------------------------------------------------------------------------------------------------------   
388
                when send_data =>
389
                    if SDataClockRef = '1' and SDataClockRefPrev = '0' and SSIOCClock = '0' then
390
                        if VCounter     <= 6 then
391
                            VCounter    := VCounter + 1;
392
                            if(SData(7) = '1') then
393
                                SSIODWrite   <= '1';
394
                                SData       <= std_logic_vector(shift_left(unsigned(SData), 1));
395
                            elsif (SData(7) = '0') then
396
                                SSIODWrite   <= '0';
397
                                SData       <= std_logic_vector(shift_left(unsigned(SData), 1));
398
                            end if;
399
                        else
400
 
401
                            SSIODWrite   <= '0'; ----
402
                            SBusy <= '1';
403
                            if SBusy = '1' then
404
                                VCounter    := 0;
405
                                SStateWriteBase      <= data_dc;
406
                                SBusy <= '0';
407
                            end if;
408
 
409
                        end if;
410
                    end if;
411
------------------------------------------------------------------------------------------
412
--  "data_dc" durumu; sadece 1 clock SIOC referans bekleyerek "stop" durumuna gecer.
413
------------------------------------------------------------------------------------------
414
                when data_dc =>
415
                    if SSIOCClock = '1' and SSIOCClockPrev = '0' then
416
                        SData      <= (others => '0');
417
                        SStateWriteBase <= stop;
418
                    end if;
419
-------------------------------------------------------------------------------------------------------------------------------------------
420
--  "stop" durumu; ilk olarak SCCB haberlesmesini sonlandirmak icin ilk olarak SIOC hattini lojik-1 yapar, ardindan 1 SIOC saat
421
--  referansi bekledikten sonra SIOD hattini lojik-1 yapar ve "idle" durumuna gecis yapar.
422
-------------------------------------------------------------------------------------------------------------------------------------------   
423
                when stop =>
424
                    SSIOCWrite   <= '1';
425
                    if SSIOCClock = '1' and SSIOCClockPrev = '0' then
426
                          SSIODWrite   <= '1';
427
                        SBusy       <= '1';
428
                        SAddr       <= (others => '0');
429
                        SReg        <= (others => '0');
430
                        SData       <= (others => '0');
431
                        if SBusy = '1' then
432
                            --SReady      <= '1';
433
                            SStateWriteBase      <= idle;
434
                            SDone       <= '1';
435
 
436
                            SBusy       <= '0';
437
                        end if;
438
                    elsif SSIOCClock = '0' and SSIOCClockPrev = '1' then
439
                        SSIODWrite   <= '1';
440
                    end if;
441
 
442
                when others =>
443
            end case;
444
        end if;
445
    end process;
446
 
447
end Behavioral;

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