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[/] [p9813_rgb_led_string_driver/] [trunk/] [rtl/] [VHDL/] [testbench/] [testbench.vhd] - Blame information for rev 2

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1 2 jclaytons
--
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-- Test Bench
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.function_pack.all;
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use work.pull_pack_sim.all;
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use work.sim_control_port_pack.all;
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entity testbench is
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--
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--the testbench is a closed entity
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--
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end testbench;
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architecture struct of testbench is
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  ----------------------------------------------------------------------
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  -- NOTE: Some of these constants are duplicated inside the modules under test.
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  --       Synthesizable code should not contain simulation constants.
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  ----------------------------------------------------------------------
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  -- System Constants and Settings
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  constant TEST_CLKRATE    : integer := 124990000; -- The clock rate at which the stimulus logic runs
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  constant DUT_REF_CLKRATE : integer :=  50000000; -- The clock rate at which the test device runs
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  constant TEST_BAUDRATE   : integer :=    921600; -- Serial Link Baud rate
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  constant TEST_PARITY     : integer :=         0; -- 0=none, 1=even, 2=odd
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  constant CMD_LINE_SIZE   : integer :=        80; -- Length of buffer to hold file input bytes
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  constant PPSGEN_PERIOD   : time    := 1001000 * 1 us;
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  ----------------------------------------------------------------------
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  -- Component Declarations
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  -----------------------------------
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  component fpga
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  port (
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    -- System Clock & Reset_n
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    sys_clk_ref  : in   std_logic;
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    sys_rst_n_i  : in   std_logic;
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    -- Standardized Board Inputs / Outputs
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    switch       : in  unsigned(7 downto 0);
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    led          : out unsigned(7 downto 0);
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    exp_io       : inout unsigned(39 downto 1);
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    -- TTL serial interface
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    uart_0_tx_o  : out std_logic;
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    uart_0_rx_i  : in  std_logic
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  );
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  end component;
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  -----------------------------------------------------------------------------
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  -- Internal signal declarations
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    -- Common Signals
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  signal sys_rst       : std_logic;
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  signal sys_rst_n     : std_logic;
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  signal sys_clk       : std_logic;
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  signal dut_ref_clk   : std_logic := '0';
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    -- Signals for uart_control_port
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  signal uart_cmd      : std_logic;
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  signal uart_resp     : std_logic;
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    -- Signals from unit under test, so they show up in testbench
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    -- Board Inputs / Outputs
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  signal switch        : unsigned(7 downto 0);
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  signal led           : unsigned(7 downto 0);
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  signal exp_io        : unsigned(39 downto 1);
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begin
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  ------------------------------------------------------------------------
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  -- Set up low asserted reset
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  sys_rst_n <= not sys_rst;
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  ------------------------------------------------------------------------
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  -- Set up independent DUT reference clock
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  dut_ref_clk_proc : process
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    variable PS_PER_SECOND : real := 1.0E+12;
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    variable half_period : time := integer(PS_PER_SECOND/(2.0*real(DUT_REF_CLKRATE))) * 1 ps;
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  begin
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     --wait for 1/2 of the clock period;
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     wait for half_period;
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     dut_ref_clk <= not dut_ref_clk;
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  end process;
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  ------------------------------------------------------------------------
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  -- Instantiate a UART Control Port
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  ucp0 : sim_uart_control_port
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  generic map(
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    INPUT_FILE     => ".\rs232_test_in.txt",
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    OUTPUT_FILE    => ".\rs232_test_out.txt",
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    POR_DURATION   =>        500 ns,  -- Duration of internal reset signal activity
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    POR_ASSERT_LOW =>         false,  -- Determine polarity of reset signal
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    CLKRATE        =>  TEST_CLKRATE,  -- Control Port clock rate default.
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    UART_BAUDRATE  => TEST_BAUDRATE,  -- UART Speed, in bits per second.
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    UART_PARITY    =>   TEST_PARITY,
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    LINE_LENGTH    => CMD_LINE_SIZE   -- Length of buffer to hold file input bytes
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  )
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  port map (
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    test_rst => sys_rst,
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    test_clk => sys_clk,
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    uart_tx  => uart_cmd,
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    uart_rx  => uart_resp
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  );
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  ------------------------------------------------------------------------
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  -- Instantiate Unit Under Test
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  dut_0 : fpga
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  port map(
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    -- System Clock & Reset_n
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    sys_clk_ref  => dut_ref_clk,
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    sys_rst_n_i  => sys_rst_n,
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    -- Standardized Board Inputs / Outputs
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    switch       => switch,
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    led          => led,
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    exp_io       => exp_io,
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    -- TTL serial interface
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    uart_0_tx_o  => uart_resp,
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    uart_0_rx_i  => uart_cmd
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  );
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-- Assign pins
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  -- Feed the randomized PN sequence data into the unit under test.
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  exp_io(32) <= exp_io(1);
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-- Apply a value to the inputs
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switch <= "11111101"; -- low is 'on'
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-- Create pullups as needed
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  exp_io_loop: for i in exp_io'length downto 1 generate
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    i_pu : pullup1
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      port map (
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          pin => exp_io(i)
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      );
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  end generate exp_io_loop;
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  pu1: pullup1 PORT MAP (pin => uart_cmd);
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  pu2: pullup1 PORT MAP (pin => uart_resp);
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--    eight_loop: for i in 7 downto 0 GENERATE
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--      i_pu8 : pullup1
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--        PORT MAP (
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--            pin => PC(i)            --Pullups on the Mod IRQ lines
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--          );
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--    END GENERATE eight_loop;
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end struct;

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