URL https://opencores.org/ocsvn/p9813_rgb_led_string_driver/p9813_rgb_led_string_driver/trunk

Subversion Repositories p9813_rgb_led_string_driver

[/] [p9813_rgb_led_string_driver/] [trunk/] [rtl/] [VHDL/] [ucrc_pack.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------
-- Package
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package ucrc_pack is
 
-- Component declarations not provided any more.
-- With VHDL '93 and newer, component declarations are allowed,
-- but not required.
--
-- If you please, try direct instantiation instead, for example:
--
--   instance_name : entity work.entity_name(beh)
--
 
end ucrc_pack;
 
-------------------------------------------------------------------------------
-- Serial CRC module
-------------------------------------------------------------------------------
--
-- Author: John Clayton
-- Date  : Jan.  8, 2014 Wrote description and began coding.
--                       Added separate asynchronous and synchronous
--                       reset inputs.  Changed signal names to resemble
--                       other packages within the project, and modified
--                       format to match my own personal coding style.
--
-- Description
-------------------------------------------------------------------------------
-- This is a CRC calculator.
-- It was obtained from http://www.opencores.org.
----------------------------------------------------------------------
----                                                              ----
---- Ultimate CRC.                                                ----
----                                                              ----
---- This file is part of the ultimate CRC project                ----
---- http://www.opencores.org/cores/ultimate_crc/                 ----
----                                                              ----
---- Description                                                  ----
---- CRC generator/checker, serial implementation.                ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: ucrc_pack.vhd,v $
-- Revision 1.6  2018-02-05 16:51:45-07  barlettp
-- ASPI
--
-- Revision 1.5  2017-03-06 11:50:55-07  barlettp
-- Actuator Systems Power Interface FPGA
--
-- Revision 1.1  2014-08-19 09:03:30-07  claytonj
-- Initial revision
--
-- Revision 1.2  2005/05/09 19:26:58  gedra
-- Moved match signal into clock enable
--
-- Revision 1.1  2005/05/07 12:47:47  gedra
-- Serial implementation.
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ucrc_ser is
  generic (
    POLYNOMIAL : unsigned := "0001000000100001"; -- 4 to 32 bits
    INIT_VALUE : unsigned := "1111111111111111"
  );
  port (
    -- System clock and asynchronous reset
    sys_clk    : in  std_logic; -- clock
    sys_rst_n  : in  std_logic; -- asynchronous reset
    sys_clk_en : in  std_logic; -- clock enable
 
    -- Input and Control
    clear_i : in  std_logic;    -- synchronous reset
    data_i  : in  std_logic;    -- data input
    flush_i : in  std_logic;    -- flush crc
 
    -- Output
    match_o : out std_logic;    -- CRC match flag
    crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
  );
end ucrc_ser;
 
architecture beh of ucrc_ser is
 
  constant msb         : integer                        := POLYNOMIAL'length - 1;
  constant init_msb    : integer                        := INIT_VALUE'length - 1;
  constant p           : unsigned(msb downto 0) := POLYNOMIAL;
 
  signal din, crc_msb  : unsigned(msb downto 1);
  signal crc, zero, fb : unsigned(msb downto 0);
 
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
  PCHK : if msb /= init_msb generate
    process
    begin
      report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
        severity failure;
      wait;
    end process;
  end generate PCHK;
 
  PCHK2 : if (msb < 3) or (msb > 31) generate
    process
    begin
      report "POLYNOMIAL must be of order 4 to 32!"
        severity failure;
      wait;
    end process;
  end generate PCHK2;
 
  PCHK3 : if p(0) /= '1' generate      -- LSB must be 1
    process
    begin
      report "POLYNOMIAL must have lsb set to 1!"
        severity failure;
      wait;
    end process;
  end generate PCHK3;
 
   zero  <= (others => '0');
   crc_o <= crc;
 
-- Create vectors of data input and MSB of CRC
   DI : for i in 1 to msb generate
     din(i)     <= data_i;
     crc_msb(i) <= crc(msb);
   end generate DI;
 
-- Feedback signals
   fb(0)            <= data_i xor crc(msb);
   fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));
 
-- CRC process
  CRCP : process (sys_clk, sys_rst_n)
  begin
    if sys_rst_n='0' then -- async. reset
      crc     <= INIT_VALUE;
      match_o <= '0';
    elsif rising_edge(sys_clk) then
      if clear_i='1' then -- sync. reset
        crc     <= INIT_VALUE;
        match_o <= '0';
      else
        if sys_clk_en = '1' then
          -- CRC generation
          if flush_i = '1' then
            crc(0)            <= '0';
            crc(msb downto 1) <= crc(msb - 1 downto 0);
          else
            crc <= fb;
          end if;
          -- CRC match checker (if data plus CRC is clocked in without errors,
          -- the CRC register ends up with all zeroes)
          if fb = zero then
            match_o <= '1';
          else
            match_o <= '0';
          end if;
        end if;
      end if;
    end if;
  end process;
 
end beh;
 
-------------------------------------------------------------------------------
-- Parallel CRC module
-------------------------------------------------------------------------------
--
-- Author: John Clayton
-- Date  : Jan.  8, 2014 Wrote description and began coding.
--                       Added separate asynchronous and synchronous
--                       reset inputs.  Changed signal names to resemble
--                       other packages within the project, and modified
--                       format to match my own personal coding style.
--
-- Description
-------------------------------------------------------------------------------
-- This is a CRC calculator.
-- It was obtained from http://www.opencores.org.
----------------------------------------------------------------------
----                                                              ----
---- Ultimate CRC.                                                ----
----                                                              ----
---- This file is part of the ultimate CRC projectt               ----
---- http://www.opencores.org/cores/ultimate_crc/                 ----
----                                                              ----
---- Description                                                  ----
---- CRC generator/checker, parallel implementation.              ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2005 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: ucrc_pack.vhd,v $
-- Revision 1.6  2018-02-05 16:51:45-07  barlettp
-- ASPI
--
-- Revision 1.5  2017-03-06 11:50:55-07  barlettp
-- Actuator Systems Power Interface FPGA
--
-- Revision 1.1  2014-08-19 09:03:30-07  claytonj
-- Initial revision
--
-- Revision 1.1  2005/05/09 15:58:38  gedra
-- Parallel implementation
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity ucrc_par is
  generic (
    POLYNOMIAL : unsigned := "0001000000100001";
    INIT_VALUE : unsigned := "1111111111111111";
    DATA_WIDTH : integer range 2 to 256 := 8
  );
  port (
    -- System clock and asynchronous reset
    sys_clk    : in  std_logic;       -- clock
    sys_rst_n  : in  std_logic;       -- asynchronous reset
    sys_clk_en : in  std_logic;       -- clock enable
 
    -- Input and Control
    clear_i : in  std_logic; -- synchronous reset
    data_i  : in  unsigned(DATA_WIDTH - 1 downto 0);  -- data input
 
    -- Output
    match_o : out std_logic;       -- CRC match flag
    crc_o   : out unsigned(POLYNOMIAL'length - 1 downto 0)  -- CRC output
  );
end ucrc_par;
 
architecture beh of ucrc_par is
 
  constant msb      : integer                := POLYNOMIAL'length - 1;
  constant init_msb : integer                := INIT_VALUE'length - 1;
  constant p        : unsigned(msb downto 0) := POLYNOMIAL;
  constant dw       : integer                := DATA_WIDTH;
  constant pw       : integer                := POLYNOMIAL'length;
  type fb_array is array (dw downto 1) of unsigned(msb downto 0);
  type dmsb_array is array (dw downto 1) of unsigned(msb downto 1);
  signal crca       : fb_array;
  signal da, ma     : dmsb_array;
  signal crc, zero  : unsigned(msb downto 0);
 
begin
 
-- Parameter checking: Invalid generics will abort simulation/synthesis
  PCHK1 : if msb /= init_msb generate
    process
    begin
      report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
        severity failure;
      wait;
    end process;
  end generate PCHK1;
 
  PCHK2 : if (msb < 3) or (msb > 31) generate
    process
    begin
      report "POLYNOMIAL must be of order 4 to 32!"
        severity failure;
      wait;
    end process;
  end generate PCHK2;
 
  PCHK3 : if p(0) /= '1' generate      -- LSB must be 1
    process
    begin
      report "POLYNOMIAL must have lsb set to 1!"
        severity failure;
      wait;
    end process;
  end generate PCHK3;
 
-- Generate vector of each data bit
  CA : for i in 1 to dw generate       -- data bits
    DAT : for j in 1 to msb generate
      da(i)(j) <= data_i(i - 1);
    end generate DAT;
  end generate CA;
 
-- Generate vector of each CRC MSB
   MS0 : for i in 1 to msb generate
     ma(1)(i) <= crc(msb);
   end generate MS0;
   MSP : for i in 2 to dw generate
     MSU : for j in 1 to msb generate
       ma(i)(j) <= crca(i - 1)(msb);
     end generate MSU;
   end generate MSP;
 
-- Generate feedback matrix
   crca(1)(0)            <= da(1)(1) xor crc(msb);
   crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
   FB : for i in 2 to dw generate
     crca(i)(0)            <= da(i)(1) xor crca(i - 1)(msb);
     crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
                              ((da(i) xor ma(i)) and p(msb downto 1));
   end generate FB;
 
-- CRC process
  crc_o <= crc;
  zero  <= (others => '0');
 
  CRCP : process (sys_clk, sys_rst_n)
  begin
    if sys_rst_n='0' then -- async. reset
      crc     <= INIT_VALUE;
      match_o <= '0';
    elsif rising_edge(sys_clk) then
      if clear_i='1' then -- sync. reset
        crc     <= INIT_VALUE;
        match_o <= '0';
      elsif sys_clk_en = '1' then
        crc <= crca(dw);
        if crca(dw) = zero then
          match_o <= '1';
        else
          match_o <= '0';
        end if;
      end if;
    end if;
  end process;
 
end beh;
 
 

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Subversion Repositories p9813_rgb_led_string_driver

[/] [p9813_rgb_led_string_driver/] [trunk/] [rtl/] [VHDL/] [ucrc_pack.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jclaytons	`--------------------------------------------------------------------------`
2			`-- Package`
3			`--`
4
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.numeric_std.all;`
8
9			`package ucrc_pack is`
10
11			`-- Component declarations not provided any more.`
12			`-- With VHDL '93 and newer, component declarations are allowed,`
13			`-- but not required.`
14			`--`
15			`-- If you please, try direct instantiation instead, for example:`
16			`--`
17			`-- instance_name : entity work.entity_name(beh)`
18			`--`
19
20			`end ucrc_pack;`
21
22			`-------------------------------------------------------------------------------`
23			`-- Serial CRC module`
24			`-------------------------------------------------------------------------------`
25			`--`
26			`-- Author: John Clayton`
27			`-- Date : Jan. 8, 2014 Wrote description and began coding.`
28			`-- Added separate asynchronous and synchronous`
29			`-- reset inputs. Changed signal names to resemble`
30			`-- other packages within the project, and modified`
31			`-- format to match my own personal coding style.`
32			`--`
33			`-- Description`
34			`-------------------------------------------------------------------------------`
35			`-- This is a CRC calculator.`
36			`-- It was obtained from http://www.opencores.org.`
37			`----------------------------------------------------------------------`
38			`---- ----`
39			`---- Ultimate CRC. ----`
40			`---- ----`
41			`---- This file is part of the ultimate CRC project ----`
42			`---- http://www.opencores.org/cores/ultimate_crc/ ----`
43			`---- ----`
44			`---- Description ----`
45			`---- CRC generator/checker, serial implementation. ----`
46			`---- ----`
47			`---- ----`
48			`---- To Do: ----`
49			`---- - ----`
50			`---- ----`
51			`---- Author(s): ----`
52			`---- - Geir Drange, gedra@opencores.org ----`
53			`---- ----`
54			`----------------------------------------------------------------------`
55			`---- ----`
56			`---- Copyright (C) 2005 Authors and OPENCORES.ORG ----`
57			`---- ----`
58			`---- This source file may be used and distributed without ----`
59			`---- restriction provided that this copyright statement is not ----`
60			`---- removed from the file and that any derivative work contains ----`
61			`---- the original copyright notice and the associated disclaimer. ----`
62			`---- ----`
63			`---- This source file is free software; you can redistribute it ----`
64			`---- and/or modify it under the terms of the GNU General ----`
65			`---- Public License as published by the Free Software Foundation; ----`
66			`---- either version 2.0 of the License, or (at your option) any ----`
67			`---- later version. ----`
68			`---- ----`
69			`---- This source is distributed in the hope that it will be ----`
70			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
71			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
72			`---- PURPOSE. See the GNU General Public License for more details.----`
73			`---- ----`
74			`---- You should have received a copy of the GNU General ----`
75			`---- Public License along with this source; if not, download it ----`
76			`---- from http://www.gnu.org/licenses/gpl.txt ----`
77			`---- ----`
78			`----------------------------------------------------------------------`
79			`--`
80			`-- CVS Revision History`
81			`--`
82			`-- $Log: ucrc_pack.vhd,v $`
83			`-- Revision 1.6 2018-02-05 16:51:45-07 barlettp`
84			`-- ASPI`
85			`--`
86			`-- Revision 1.5 2017-03-06 11:50:55-07 barlettp`
87			`-- Actuator Systems Power Interface FPGA`
88			`--`
89			`-- Revision 1.1 2014-08-19 09:03:30-07 claytonj`
90			`-- Initial revision`
91			`--`
92			`-- Revision 1.2 2005/05/09 19:26:58 gedra`
93			`-- Moved match signal into clock enable`
94			`--`
95			`-- Revision 1.1 2005/05/07 12:47:47 gedra`
96			`-- Serial implementation.`
97			`--`
98			`--`
99			`--`
100
101			`library ieee;`
102			`use ieee.std_logic_1164.all;`
103			`use ieee.numeric_std.all;`
104
105			`entity ucrc_ser is`
106			`generic (`
107			`POLYNOMIAL : unsigned := "0001000000100001"; -- 4 to 32 bits`
108			`INIT_VALUE : unsigned := "1111111111111111"`
109			`);`
110			`port (`
111			`-- System clock and asynchronous reset`
112			`sys_clk : in std_logic; -- clock`
113			`sys_rst_n : in std_logic; -- asynchronous reset`
114			`sys_clk_en : in std_logic; -- clock enable`
115
116			`-- Input and Control`
117			`clear_i : in std_logic; -- synchronous reset`
118			`data_i : in std_logic; -- data input`
119			`flush_i : in std_logic; -- flush crc`
120
121			`-- Output`
122			`match_o : out std_logic; -- CRC match flag`
123			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
124			`);`
125			`end ucrc_ser;`
126
127			`architecture beh of ucrc_ser is`
128
129			`constant msb : integer := POLYNOMIAL'length - 1;`
130			`constant init_msb : integer := INIT_VALUE'length - 1;`
131			`constant p : unsigned(msb downto 0) := POLYNOMIAL;`
132
133			`signal din, crc_msb : unsigned(msb downto 1);`
134			`signal crc, zero, fb : unsigned(msb downto 0);`
135
136			`begin`
137
138			`-- Parameter checking: Invalid generics will abort simulation/synthesis`
139			`PCHK : if msb /= init_msb generate`
140			`process`
141			`begin`
142			`report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"`
143			`severity failure;`
144			`wait;`
145			`end process;`
146			`end generate PCHK;`
147
148			`PCHK2 : if (msb < 3) or (msb > 31) generate`
149			`process`
150			`begin`
151			`report "POLYNOMIAL must be of order 4 to 32!"`
152			`severity failure;`
153			`wait;`
154			`end process;`
155			`end generate PCHK2;`
156
157			`PCHK3 : if p(0) /= '1' generate -- LSB must be 1`
158			`process`
159			`begin`
160			`report "POLYNOMIAL must have lsb set to 1!"`
161			`severity failure;`
162			`wait;`
163			`end process;`
164			`end generate PCHK3;`
165
166			`zero <= (others => '0');`
167			`crc_o <= crc;`
168
169			`-- Create vectors of data input and MSB of CRC`
170			`DI : for i in 1 to msb generate`
171			`din(i) <= data_i;`
172			`crc_msb(i) <= crc(msb);`
173			`end generate DI;`
174
175			`-- Feedback signals`
176			`fb(0) <= data_i xor crc(msb);`
177			`fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1));`
178
179			`-- CRC process`
180			`CRCP : process (sys_clk, sys_rst_n)`
181			`begin`
182			`if sys_rst_n='0' then -- async. reset`
183			`crc <= INIT_VALUE;`
184			`match_o <= '0';`
185			`elsif rising_edge(sys_clk) then`
186			`if clear_i='1' then -- sync. reset`
187			`crc <= INIT_VALUE;`
188			`match_o <= '0';`
189			`else`
190			`if sys_clk_en = '1' then`
191			`-- CRC generation`
192			`if flush_i = '1' then`
193			`crc(0) <= '0';`
194			`crc(msb downto 1) <= crc(msb - 1 downto 0);`
195			`else`
196			`crc <= fb;`
197			`end if;`
198			`-- CRC match checker (if data plus CRC is clocked in without errors,`
199			`-- the CRC register ends up with all zeroes)`
200			`if fb = zero then`
201			`match_o <= '1';`
202			`else`
203			`match_o <= '0';`
204			`end if;`
205			`end if;`
206			`end if;`
207			`end if;`
208			`end process;`
209
210			`end beh;`
211
212			`-------------------------------------------------------------------------------`
213			`-- Parallel CRC module`
214			`-------------------------------------------------------------------------------`
215			`--`
216			`-- Author: John Clayton`
217			`-- Date : Jan. 8, 2014 Wrote description and began coding.`
218			`-- Added separate asynchronous and synchronous`
219			`-- reset inputs. Changed signal names to resemble`
220			`-- other packages within the project, and modified`
221			`-- format to match my own personal coding style.`
222			`--`
223			`-- Description`
224			`-------------------------------------------------------------------------------`
225			`-- This is a CRC calculator.`
226			`-- It was obtained from http://www.opencores.org.`
227			`----------------------------------------------------------------------`
228			`---- ----`
229			`---- Ultimate CRC. ----`
230			`---- ----`
231			`---- This file is part of the ultimate CRC projectt ----`
232			`---- http://www.opencores.org/cores/ultimate_crc/ ----`
233			`---- ----`
234			`---- Description ----`
235			`---- CRC generator/checker, parallel implementation. ----`
236			`---- ----`
237			`---- ----`
238			`---- To Do: ----`
239			`---- - ----`
240			`---- ----`
241			`---- Author(s): ----`
242			`---- - Geir Drange, gedra@opencores.org ----`
243			`---- ----`
244			`----------------------------------------------------------------------`
245			`---- ----`
246			`---- Copyright (C) 2005 Authors and OPENCORES.ORG ----`
247			`---- ----`
248			`---- This source file may be used and distributed without ----`
249			`---- restriction provided that this copyright statement is not ----`
250			`---- removed from the file and that any derivative work contains ----`
251			`---- the original copyright notice and the associated disclaimer. ----`
252			`---- ----`
253			`---- This source file is free software; you can redistribute it ----`
254			`---- and/or modify it under the terms of the GNU General ----`
255			`---- Public License as published by the Free Software Foundation; ----`
256			`---- either version 2.0 of the License, or (at your option) any ----`
257			`---- later version. ----`
258			`---- ----`
259			`---- This source is distributed in the hope that it will be ----`
260			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
261			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
262			`---- PURPOSE. See the GNU General Public License for more details.----`
263			`---- ----`
264			`---- You should have received a copy of the GNU General ----`
265			`---- Public License along with this source; if not, download it ----`
266			`---- from http://www.gnu.org/licenses/gpl.txt ----`
267			`---- ----`
268			`----------------------------------------------------------------------`
269			`--`
270			`-- CVS Revision History`
271			`--`
272			`-- $Log: ucrc_pack.vhd,v $`
273			`-- Revision 1.6 2018-02-05 16:51:45-07 barlettp`
274			`-- ASPI`
275			`--`
276			`-- Revision 1.5 2017-03-06 11:50:55-07 barlettp`
277			`-- Actuator Systems Power Interface FPGA`
278			`--`
279			`-- Revision 1.1 2014-08-19 09:03:30-07 claytonj`
280			`-- Initial revision`
281			`--`
282			`-- Revision 1.1 2005/05/09 15:58:38 gedra`
283			`-- Parallel implementation`
284			`--`
285			`--`
286			`--`
287
288			`library ieee;`
289			`use ieee.std_logic_1164.all;`
290			`use ieee.numeric_std.all;`
291
292			`entity ucrc_par is`
293			`generic (`
294			`POLYNOMIAL : unsigned := "0001000000100001";`
295			`INIT_VALUE : unsigned := "1111111111111111";`
296			`DATA_WIDTH : integer range 2 to 256 := 8`
297			`);`
298			`port (`
299			`-- System clock and asynchronous reset`
300			`sys_clk : in std_logic; -- clock`
301			`sys_rst_n : in std_logic; -- asynchronous reset`
302			`sys_clk_en : in std_logic; -- clock enable`
303
304			`-- Input and Control`
305			`clear_i : in std_logic; -- synchronous reset`
306			`data_i : in unsigned(DATA_WIDTH - 1 downto 0); -- data input`
307
308			`-- Output`
309			`match_o : out std_logic; -- CRC match flag`
310			`crc_o : out unsigned(POLYNOMIAL'length - 1 downto 0) -- CRC output`
311			`);`
312			`end ucrc_par;`
313
314			`architecture beh of ucrc_par is`
315
316			`constant msb : integer := POLYNOMIAL'length - 1;`
317			`constant init_msb : integer := INIT_VALUE'length - 1;`
318			`constant p : unsigned(msb downto 0) := POLYNOMIAL;`
319			`constant dw : integer := DATA_WIDTH;`
320			`constant pw : integer := POLYNOMIAL'length;`
321			`type fb_array is array (dw downto 1) of unsigned(msb downto 0);`
322			`type dmsb_array is array (dw downto 1) of unsigned(msb downto 1);`
323			`signal crca : fb_array;`
324			`signal da, ma : dmsb_array;`
325			`signal crc, zero : unsigned(msb downto 0);`
326
327			`begin`
328
329			`-- Parameter checking: Invalid generics will abort simulation/synthesis`
330			`PCHK1 : if msb /= init_msb generate`
331			`process`
332			`begin`
333			`report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"`
334			`severity failure;`
335			`wait;`
336			`end process;`
337			`end generate PCHK1;`
338
339			`PCHK2 : if (msb < 3) or (msb > 31) generate`
340			`process`
341			`begin`
342			`report "POLYNOMIAL must be of order 4 to 32!"`
343			`severity failure;`
344			`wait;`
345			`end process;`
346			`end generate PCHK2;`
347
348			`PCHK3 : if p(0) /= '1' generate -- LSB must be 1`
349			`process`
350			`begin`
351			`report "POLYNOMIAL must have lsb set to 1!"`
352			`severity failure;`
353			`wait;`
354			`end process;`
355			`end generate PCHK3;`
356
357			`-- Generate vector of each data bit`
358			`CA : for i in 1 to dw generate -- data bits`
359			`DAT : for j in 1 to msb generate`
360			`da(i)(j) <= data_i(i - 1);`
361			`end generate DAT;`
362			`end generate CA;`
363
364			`-- Generate vector of each CRC MSB`
365			`MS0 : for i in 1 to msb generate`
366			`ma(1)(i) <= crc(msb);`
367			`end generate MS0;`
368			`MSP : for i in 2 to dw generate`
369			`MSU : for j in 1 to msb generate`
370			`ma(i)(j) <= crca(i - 1)(msb);`
371			`end generate MSU;`
372			`end generate MSP;`
373
374			`-- Generate feedback matrix`
375			`crca(1)(0) <= da(1)(1) xor crc(msb);`
376			`crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));`
377			`FB : for i in 2 to dw generate`
378			`crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);`
379			`crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor`
380			`((da(i) xor ma(i)) and p(msb downto 1));`
381			`end generate FB;`
382
383			`-- CRC process`
384			`crc_o <= crc;`
385			`zero <= (others => '0');`
386
387			`CRCP : process (sys_clk, sys_rst_n)`
388			`begin`
389			`if sys_rst_n='0' then -- async. reset`
390			`crc <= INIT_VALUE;`
391			`match_o <= '0';`
392			`elsif rising_edge(sys_clk) then`
393			`if clear_i='1' then -- sync. reset`
394			`crc <= INIT_VALUE;`
395			`match_o <= '0';`
396			`elsif sys_clk_en = '1' then`
397			`crc <= crca(dw);`
398			`if crca(dw) = zero then`
399			`match_o <= '1';`
400			`else`
401			`match_o <= '0';`
402			`end if;`
403			`end if;`
404			`end if;`
405			`end process;`
406
407			`end beh;`
408
409