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[/] [pdp8/] [trunk/] [de0_nano/] [oct_7seg.vhd] - Blame information for rev 5

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1 5 trurl
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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entity oct_7seg is
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        port (
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                CLOCK_50 : in std_logic;
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                oct_digit : in std_logic_vector(2 downto 0);
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                seg : buffer std_logic_vector(6 downto 0)
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        );
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end oct_7seg;
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architecture rtl of oct_7seg is
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begin
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  process(CLOCK_50)
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  begin
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-- seg = {g,f,e,d,c,b,a};
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-- 0 is on and 1 is off
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    case oct_digit is
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      when "000" => seg <= B"1000000";
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           when "001" => seg <= B"1111001";
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           when "010" => seg <= B"0100100";
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      when "011" => seg <= B"0110000";
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      when "100" => seg <= B"0011001";
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      when "101" => seg <= B"0010010";
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      when "110" => seg <= B"0000010";
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      when "111" => seg <= B"1111000";
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      when others => seg <= B"0000000";
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    end case;
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  end process;
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end rtl;

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