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[/] [pdp8/] [trunk/] [minimal/] [minimal_testbench.vhd] - Blame information for rev 2

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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--!      Minimal Test Bench
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--!
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--! \details
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--!      Test Bench.
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--!
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--! \file
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--!      minimal_testbench.vhd
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--!
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--! \author
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--!      Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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--  Copyright (C) 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee;                                                   --! IEEE Library
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use ieee.std_logic_1164.all;                                    --! IEEE 1164
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use ieee.std_logic_textio.all;                                  --! IEEE Std Logic TextIO
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use std.textio.all;                                             --! TEXTIO
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--
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--! MINIMAL Test Bench Entity
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--
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entity MINIMAL_TESTBENCH is
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end MINIMAL_TESTBENCH;
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--
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--! MINIMAL Test Bench Behav
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--
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architecture behav of MINIMAL_TESTBENCH is
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    --
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    -- PDP8 Pins
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    --
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    signal clk            : std_logic           := '0';
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    signal rst            : std_logic           := '0';
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    -- TTY1 Interfaces
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    signal tty1RXD        : std_logic           := '1';
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    signal tty1TXD        : std_logic;
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    -- SD Interface
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    signal sdCD           : std_logic           := '0';         --! SD Card Detect
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    signal sdWP           : std_logic           := '0';         --! SD Write Protect
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    signal sdMISO         : std_logic;                          --! SD Data In
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    signal sdMOSI         : std_logic;                          --! SD Data Out
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    signal sdSCLK         : std_logic;                          --! SD Clock
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    signal sdCS           : std_logic;                          --! SD Chip Select
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    --
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    -- UART
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    --
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    constant bitTIME      : time := 8680.5 ns;
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begin
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    eMINIMAL_PDP8 : entity work.eMINIMAL_PDP8 (rtl) port map (
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        -- System
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        clk     => clk,
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        rst     => rst,
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        -- TTY1 Interfaces
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        tty1RXD => tty1RXD,
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        tty1TXD => tty1TXD,
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        -- SD Interface
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        sdMISO  => sdMISO,
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        sdMOSI  => sdMOSI,
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        sdSCLK  => sdSCLK,
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        sdCS    => sdCS
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    );
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    --
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    -- SD Card Simulator
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    --
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    iSDSIM : entity work.eSDSIM (behav) port map (
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        clk    => clk,
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        rst    => rst,
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        sdCD   => sdCD,
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        sdWP   => sdWP,
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        sdMISO => sdMISO,
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        sdMOSI => sdMOSI,
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        sdSCLK => sdSCLK,
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        sdCS   => sdCS
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    );
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    --
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    -- UART Simulator
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    --
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    eUARTSIM : entity work.eUARTSIM  (behav) port map (
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        rst     => rst,
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        bitTIME => bitTIME,
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        TXD     => tty1RXD
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    );
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    --
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    -- Reset Signal
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    --
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    rst <= '1', '0' after 80 ns;
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    --
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    --! Clock Generator
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    --
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    CLKGEN : process
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    begin
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        wait for 10 ns;
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        clk <= not(clk);
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    end process CLKGEN;
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end behav;

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