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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Arithmetic Logic Unit (ALU) Register
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--!
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--! \details
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--! The ALU 'owns' the Link Register (L) and Accumulator
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--! Register (AC). This device performs every operation
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--! that manipules either the Link Register or Accumulator.
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--!
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--! This code operates on the Link Register and Accumulator
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--! as if it were a single 13-bit wide register. The Link
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--! Register is LAC(0) while the Accumlator is LAC(1 to 12).
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--!
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--! \todo
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--! Although the CPU is knitted together with a 'rats nest'
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--! of interconnections, this file is 'rattier' than most.
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--! It could stand a good cleanup. Any cleanup should also
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--! address EAE and how that fits with the ALU.
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--!
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--! \file
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--! alu.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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use work.cpu_types.all; --! Types
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--
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--! CPU Arithmetic Logic Unit (ALU) Register Entity
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--
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entity eALU is port (
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sys : in sys_t; --! Clock/Reset
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acOP : in acOP_t; --! AC Operation
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BTSTRP : in std_logic; --! Bootstrap Flag
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GTF : in std_logic; --! Greater Than Flag
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HLTTRP : in std_logic; --! Hlttrp Flag
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IE : in std_logic; --! Interrupt Enable Flip-Flop
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IRQ : in std_logic; --! Interrupt Request flag
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PNLTRP : in std_logic; --! Panel Trap Flag
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PWRTRP : in std_logic; --! Power-on Trap Flag
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DF : in field_t; --! DF Input
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EAE : in eae_t; --! EAE Input
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INF : in field_t; --! INF Input
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IR : in data_t; --! IR Input
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MA : in addr_t; --! MA Input
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MD : in data_t; --! MB Input
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MQ : in data_t; --! MQ Input
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PC : in addr_t; --! PC Input
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SC : in sc_t; --! SC Input
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SF : in sf_t; --! SF Input
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SP1 : in addr_t; --! SP1 Input
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SP2 : in addr_t; --! SP2 Input
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SR : in data_t; --! SR Input
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UF : in std_logic; --! UF Input
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LAC : out ldata_t --! ALU Output
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);
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end eALU;
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--
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--! CPU Arithmetic Logic Unit (ALU) Register RTL
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--
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architecture rtl of eALU is
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signal lacREG : ldata_t; --! Link and Accumulator Register
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signal lacMUX : ldata_t; --! Link and Accumulator Multiplexer
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--!
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--! ALU Operations
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--!
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signal opIAC : ldata_t; --! Increment accumulator
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signal opBSW : ldata_t; --! Byte swap
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signal opRAL : ldata_t; --!
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signal opRTL : ldata_t; --!
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signal opR3L : ldata_t; --!
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signal opRAR : ldata_t; --!
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signal opRTR : ldata_t; --!
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signal opSHL0 : ldata_t; --!
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signal opSHL1 : ldata_t; --!
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signal opLSR : ldata_t; --!
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signal opASR : ldata_t; --!
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signal opUNDEF1 : ldata_t; --! Undefined Operation #1
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signal opUNDEF2 : ldata_t; --! Undefined Operation #2
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signal opPC : ldata_t; --! Undefined Operation #1,2
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signal opCML : ldata_t; --!
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signal opCMA : ldata_t; --!
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signal opCMACML : ldata_t; --!
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signal opCLL : ldata_t; --!
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signal opCLLCML : ldata_t; --!
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signal opCLLCMA : ldata_t; --!
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signal opCLLCMACML : ldata_t; --!
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signal opCLA : ldata_t; --!
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signal opCLACML : ldata_t; --!
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signal opCLACMA : ldata_t; --!
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signal opCLACMACML : ldata_t; --!
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signal opCLACLL : ldata_t; --!
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signal opCLACLLCML : ldata_t; --!
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signal opCLACLLCMA : ldata_t; --!
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signal opCLACLLCMACML : ldata_t; --!
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--!
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--! KM8E
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--!
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signal opRDF0 : ldata_t; --! RDF0 (HD6120)
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signal opRIF0 : ldata_t; --! RIF0 (HD6120)
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signal opRIB0 : ldata_t; --! RIB0 (HD6120)
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signal opRDF1 : ldata_t; --! RDF1 (PDP8)
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signal opRIF1 : ldata_t; --! RIF1 (PDP8)
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signal opRIB1 : ldata_t; --! RIB1 (PDP8)
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--!
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--! EAE
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--!
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signal opEAELAC : ldata_t; --! LAC <- EAE(0 to 12)
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signal opEAEZAC : ldata_t; --! LAC <- '0' & EAE(1 to 12)
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--!
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--! Flags
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--!
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signal opPRS : ldata_t; --!
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signal opGTF1 : ldata_t; --!
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signal opGTF2 : ldata_t; --!
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signal opGCF : ldata_t; --!
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--!
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--! MD operations
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--!
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signal opSUBMD : ldata_t; --! LAC <- LAC - MD
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signal opADDMD : ldata_t; --! LAC <- LAC + MD
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signal opADDMDP1 : ldata_t; --! LAC <- LAC + MD + 1
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signal opANDMD : ldata_t; --! LAC <- L & (AC and MD)
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signal opORMD : ldata_t; --! LAC <- L & (AC or MD)
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--!
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--! MQ Operations
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--!
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signal opMQSUB : ldata_t; --! LAC <- MQ - AC
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signal opMQ : ldata_t; --! LAC <- L & MQ
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signal opZMQ : ldata_t; --! LAC <- '0' & MQ
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signal opMQP1 : ldata_t; --! LAC <- MQ + 1
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signal opNEGMQ : ldata_t; --! LAC <- -MQ
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signal opNOTMQ : ldata_t; --! LAC <- not(MQ)
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signal opORMQ : ldata_t; --! LAC <- L & (AC or MQ)
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--!
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--! SC Operations
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--!
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signal opSCA : ldata_t; --! LAC <- L & (AC or SC)
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--!
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--! SP Operations
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--!
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signal opSP1 : ldata_t; --! LAC <- '0' & SP1
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signal opSP2 : ldata_t; --! LAC <- '0' & SP2
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--!
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--! SR Operations
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--!
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signal opOSR : ldata_t; --! LAC <- L & (AC or SR)
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signal opLAS : ldata_t; --! LAC <- L & SR
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begin
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-- group1 sequence 4 operations
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opIAC <= std_logic_vector(unsigned(lacREG) + "1");
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opBSW <= lacREG(0) & lacREG(7 to 12) & lacREG(1 to 6);
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-- rotate lefts
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opRAL <= lacREG( 1 to 12) & lacREG(0);
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opRTL <= lacREG( 2 to 12) & lacREG(0 to 1);
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opR3L <= lacREG( 3 to 12) & lacREG(0 to 2);
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-- rotate rights
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opRAR <= lacREG(12) & lacREG(0 to 11);
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opRTR <= lacREG(11 to 12) & lacREG(0 to 10);
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-- shift lefts
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opSHL0 <= lacREG( 1 to 12) & '0';
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opSHL1 <= lacREG( 1 to 12) & '1';
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-- shift rights
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opLSR <= '0' & lacREG(0 to 11);
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opASR <= lacREG(1) & lacREG(1) & lacREG(1 to 11);
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-- undefs
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opUNDEF1 <= lacREG(0) & (lacREG(1 to 12) and IR);
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opUNDEF2 <= lacREG(0) & MA(0 to 4) & IR(5 to 11);
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opPC <= lacREG(0) & PC;
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-- group 1 operations
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opCML <= not(lacREG(0)) & lacREG(1 to 12);
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opCMA <= lacREG(0) & not(lacREG(1 to 12));
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opCMACML <= not(lacREG(0)) & not(lacREG(1 to 12));
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opCLL <= '0' & lacREG(1 to 12);
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opCLLCML <= '1' & lacREG(1 to 12);
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opCLLCMA <= '0' & not(lacREG(1 to 12));
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opCLLCMACML <= '1' & not(lacREG(1 to 12));
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opCLA <= lacREG(0) & o"0000";
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opCLACML <= not(lacREG(0)) & o"0000";
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opCLACMA <= lacREG(0) & o"7777";
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opCLACMACML <= not(lacREG(0)) & o"7777";
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opCLACLL <= '0' & o"0000";
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opCLACLLCML <= '1' & o"0000";
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opCLACLLCMA <= '0' & o"7777";
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opCLACLLCMACML <= '1' & o"7777";
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-- KM8E ops
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opRDF0 <= lacREG(0 to 6) & DF & lacREG(10 to 12);
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opRIF0 <= lacREG(0 to 6) & INF & lacREG(10 to 12);
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opRIB0 <= lacREG(0 to 5) & SF;
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opRDF1 <= lacREG(0 to 12) or ("0000000" & DF & "000");
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opRIF1 <= lacREG(0 to 12) or ("0000000" & INF & "000");
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opRIB1 <= lacREG(0 to 12) or ("000000" & SF);
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-- Flags
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opPRS <= lacREG(0) & BTSTRP & PNLTRP & IRQ & PWRTRP & HLTTRP & '0' & "000" & "000";
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opGTF1 <= lacREG(0) & lacREG(0) & GTF & IRQ & PWRTRP & '1' & '0' & SF(1 to 3) & SF(4 to 6);
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opGTF2 <= lacREG(0) & lacREG(0) & GTF & IRQ & '0' & IE & SF(0) & SF(1 to 3) & SF(4 to 6);
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opGCF <= lacREG(0) & lacREG(0) & GTF & IRQ & PWRTRP & IE & '0' & INF & DF;
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-- EAE
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opEAELAC <= EAE(0 to 12);
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opEAEZAC <= '0' & EAE(1 to 12);
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-- MD
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opADDMD <= std_logic_vector(unsigned(lacREG(0 to 12)) + unsigned('0' & MD));
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opADDMDP1 <= std_logic_vector(unsigned(lacREG(0 to 12)) + unsigned('0' & MD) + "1");
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opSUBMD <= std_logic_vector(unsigned(lacREG(0 to 12)) - unsigned('0' & MD));
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opANDMD <= lacREG(0) & (lacREG(1 to 12) and MD);
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opORMD <= lacREG(0) & (lacREG(1 to 12) or MD);
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-- MQ
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opMQSUB <= std_logic_vector(unsigned('0' & MQ) + unsigned('0' & not(lacREG(1 to 12))) + "1");
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opMQ <= lacREG(0) & MQ;
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opZMQ <= '0' & MQ;
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opMQP1 <= std_logic_vector(unsigned('0' & MQ) + "1");
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opNEGMQ <= std_logic_vector(unsigned('0' & not(MQ)) + "1");
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opNOTMQ <= '0' & not(MQ);
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opORMQ <= lacREG(0) & (lacREG(1 to 12) or MQ);
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-- SC
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opSCA <= lacREG(0 to 7) & (lacREG(8 to 12) or SC);
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-- SP
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opSP1 <= lacREG(0) & SP1;
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opSP2 <= lacREG(0) & SP2;
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-- SR
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opLAS <= lacREG(0) & SR;
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opOSR <= lacREG(0) & (lacREG(1 to 12) or SR);
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--
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-- Adder input #2 mux.
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--
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with acOP select
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lacMUX <= lacREG when acopNOP, -- LAC <- LAC
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opIAC when acopIAC, -- LAC <- LAC + 1
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opBSW when acopBSW, -- LAC <- L & AC(6:12) & AC(0:5);
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opRAL when acopRAL, -- LAC <- AC(0:11) & L
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opRTL when acopRTL, -- LAC <- AC(1:11) & L & AC(0)
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opR3L when acopR3L, -- LAC <- AC(2:11) & L & AC(0:1)
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opRAR when acopRAR, -- LAC <- AC(11) & L & & AC(0:10);
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opRTR when acopRTR, -- LAC <- AC(10:11) & L & & AC(0:9);
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opSHL0 when acopSHL0, -- LAC <- (LAC << 1) & '0'
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| 297 |
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opSHL1 when acopSHL1, -- LAC <- (LAC << 1) & '1'
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| 298 |
|
|
opLSR when acopLSR, -- LAC <- '0' & (LAC >> 1)
|
| 299 |
|
|
opASR when acopASR, -- LAC <- L & (LAC >> 1)
|
| 300 |
|
|
opUNDEF1 when acopUNDEF1, -- LAC <- L & (AC and IR);
|
| 301 |
|
|
opUNDEF2 when acopUNDEF2, -- LAC <- L & MA(0:4) & IR(5:11)
|
| 302 |
|
|
opPC when acopPC, -- LAC <- PC
|
| 303 |
|
|
opCML when acopCML, -- LAC <- 0 0 0 CML
|
| 304 |
|
|
opCMA when acopCMA, -- LAC <- 0 0 CMA 0
|
| 305 |
|
|
opCMACML when acopCMACML, -- LAC <- 0 0 CMA CML
|
| 306 |
|
|
opCLL when acopCLL, -- LAC <- 0 CLL 0 0
|
| 307 |
|
|
opCLLCML when acopCLLCML, -- LAC <- 0 CLL 0 CML
|
| 308 |
|
|
opCLLCMA when acopCLLCMA, -- LAC <- 0 CLL CMA 0
|
| 309 |
|
|
opCLLCMACML when acopCLLCMACML, -- LAC <- 0 CLL CMA CML
|
| 310 |
|
|
opCLA when acopCLA, -- LAC <- CLA 0 0 0
|
| 311 |
|
|
opCLACML when acopCLACML, -- LAC <- CLA 0 0 CML
|
| 312 |
|
|
opCLACMA when acopCLACMA, -- LAC <- CLA 0 CMA 0
|
| 313 |
|
|
opCLACMACML when acopCLACMACML, -- LAC <- CLA 0 CMA CML
|
| 314 |
|
|
opCLACLL when acopCLACLL, -- LAC <- CLA CLL 0 0
|
| 315 |
|
|
opCLACLLCML when acopCLACLLCML, -- LAC <- CLA CLL 0 CML
|
| 316 |
|
|
opCLACLLCMA when acopCLACLLCMA, -- LAC <- CLA CLL CMA 0
|
| 317 |
|
|
opCLACLLCMACML when acopCLACLLCMACML,-- LAC <- CLA CLL CMA CML
|
| 318 |
|
|
opRDF0 when acopRDF0, -- LAC <- LAC(0 to 6) & DF & LAC(10 to 12)
|
| 319 |
|
|
opRIF0 when acopRIF0, -- LAC <- LAC(0 to 6) & INF & LAC(10 to 12);
|
| 320 |
|
|
opRIB0 when acopRIB0, -- LAC <- LAC(0 to 5) & SF
|
| 321 |
|
|
opRDF1 when acopRDF1, -- LAC <- LAC(0 to 12) or ("0000000" & DF & "000");
|
| 322 |
|
|
opRIF1 when acopRIF1, -- LAC <- LAC(0 to 12) or ("0000000" & INF & "000")
|
| 323 |
|
|
opRIB1 when acopRIB1, -- LAC <- LAC(0 to 12) or ("000000" & SF);
|
| 324 |
|
|
opPRS when acopPRS, -- LAC <- LAC(0) & BTSTRP & PNLTRP & IRQ & PWRTRP & HLTTRP & '0' & "000" & "000";
|
| 325 |
|
|
opGTF1 when acopGTF1, -- HD6120 GTF
|
| 326 |
|
|
opGTF2 when acopGTF2, -- PDP8 GTF
|
| 327 |
|
|
opGCF when acopGCF, -- LAC <- LAC(0) & LAC(0) & GTF & IRQ & PWRTRP & IE & '0' & INF & DF;
|
| 328 |
|
|
opEAELAC when acopEAELAC, -- LAC <- EAE(0 to 12)
|
| 329 |
|
|
opEAEZAC when acopEAEZAC, -- LAC <- '0' & EAE(1 to 12);
|
| 330 |
|
|
opSUBMD when acopSUBMD, -- LAC <- LAC - MD <- LAC + NOT(MD) + 1
|
| 331 |
|
|
opADDMD when acopADDMD, -- LAC <- LAC + MD
|
| 332 |
|
|
opADDMDP1 when acopADDMDP1, -- LAC <- LAC + MD + 1
|
| 333 |
|
|
opANDMD when acopANDMD, -- LAC <- L & (AC and MD)
|
| 334 |
|
|
opORMD when acopORMD, -- LAC <- L & (AC or MD)
|
| 335 |
|
|
opMQSUB when acopMQSUB, -- LAC <- MQ - AC <- MQ + NOT(AC) + 1
|
| 336 |
|
|
opMQ when acopMQ, -- LAC <- L & MQ
|
| 337 |
|
|
opZMQ when acopZMQ, -- LAC <- 0 & MQ
|
| 338 |
|
|
opMQP1 when acopMQP1, -- LAC <- MQ + 1
|
| 339 |
|
|
opNEGMQ when acopNEGMQ, -- LAC <- -MQ <- NOT(MQ) + 1
|
| 340 |
|
|
opNOTMQ when acopNOTMQ, -- LAC <- NOT(MQ)
|
| 341 |
|
|
opORMQ when acopORMQ, -- LAC <- L & (AC or MQ)
|
| 342 |
|
|
opSCA when acopSCA, -- LAC <- LAC(0 to 7) & (LAC(8 to 12) or SC)
|
| 343 |
|
|
opSP1 when acopSP1, -- LAC <- LAC(0) & SP1
|
| 344 |
|
|
opSP2 when acopSP2, -- LAC <- LAC(0) & SP2
|
| 345 |
|
|
opLAS when acopLAS, -- LAC <- SR
|
| 346 |
|
|
opOSR when acopOSR, -- LAC <- LAC(0) & (LAC(1 to 12) or SR)
|
| 347 |
|
|
(others => '0') when others; --
|
| 348 |
|
|
|
| 349 |
|
|
--
|
| 350 |
|
|
--! ALU Register
|
| 351 |
|
|
--
|
| 352 |
|
|
|
| 353 |
|
|
REG_ALU : process(sys)
|
| 354 |
|
|
begin
|
| 355 |
|
|
if sys.rst = '1' then
|
| 356 |
|
|
lacREG <= (others => '0');
|
| 357 |
|
|
elsif rising_edge(sys.clk) then
|
| 358 |
|
|
lacREG <= lacMUX;
|
| 359 |
|
|
end if;
|
| 360 |
|
|
end process REG_ALU;
|
| 361 |
|
|
|
| 362 |
|
|
LAC <= lacREG;
|
| 363 |
|
|
|
| 364 |
|
|
end rtl;
|
