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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Extended Arithmetic Element (EAE)
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--!
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--! \file
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--! eae.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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use work.cpu_types.all; --! Types
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--
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--! CPU Extended Arithmetic Element (EAE) Entity
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--
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entity eEAE is
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port (
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sys : in sys_t; --! Clock/Reset
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eaeOP : in eaeOP_t; --! EAE Operation
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MD : in data_t; --! MD Register
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MQ : in data_t; --! MQ Register
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AC : in data_t; --! AC register
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EAE : out eae_t --! EAE Output
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);
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end eEAE;
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--
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--! CPU Extended Arithmetic Element (EAE) RTL
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--
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architecture rtl of eEAE is
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signal eaeREG : eae_t; --! EAE Register
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signal eaeMUX : eae_t; --! EAE Multiplexer
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signal temp1 : unsigned(0 to 24);
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--
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-- Function to implement 24bit ASR
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--
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function asr24(i : std_logic_vector; sc : std_logic_vector) return std_logic_vector is
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constant count : integer := to_integer(unsigned(sc));
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begin
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case count is
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when 0 =>
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return i(1) & i(1 to 24);
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when 1 =>
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return i(1) & i(1) & i(1 to 23);
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when 2 =>
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return i(1) & i(1) & i(1) & i(1 to 22);
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when 3 =>
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return i(1) & i(1) & i(1) & i(1) & i(1 to 21);
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when 4 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 20);
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when 5 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 19);
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when 6 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 18);
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when 7 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 17);
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when 8 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1 to 16);
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when 9 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1 to 15);
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when 10 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1 to 14);
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when 11 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1 to 13);
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when 12 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1 to 12);
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when 13 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 11);
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when 14 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 10);
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when 15 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 9);
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when 16 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 8);
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when 17 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1 to 7);
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when 18 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1 to 6);
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when 19 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1 to 5);
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when 20 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1 to 4);
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when 21 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1 to 3);
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when 22 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1 to 2);
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when 23 =>
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return i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1) &
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i(1) & i(1) & i(1) & i(1) & i(1) & i(1) & i(1);
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when others =>
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return i;
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end case;
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end asr24;
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--
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-- Function to implement 24bit LSR
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--
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function lsr24(i : std_logic_vector; sc : std_logic_vector) return std_logic_vector is
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constant count : integer := to_integer(unsigned(sc));
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begin
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case count is
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when 0 =>
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return '0' & i(1 to 24);
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when 1 =>
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return '0' & '0' & i(1 to 23);
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when 2 =>
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return '0' & '0' & '0' & i(1 to 22);
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when 3 =>
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return '0' & '0' & '0' & '0' & i(1 to 21);
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when 4 =>
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return '0' & '0' & '0' & '0' & '0' & i(1 to 20);
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when 5 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & i(1 to 19);
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when 6 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & i(1 to 18);
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when 7 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & i(1 to 17);
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when 8 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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i(1 to 16);
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when 9 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & i(1 to 15);
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when 10 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & i(1 to 14);
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when 11 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & '0' & i(1 to 13);
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when 12 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & '0' & '0' & i(1 to 12);
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when 13 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & '0' & '0' & '0' & i(1 to 11);
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when 14 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & '0' & '0' & '0' & '0' & i(1 to 10);
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when 15 =>
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| 204 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & i(1 to 9);
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| 206 |
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when 16 =>
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 208 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & i(1 to 8);
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| 209 |
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when 17 =>
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| 210 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 211 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 212 |
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i(1 to 7);
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| 213 |
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when 18 =>
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| 214 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 215 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 216 |
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'0' & i(1 to 6);
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| 217 |
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when 19 =>
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| 218 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 219 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 220 |
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'0' & '0' & i(1 to 5);
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| 221 |
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when 20 =>
|
| 222 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 223 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 224 |
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'0' & '0' & '0' & i(1 to 4);
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| 225 |
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when 21 =>
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| 226 |
|
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 227 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 228 |
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'0' & '0' & '0' & '0' & i(1 to 3);
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| 229 |
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when 22 =>
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| 230 |
|
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 231 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 232 |
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'0' & '0' & '0' & '0' & '0' & i(1 to 2);
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| 233 |
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when 23 =>
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| 234 |
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return '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
|
| 235 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
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| 236 |
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'0' & '0' & '0' & '0' & '0' & '0' & '0';
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| 237 |
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when others =>
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| 238 |
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return i;
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| 239 |
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end case;
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| 240 |
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end lsr24;
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| 241 |
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|
| 242 |
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--
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| 243 |
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|
-- Function to implement 24bit SHL
|
| 244 |
|
|
--
|
| 245 |
|
|
|
| 246 |
|
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function shl24(i : std_logic_vector; sc : std_logic_vector) return std_logic_vector is
|
| 247 |
|
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constant count : integer := to_integer(unsigned(sc));
|
| 248 |
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begin
|
| 249 |
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case count is
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| 250 |
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when 0 =>
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| 251 |
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return i( 0 to 24);
|
| 252 |
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when 1 =>
|
| 253 |
|
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return i( 1 to 24) & "0";
|
| 254 |
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when 2 =>
|
| 255 |
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return i( 2 to 24) & "00";
|
| 256 |
|
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when 3 =>
|
| 257 |
|
|
return i( 3 to 24) & "000";
|
| 258 |
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when 4 =>
|
| 259 |
|
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return i( 4 to 24) & "0000";
|
| 260 |
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when 5 =>
|
| 261 |
|
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return i( 5 to 24) & "00000";
|
| 262 |
|
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when 6 =>
|
| 263 |
|
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return i( 6 to 24) & "000000";
|
| 264 |
|
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when 7 =>
|
| 265 |
|
|
return i( 7 to 24) & "0000000";
|
| 266 |
|
|
when 8 =>
|
| 267 |
|
|
return i( 8 to 24) & "00000000";
|
| 268 |
|
|
when 9 =>
|
| 269 |
|
|
return i( 9 to 24) & "000000000";
|
| 270 |
|
|
when 10 =>
|
| 271 |
|
|
return i(10 to 24) & "0000000000";
|
| 272 |
|
|
when 11 =>
|
| 273 |
|
|
return i(11 to 24) & "00000000000";
|
| 274 |
|
|
when 12 =>
|
| 275 |
|
|
return i(12 to 24) & "000000000000";
|
| 276 |
|
|
when 13 =>
|
| 277 |
|
|
return i(13 to 24) & "0000000000000";
|
| 278 |
|
|
when 14 =>
|
| 279 |
|
|
return i(14 to 24) & "00000000000000";
|
| 280 |
|
|
when 15 =>
|
| 281 |
|
|
return i(15 to 24) & "000000000000000";
|
| 282 |
|
|
when 16 =>
|
| 283 |
|
|
return i(16 to 24) & "0000000000000000";
|
| 284 |
|
|
when 17 =>
|
| 285 |
|
|
return i(17 to 24) & "00000000000000000";
|
| 286 |
|
|
when 18 =>
|
| 287 |
|
|
return i(18 to 24) & "000000000000000000";
|
| 288 |
|
|
when 19 =>
|
| 289 |
|
|
return i(19 to 24) & "0000000000000000000";
|
| 290 |
|
|
when 20 =>
|
| 291 |
|
|
return i(20 to 24) & "00000000000000000000";
|
| 292 |
|
|
when 21 =>
|
| 293 |
|
|
return i(21 to 24) & "000000000000000000000";
|
| 294 |
|
|
when 22 =>
|
| 295 |
|
|
return i(22 to 24) & "0000000000000000000000";
|
| 296 |
|
|
when 23 =>
|
| 297 |
|
|
return i(23 to 24) & "00000000000000000000000";
|
| 298 |
|
|
when 24 =>
|
| 299 |
|
|
return i(24 to 24) & "000000000000000000000000";
|
| 300 |
|
|
when others =>
|
| 301 |
|
|
return "0000000000000000000000000";
|
| 302 |
|
|
end case;
|
| 303 |
|
|
end shl24;
|
| 304 |
|
|
|
| 305 |
|
|
begin
|
| 306 |
|
|
|
| 307 |
|
|
temp1 <= ('0' & unsigned(MD) * unsigned(MQ)) + unsigned(AC);
|
| 308 |
|
|
|
| 309 |
|
|
--
|
| 310 |
|
|
-- EAE Multiplexer
|
| 311 |
|
|
--
|
| 312 |
|
|
|
| 313 |
|
|
with eaeOP select
|
| 314 |
|
|
eaeMUX <= eaeREG when eaeopNOP, -- EAE <- EAE
|
| 315 |
|
|
std_logic_vector(temp1) when eaeopMUY; -- EAE <- (MQ * MD) + AC;
|
| 316 |
|
|
--asr24(eaeREG, MD) when eaeopASRMD, -- EAE <- EAE ASR MD
|
| 317 |
|
|
--lsr24(eaeREG, MD) when eaeopLSRMD, -- EAE <- EAE LSR MD
|
| 318 |
|
|
--shl24(eaeREG, MD) when eaeopSHLMD; -- EAE <- EAE SHL MD
|
| 319 |
|
|
--
|
| 320 |
|
|
--! EAE Register
|
| 321 |
|
|
--
|
| 322 |
|
|
|
| 323 |
|
|
REG_EAE : process(sys)
|
| 324 |
|
|
begin
|
| 325 |
|
|
if sys.rst = '1' then
|
| 326 |
|
|
eaeREG <= (others => '0');
|
| 327 |
|
|
elsif rising_edge(sys.clk) then
|
| 328 |
|
|
eaeREG <= eaeMUX;
|
| 329 |
|
|
end if;
|
| 330 |
|
|
end process REG_EAE;
|
| 331 |
|
|
|
| 332 |
|
|
EAE <= eaeREG;
|
| 333 |
|
|
|
| 334 |
|
|
end rtl;
|
