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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--!      CPU ION Delay (ID) Register
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--!
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--! \details
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--!      The ION Delay (ID) register delays the effect of the ION
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--!      instruction until the instruction after the ION
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--!      instruction has executed.   This will allow a return
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--!      from interrupt to be executed before the next interrupt
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--!      request is serviced.
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--!
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--!      The ID register is set by the ION IOT instruction.
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--!
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--!      If the ID register is set during the state that checks
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--!      for interupt activity, the interrupt will not occur.
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--!
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--!      After the interrupt check, the ION Register is cleared.
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--!      Any deferred interrupts will be processed before the
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--!      next instruction.
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--!
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--! \file
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--!      id.vhd
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--!
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--! \author
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--!      Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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--  Copyright (C) 2009, 2010, 2011 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee;                                   --! IEEE Library
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use ieee.std_logic_1164.all;                    --! IEEE 1164
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use work.cpu_types.all;                         --! Types
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--
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--! CPU ION Delay (ID) Register Entity
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--
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entity eID is port (
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    sys  : in  sys_t;                           --! Clock/Reset
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    idOP : in  idOP_t;                          --! ID Operation
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    ID   : out std_logic                        --! ID Output
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);
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end eID;
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--
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--! CPU ION Delay (ID) Register RTL
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--
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architecture rtl of eID is
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    signal idREG : std_logic;                   -- ION Delay Register
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    signal idMUX : std_logic;                   -- ION Delay Register Multiplexer
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begin
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    --
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    -- ID Multiplexer
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    --
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    with idOP select
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        idMUX <= idREG when idopNOP,
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                 '0'   when idopCLR,
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                 '1'   when idopSET;
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    --
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    --! ID Register
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    --
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    REG_ID : process(sys)
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    begin
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        if sys.rst = '1' then
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            idREG <= '0';
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        elsif rising_edge(sys.clk) then
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            idREG <= idMUX;
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        end if;
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    end process REG_ID;
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    ID <= idREG;
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end rtl;

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