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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Interrupt Enable (IE) Register
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--!
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--! The IE register is modified under the following
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--! conditions:
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--! -# the IE Register is cleared on entry to an interrupt,
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--! and
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--! -# the IE Register is cleared when the Front Panel CLEAR
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--! switch is asserted, and
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--! -# the IE Register is cleared when the Skip If Interupt
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--! System Is On (SKON) instruction is executed, and
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--! -# the IE Register is cleared when the Interrupt Disable
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--! (IOF) instruction is executed, and
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--! -# the IE Register is set when the Interrupt Enable
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--! (ION) instruction is executed, and
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--!
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--! \note
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--! Per tribal knowledge, several unimplemented
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--! instructions have the side-effect of performing an
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--! interrupt Enable (ION) instruction which also sets
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--! the IE Register. These are enumerated in the CPU
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--! VHDL code, but not summarized here.
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--!
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--! \file
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--! ie.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use work.cpu_types.all; --! Types
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--
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--! CPU Interrupt Enable (IE) Register Entity
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--
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entity eIE is port (
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sys : in sys_t; --! Clock/Reset
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ieOP : in ieOP_t; --! IE Operation
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IE : out std_logic --! IE Output
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);
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end eIE;
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--
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--! CPU Interrupt Enable (IE) Register RTL
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--
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architecture rtl of eIE is
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signal ieREG : std_logic; --! Interrupt Enable Flip-Flop
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signal ieMUX : std_logic; --! Interrupt Enable Flip-Flop Multiplexer
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begin
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--
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-- IE Multiplexer
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--
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with ieOP select
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ieMUX <= ieREG when ieopNOP,
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'0' when ieopCLR,
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'1' when ieopSET;
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--
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--! IE Register
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--
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REG_IE : process(sys)
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begin
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if sys.rst = '1' then
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ieREG <= '0';
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elsif rising_edge(sys.clk) then
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ieREG <= ieMUX;
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end if;
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end process REG_IE;
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IE <= ieREG;
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end rtl;
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