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-----------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Program Counter (PC) Register
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--!
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--! \details
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--! The Program Counter (PC) Register contains the address
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--! of the next instruction to be executed.
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--!
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--! A block diagram of the PC block is illustrated below.
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--!
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--! \image
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--! html pc.png "Program Counter Block Diagram"
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--!
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--! Of note, the PC contains it's own adder which really
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--! only adds by 0 or 1. Similarly the PC contains a
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--! couple of constants that are used for PDP8 interrupts,
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--! HD-6120 Panel Traps, etc.
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--!
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--! \file
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--! pc.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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use work.cpu_types.all; --! CPU Types
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--
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--! CPU Program Counter (PC) Register Entity
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--
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entity ePC is port (
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sys : in sys_t; --! Clock/Reset
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pcOP : in pcOP_t; --! PC Operation
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IR : in data_t; --! Instruction Register
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MA : in addr_t; --! Memory Address Register
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MB : in data_t; --! Memory Data Register
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MD : in data_t; --! Memory Data
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SR : in data_t; --! Switch Register
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PC : out addr_t --! PC Output
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);
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end ePC;
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--
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--! CPU Program Counter (PC) Register RTL
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--
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architecture rtl of ePC is
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signal pcREG : addr_t; --! Program Counter
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signal addMUX1 : addr_t; --! Adder Mux #1
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signal addMUX2 : addr_t; --! Adder Mux #2
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signal CP : addr_t; --! Current Page Addr
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signal ZP : addr_t; --! Zero Page Addr
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begin
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--
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-- Current Page and Zero Page addresses
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--
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CP <= MA(0 to 4) & IR(5 to 11); -- Current Page Addr
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ZP <= "00000" & IR(5 to 11); -- Zero Page Addr
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--
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-- Adder input #1 mux.
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-- This will synthesize into a 16x12 ROM
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--
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with pcOP select
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addMUX1 <= o"0000" when pcopNOP, -- PC <- PC
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o"0000" when pcop0000, -- PC <- "0000"
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o"0001" when pcop0001, -- PC <- "0001"
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o"0000" when pcop7777, -- PC <- "7777"
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o"0000" when pcopMA, -- PC <- MA
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o"0000" when pcopMB, -- PC <- MB
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o"0000" when pcopMD, -- PC <- MD
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o"0000" when pcopSR, -- PC <- SR
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o"0000" when pcopZP, -- PC <- "00000" & IR(5 to 11)
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o"0000" when pcopCP, -- PC <- MA(0 to 4) & IR(5 to 11)
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o"0001" when pcopINC, -- PC <- PC + 1
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o"0001" when pcopMAP1, -- PC <- MA + 1
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o"0001" when pcopMBP1, -- PC <- MB + 1
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o"0001" when pcopMDP1, -- PC <- MD + 1
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o"0001" when pcopZPP1, -- PC <- ("00000" & IR(5 to 11)) + "1"
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o"0001" when pcopCPP1; -- PC <- (MA(0 to 4) & IR(5 to 11)) + "1"
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--
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-- Adder input #2 mux.
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--
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with pcOP select
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addMUX2 <= pcREG when pcopNOP, -- PC <- PC
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o"0000" when pcop0000, -- PC <- "0000"
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o"0000" when pcop0001, -- PC <- "0001"
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o"7777" when pcop7777, -- PC <- "7777"
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MA when pcopMA, -- PC <- MA
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MB when pcopMB, -- PC <- MB
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MD when pcopMD, -- PC <- MD
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SR when pcopSR, -- PC <- SR
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ZP when pcopZP, -- PC <- "00000" & IR(5 to 11
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CP when pcopCP, -- PC <- MA(0 to 4) & IR(5 to 11)
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pcREG when pcopINC, -- PC <- PC + 1
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MA when pcopMAP1, -- PC <- MA + 1
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MB when pcopMBP1, -- PC <- MB + 1
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MD when pcopMDP1, -- PC <- MD + 1
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ZP when pcopZPP1, -- PC <- ("00000" & IR(5 to 11)) + "1"
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CP when pcopCPP1; -- PC <- (MA(0 to 4) & IR(5 to 11)) + "1"
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--
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--! PC Register
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--
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REG_PC : process(sys)
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begin
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if sys.rst = '1' then
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pcREG <= o"0000";
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elsif rising_edge(sys.clk) then
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pcREG <= std_logic_vector(unsigned(addMUX2) + unsigned(addMUX1));
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end if;
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end process REG_PC;
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PC <= pcREG;
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end rtl;
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