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--------------------------------------------------------------------
2
--!
3
--! PDP-8 Processor
4
--!
5
--! \brief
6
--!      RK8E Secure Digital Interface
7
--!
8
--! \details
9
--!      The SD Interface reads or writes a 256 word (512 byte)
10
--!      sector to the SD device.  This interfaces uses a
11
--!      SPI interface (implemented independantly) to communicate
12
--!      with the SD device.
13
--!
14
--!      The RK8E controller has a LEN bit in the Command Register
15
--!      which causes the controller to perform a 128 word (256 byte)
16
--!      disk operation.   This eventually drives the sdLEN pin
17
--!      of this entity.
18
--!
19
--!      Section 11.14.7.11 of the External Bus Options Maintenance
20
--!      Manual Volume 3 says the following:
21
--!
22
--! \code
23
--!      If the RK8-E has been instructed to write 128 words,
24
--!      128th word is asserted after 128 words (half block)
25
--!      have been transferred.   The 128th word ends data
26
--!      transfer operations and the disk reads or writes zeros
27
--!      until the full block of data (256 words) has been read
28
--!      or written.
29
--! \endcode
30
--!
31
--!      It is fortunate that the controller works as described
32
--!      above because interactions between the controller and
33
--!      the SD disk are always 256 words (512 bytes).  The SD
34
--!      device cannot support 128 word (256 byte) transfers.
35
--!
36
--! \file
37
--!      sd.vhd
38
--!
39
--! \author
40
--!      Rob Doyle - doyle (at) cox (dot) net
41
--!
42
--------------------------------------------------------------------
43
--
44
--  Copyright (C) 2012 Rob Doyle
45
--
46
-- This source file may be used and distributed without
47
-- restriction provided that this copyright statement is not
48
-- removed from the file and that any derivative work contains
49
-- the original copyright notice and the associated disclaimer.
50
--
51
-- This source file is free software; you can redistribute it
52
-- and/or modify it under the terms of the GNU Lesser General
53
-- Public License as published by the Free Software Foundation;
54
-- version 2.1 of the License.
55
--
56
-- This source is distributed in the hope that it will be
57
-- useful, but WITHOUT ANY WARRANTY; without even the implied
58
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
59
-- PURPOSE. See the GNU Lesser General Public License for more
60
-- details.
61
--
62
-- You should have received a copy of the GNU Lesser General
63
-- Public License along with this source; if not, download it
64
-- from http://www.gnu.org/licenses/lgpl.txt
65
--
66
--------------------------------------------------------------------
67
--
68
-- Comments are formatted for doxygen
69
--
70
 
71
library ieee;                                   --! IEEE Library
72
use ieee.std_logic_1164.all;                    --! IEEE 1164
73
use ieee.numeric_std.all;                       --! IEEE Numeric Std
74
use work.cpu_types.all;                         --! CPU Types
75
use work.sdspi_types.all;                       --! SPI Types
76
use work.sd_types.all;                          --! SD Types
77
 
78
--
79
--! RK8E Secure Digital Interface Entity
80
--
81
 
82
entity eSD is port (
83
    sys        : in  sys_t;                     --! Clock/Reset
84
    ioclr      : in  std_logic;                 --! IOCLR
85
    -- PDP8 Interface
86
    dmaDIN     : in  data_t;                    --! DMA Data Into Disk
87
    dmaDOUT    : out data_t;                    --! DMA Data Out of Disk
88
    dmaADDR    : out addr_t;                    --! DMA Address
89
    dmaRD      : out std_logic;                 --! DMA Read
90
    dmaWR      : out std_logic;                 --! DMA Write
91
    dmaREQ     : out std_logic;                 --! DMA Request
92
    dmaGNT     : in  std_logic;                 --! DMA Grant
93
    -- Interface to SD Hardware
94
    sdMISO     : in  std_logic;                 --! SD Data In
95
    sdMOSI     : out std_logic;                 --! SD Data Out
96
    sdSCLK     : out std_logic;                 --! SD Clock
97
    sdCS       : out std_logic;                 --! SD Chip Select
98
    -- RK8E Interface
99
    sdOP       : in  sdOP_t;                    --! SD OP
100
    sdMEMaddr  : in  addr_t;                    --! Memory Address
101
    sdDISKaddr : in  sdDISKaddr_t;              --! Disk Address
102
    sdLEN      : in  sdLEN_t;                   --! Sector Length
103
    sdSTAT     : out sdSTAT_t                   --! Status
104
);
105
end eSD;
106
 
107
--
108
--! RK8E Secure Digital Interface RTL
109
--
110
 
111
architecture rtl of eSD is
112
 
113
    --
114
    -- Sending leading 0xff just sends clocks with data parked.
115
    --
116
 
117
    constant sdCMD0   : sdCMD_t := (x"40", x"00", x"00", x"00", x"00", x"95");
118
    constant sdCMD8   : sdCMD_t := (x"48", x"00", x"00", x"01", x"aa", x"87");
119
    constant sdCMD13  : sdCMD_t := (x"4d", x"00", x"00", x"00", x"00", x"ff");
120
    constant sdACMD41 : sdCMD_t := (x"69", x"40", x"00", x"00", x"00", x"ff");
121
    constant sdCMD55  : sdCMD_t := (x"77", x"00", x"00", x"00", x"00", x"ff");
122
    constant sdCMD58  : sdCMD_t := (x"7a", x"00", x"00", x"00", x"00", x"ff");
123
 
124
    type state_t is (stateRESET,
125
                     -- Init States
126
                     stateINIT00,
127
                     stateINIT01,
128
                     stateINIT02,
129
                     stateINIT03,
130
                     stateINIT04,
131
                     stateINIT05,
132
                     stateINIT06,
133
                     stateINIT07,
134
                     stateINIT08,
135
                     stateINIT09,
136
                     stateINIT10,
137
                     stateINIT11,
138
                     stateINIT12,
139
                     stateINIT13,
140
                     stateINIT14,
141
                     stateINIT15,
142
                     stateINIT16,
143
                     stateINIT17,
144
                     -- Read States
145
                     stateREAD00,
146
                     stateREAD01,
147
                     stateREAD02,
148
                     stateREAD03,
149
                     stateREAD04,
150
                     stateREAD05,
151
                     stateREAD06,
152
                     stateREAD07,
153
                     stateREAD08,
154
                     stateREAD09,
155
                     -- Write States
156
                     stateWRITE00,
157
                     stateWRITE01,
158
                     stateWRITE02,
159
                     stateWRITE03,
160
                     stateWRITE04,
161
                     stateWRITE05,
162
                     stateWRITE06,
163
                     stateWRITE07,
164
                     stateWRITE08,
165
                     stateWRITE09,
166
                     stateWRITE10,
167
                     stateWRITE11,
168
                     stateWRITE12,
169
                     stateWRITE13,
170
                     stateWRITE14,
171
                     stateWRITE15,
172
                     stateWRITE16,
173
                     -- Other States
174
                     stateFINI,
175
                     stateIDLE,
176
                     stateDONE,
177
                     stateINFAIL,
178
                     stateRWFAIL);
179
    signal   state   : state_t;                 --! Current State
180
    signal   spiOP   : spiOP_t;                 --! SPI Op
181
    signal   spiRXD  : sdBYTE_t;                --! SPI Received Data
182
    signal   spiTXD  : sdBYTE_t;                --! SPI Transmit Data
183
    signal   spiDONE : std_logic;               --! Asserted when SPI is done
184
    signal   bytecnt : integer range 0 to 65535;--! Byte Counter
185
    signal   sdCMD17 : sdCMD_t;                 --! CMD17
186
    signal   sdCMD24 : sdCMD_t;                 --! CMD24
187
    signal   memADDR : addr_t;                  --! Memory Address
188
    signal   memBUF  : std_logic_vector(0 to 3);--! Memory Buffer
189
    signal   memREQ  : std_logic;               --! DMA Request
190
    signal   abort   : std_logic;               --! Abort this command
191
    signal   timeout : integer range 0 to 499999;--! Timeout
192
    signal   rdCNT   : sdBYTE_t;                --! Read Counter
193
    signal   wrCNT   : sdBYTE_t;                --! Write Counter
194
    signal   err     : sdBYTE_t;                --! Error State
195
    signal   val     : sdBYTE_t;                --! Error Value
196
    signal   sdSTATE : sdSTATE_t;               --! State
197
    constant nCR     : integer := 8;            --! NCR from SD Spec
198
    constant nAC     : integer := 1023;         --! NAC from SD Spec
199
    constant nWR     : integer := 20;           --! NWR from SD Spec
200
 
201
begin
202
 
203
    --!
204
    --! SD_STATE:
205
    --! This process assumes a 50 MHz clock
206
    --
207
 
208
    SD_STATE : process(sys)
209
    begin
210
 
211
        if sys.rst = '1' then
212
            err     <= (others => '0');
213
            val     <= (others => '0');
214
            rdCNT   <= (others => '0');
215
            wrCNT   <= (others => '0');
216
            spiOP   <= spiNOP;
217
            bytecnt <= 0;
218
            dmaRD   <= '0';
219
            dmaWR   <= '0';
220
            memREQ  <= '0';
221
            memBUF  <= (others => '0');
222
            memADDR <= (others => '0');
223
            dmaDOUT <= (others => '0');
224
            spiTXD  <= (others => '0');
225
            sdCMD17 <= (x"51", x"00", x"00", x"00", x"00", x"ff");
226
            sdCMD24 <= (x"58", x"00", x"00", x"00", x"00", x"ff");
227
            abort   <= '0';
228
            bytecnt <= 0;
229
            dmaRD   <= '0';
230
            dmaWR   <= '0';
231
            memREQ  <= '0';
232
            spiOP   <= spiNOP;
233
            timeout <= 499999;
234
            sdSTATE <= sdstateINIT;
235
            state   <= stateRESET;
236
        elsif rising_edge(sys.clk) then
237
 
238
            dmaRD   <= '0';
239
            dmaWR   <= '0';
240
            spiOP   <= spiNOP;
241
 
242
            if sdOP = sdopABORT and state /= stateIDLE then
243
                abort <= '1';
244
            end if;
245
 
246
            case state is
247
 
248
                --
249
                -- stateRESET:
250
                --
251
 
252
                when stateRESET =>
253
                    timeout <= timeout - 1;
254
                    bytecnt <= 0;
255
                    state   <= stateINIT00;
256
 
257
                --
258
                -- stateINIT00
259
                --  Send 8x8 clocks cycles
260
                --
261
 
262
                when stateINIT00 =>
263
                    timeout <= timeout - 1;
264
                    if spiDONE = '1' or bytecnt = 0 then
265
                        if bytecnt = nCR then
266
                            bytecnt <= 0;
267
                            spiOP   <= spiCSL;
268
                            state   <= stateINIT01;
269
                        else
270
                            spiOP   <= spiTR;
271
                            spiTXD  <= x"ff";
272
                            bytecnt <= bytecnt + 1;
273
                        end if;
274
                    end if;
275
 
276
                --
277
                -- stateINIT01:
278
                --  Send GO_IDLE_STATE command (CMD0)
279
                --
280
 
281
                when stateINIT01 =>
282
                    timeout <= timeout - 1;
283
                    if spiDONE = '1' or bytecnt = 0 then
284
                        if bytecnt = 6 then
285
                            bytecnt <= 0;
286
                            state   <= stateINIT02;
287
                        else
288
                            spiOP   <= spiTR;
289
                            spiTXD  <= sdCMD0(bytecnt);
290
                            bytecnt <= bytecnt + 1;
291
                        end if;
292
                    end if;
293
 
294
                --
295
                -- stateINIT02:
296
                --  Read R1 Response from CMD0
297
                --  Response should be x"01"
298
                --
299
 
300
                when stateINIT02 =>
301
                    timeout <= timeout - 1;
302
                    if bytecnt = 0 then
303
                        spiOP   <= spiTR;
304
                        spiTXD  <= x"ff";
305
                        bytecnt <= 1;
306
                    else
307
                        if spiDONE = '1' then
308
                            if spiRXD = x"ff" then
309
                                if bytecnt = nCR then
310
                                    spiOP   <= spiCSH;
311
                                    bytecnt <= 0;
312
                                    state   <= stateRESET;
313
                                else
314
                                    spiOP   <= spiTR;
315
                                    spiTXD  <= x"ff";
316
                                    bytecnt <= bytecnt + 1;
317
                                end if;
318
                            else
319
                                spiOP   <= spiCSH;
320
                                bytecnt <= 0;
321
                                if spiRXD = x"01" then
322
                                    state <= stateINIT03;
323
                                else
324
                                    state <= stateRESET;
325
                                end if;
326
                            end if;
327
                        end if;
328
                    end if;
329
 
330
                --
331
                -- stateINIT03:
332
                --  Send 8 clock cycles
333
                --
334
 
335
                when stateINIT03 =>
336
                    timeout <= timeout - 1;
337
                    if bytecnt = 0 then
338
                        spiOP   <= spiTR;
339
                        spiTXD  <= x"ff";
340
                        bytecnt <= 1;
341
                    elsif spiDONE = '1' then
342
                        spiOP   <= spiCSL;
343
                        bytecnt <= 0;
344
                        state   <= stateINIT04;
345
                    end if;
346
 
347
                --
348
                -- stateINIT04:
349
                --   Send SEND_IF_COND (CMD8)
350
                --
351
 
352
                when stateINIT04 =>
353
                    timeout <= timeout - 1;
354
                    if spiDONE = '1' or bytecnt = 0 then
355
                        if bytecnt = 6 then
356
                            bytecnt <= 0;
357
                            state   <= stateINIT05;
358
                        else
359
                            spiOP   <= spiTR;
360
                            spiTXD  <= sdCMD8(bytecnt);
361
                            bytecnt <= bytecnt + 1;
362
                        end if;
363
                    end if;
364
 
365
                --
366
                -- stateINIT05
367
                --  Read first byte R1 of R7 Response
368
                --  Response should be x"01" for V2.00 initialization or
369
                --  x"05" for V1.00 initialization.
370
                --
371
 
372
                when stateINIT05 =>
373
                    timeout <= timeout - 1;
374
                    if bytecnt = 0 then
375
                        spiOP   <= spiTR;
376
                        spiTXD  <= x"ff";
377
                        bytecnt <= 1;
378
                    else
379
                        if spiDONE = '1' then
380
                            if spiRXD = x"ff" then
381
                                if bytecnt = nCR then
382
                                    spiOP   <= spiCSH;
383
                                    bytecnt <= 0;
384
                                    err     <= x"01";
385
                                    state   <= stateINFAIL;
386
                                else
387
                                    spiOP   <= spiTR;
388
                                    spiTXD  <= x"ff";
389
                                    bytecnt <= bytecnt + 1;
390
                                end if;
391
                            else
392
                                bytecnt   <= 0;
393
                                if spiRXD = x"01" then
394
                                    state <= stateINIT06;
395
                                elsif spiRXD <= x"05" then
396
                                    err   <= x"02";
397
                                    state <= stateINFAIL;
398
                                else
399
                                    spiOP <= spiCSH;
400
                                    err   <= x"03";
401
                                    state <= stateINFAIL;
402
                                end if;
403
                            end if;
404
                        end if;
405
                    end if;
406
 
407
                --
408
                -- stateINIT06
409
                --  Read 32-bit Response to CMD8
410
                --  Response should be x"00_00_01_aa"
411
                --    x"01" - Voltage
412
                --    x"55" - Pattern
413
                --
414
 
415
                when stateINIT06 =>
416
                    timeout <= timeout - 1;
417
                    case bytecnt is
418
                        when 0 =>
419
                            spiOP   <= spiTR;
420
                            spiTXD  <= x"ff";
421
                            bytecnt <= 1;
422
                         when 1 =>
423
                            if spiDONE = '1' then
424
                                if spiRXD = x"00" then
425
                                    spiOP   <= spiTR;
426
                                    spiTXD  <= x"ff";
427
                                    bytecnt <= 2;
428
                                else
429
                                    err   <= x"04";
430
                                    state <= stateINFAIL;
431
                                end if;
432
                            end if;
433
                         when 2 =>
434
                            if spiDONE = '1' then
435
                                if spiRXD = x"00" then
436
                                    spiOP   <= spiTR;
437
                                    spiTXD  <= x"ff";
438
                                    bytecnt <= 3;
439
                                else
440
                                    err   <= x"05";
441
                                    state <= stateINFAIL;
442
                                end if;
443
                            end if;
444
                         when 3 =>
445
                            if spiDONE = '1' then
446
                                if spiRXD = x"01" then
447
                                    spiOP   <= spiTR;
448
                                    spiTXD  <= x"ff";
449
                                    bytecnt <= 4;
450
                                else
451
                                    err   <= x"06";
452
                                    state <= stateINFAIL;
453
                                end if;
454
                            end if;
455
                         when 4 =>
456
                            if spiDONE = '1' then
457
                                if spiRXD = x"aa" then
458
                                    spiOP   <= spiCSH;
459
                                    bytecnt <= 0;
460
                                    state   <= stateINIT07;
461
                                else
462
                                    err   <= x"07";
463
                                    state <= stateINFAIL;
464
                                end if;
465
                            end if;
466
                         when others =>
467
                            null;
468
                    end case;
469
 
470
                --
471
                -- stateINIT07:
472
                --  Send 8 clock cycles
473
                --
474
 
475
                when stateINIT07 =>
476
                    timeout <= timeout - 1;
477
                    if bytecnt = 0 then
478
                        spiOP   <= spiTR;
479
                        spiTXD  <= x"ff";
480
                        bytecnt <= 1;
481
                    elsif spiDONE = '1' then
482
                        spiOP   <= spiCSL;
483
                        bytecnt <= 0;
484
                        state   <= stateINIT08;
485
                    end if;
486
 
487
                --
488
                -- stateINIT08:
489
                --   Send APP_CMD (CMD55)
490
                --
491
 
492
                when stateINIT08 =>
493
                    timeout <= timeout - 1;
494
                    if spiDONE = '1' or bytecnt = 0 then
495
                        if bytecnt = 6 then
496
                            bytecnt <= 0;
497
                            state   <= stateINIT09;
498
                        else
499
                            spiOP   <= spiTR;
500
                            spiTXD  <= sdCMD55(bytecnt);
501
                            bytecnt <= bytecnt + 1;
502
                        end if;
503
                    end if;
504
 
505
                --
506
                -- stateINIT09:
507
                --  Read R1 response from CMD55.
508
                --  Response should be x"01"
509
                --
510
 
511
                when stateINIT09 =>
512
                    timeout <= timeout - 1;
513
                    if bytecnt = 0 then
514
                        spiOP   <= spiTR;
515
                        spiTXD  <= x"ff";
516
                        bytecnt <= 1;
517
                    else
518
                        if spiDONE = '1' then
519
                            if spiRXD = x"ff" then
520
                                if bytecnt = nCR then
521
                                    spiOP   <= spiCSH;
522
                                    bytecnt <= 0;
523
                                    err     <= x"08";
524
                                    state   <= stateINFAIL;
525
                                else
526
                                    spiOP   <= spiTR;
527
                                    spiTXD  <= x"ff";
528
                                    bytecnt <= bytecnt + 1;
529
                                end if;
530
                            else
531
                                spiOP   <= spiCSH;
532
                                bytecnt <= 0;
533
                                if spiRXD = x"01" then
534
                                    state <= stateINIT10;
535
                                else
536
                                    state <= stateINIT07;
537
                                end if;
538
                            end if;
539
                        end if;
540
                    end if;
541
 
542
                --
543
                -- stateINIT10:
544
                --  Send 8 clock cycles
545
                --
546
 
547
                when stateINIT10 =>
548
                    timeout <= timeout - 1;
549
                    if bytecnt = 0 then
550
                        spiOP   <= spiTR;
551
                        spiTXD  <= x"ff";
552
                        bytecnt <= 1;
553
                    elsif spiDONE = '1' then
554
                        spiOP   <= spiCSL;
555
                        bytecnt <= 0;
556
                        state   <= stateINIT11;
557
                    end if;
558
 
559
                --
560
                -- stateINIT11:
561
                --  Send SD_SEND_OP_COND (ACMD41)
562
                --
563
 
564
                when stateINIT11 =>
565
                    timeout <= timeout - 1;
566
                    if spiDONE = '1' or bytecnt = 0  then
567
                        if bytecnt = 6 then
568
                            bytecnt <= 0;
569
                            state   <= stateINIT12;
570
                        else
571
                            spiOP   <= spiTR;
572
                            spiTXD  <= sdACMD41(bytecnt);
573
                            bytecnt <= bytecnt + 1;
574
                        end if;
575
                    end if;
576
 
577
                --
578
                -- stateINIT12:
579
                --  Read R1 response from ACMD41.
580
                --  Response should be x"00"
581
                --
582
 
583
                when stateINIT12 =>
584
                    timeout <= timeout - 1;
585
                    if bytecnt = 0 then
586
                        spiOP   <= spiTR;
587
                        spiTXD  <= x"ff";
588
                        bytecnt <= 1;
589
                    else
590
                        if spiDONE = '1' then
591
                            if spiRXD = x"ff" then
592
                                if bytecnt = nCR then
593
                                    spiOP   <= spiCSH;
594
                                    bytecnt <= 0;
595
                                    err     <= x"09";
596
                                    state   <= stateINFAIL;
597
                                else
598
                                    spiOP   <= spiTR;
599
                                    spiTXD  <= x"ff";
600
                                    bytecnt <= bytecnt + 1;
601
                                end if;
602
                            else
603
                                spiOP   <= spiCSH;
604
                                bytecnt <= 0;
605
                                if spiRXD = x"00" then
606
                                    state <= stateINIT13;
607
                                else
608
                                    state <= stateINIT07;
609
                                end if;
610
                            end if;
611
                        end if;
612
                    end if;
613
 
614
                --
615
                -- stateINIT13
616
                --  Send 8 clock cycles
617
                --
618
 
619
                when stateINIT13 =>
620
                    timeout <= timeout - 1;
621
                    if bytecnt = 0 then
622
                        spiOP   <= spiTR;
623
                        spiTXD  <= x"ff";
624
                        bytecnt <= 1;
625
                    elsif spiDONE = '1' then
626
                        spiOP   <= spiCSL;
627
                        bytecnt <= 0;
628
                        state   <= stateINIT14;
629
                    end if;
630
 
631
                --
632
                -- stateINIT14:
633
                --  Send READ_OCR (CMD58)
634
                --
635
 
636
                when stateINIT14 =>
637
                    timeout <= timeout - 1;
638
                    if spiDONE = '1' or bytecnt = 0 then
639
                        if bytecnt = 6 then
640
                            bytecnt <= 0;
641
                            state   <= stateINIT15;
642
                        else
643
                            spiOP   <= spiTR;
644
                            spiTXD  <= sdCMD58(bytecnt);
645
                            bytecnt <= bytecnt + 1;
646
                        end if;
647
                    end if;
648
 
649
                --
650
                -- stateINIT15
651
                --  Read first byte of R3 response to CMD58
652
                --  Response should be x"00"
653
                --
654
 
655
                when stateINIT15 =>
656
                    timeout <= timeout - 1;
657
                    if bytecnt = 0 then
658
                        spiOP   <= spiTR;
659
                        spiTXD  <= x"ff";
660
                        bytecnt <= 1;
661
                    else
662
                        if spiDONE = '1' then
663
                            if spiRXD = x"ff" then
664
                                if bytecnt = nCR then
665
                                    spiOP   <= spiCSH;
666
                                    bytecnt <= 0;
667
                                    err     <= x"0a";
668
                                    state   <= stateINFAIL;
669
                                else
670
                                    spiOP   <= spiTR;
671
                                    spiTXD  <= x"ff";
672
                                    bytecnt <= bytecnt + 1;
673
                                end if;
674
                            else
675
                                bytecnt    <= 0;
676
                                if spiRXD = x"00" then
677
                                    state <= stateINIT16;
678
                                else
679
                                    spiOP <= spiCSH;
680
                                    err   <= x"0b";
681
                                    state <= stateINFAIL;
682
                                end if;
683
                            end if;
684
                        end if;
685
                    end if;
686
 
687
                --
688
                -- stateINIT16
689
                --  Response should be "e0_ff_80_00"
690
                --  Read 32-bit OCR response to CMD58
691
                --
692
 
693
                when stateINIT16 =>
694
                    timeout <= timeout - 1;
695
                    case bytecnt is
696
                        when 0 =>
697
                            spiOP   <= spiTR;
698
                            spiTXD  <= x"ff";
699
                            bytecnt <= 1;
700
                         when 1 =>
701
                            if spiDONE = '1' then
702
                                spiOP      <= spiTR;
703
                                spiTXD     <= x"ff";
704
                                bytecnt    <= 2;
705
                            end if;
706
                         when 2 =>
707
                            if spiDONE = '1' then
708
                                spiOP      <= spiTR;
709
                                spiTXD     <= x"ff";
710
                                bytecnt    <= 3;
711
                            end if;
712
                         when 3 =>
713
                            if spiDONE = '1' then
714
                                spiOP      <= spiTR;
715
                                spiTXD     <= x"ff";
716
                                bytecnt    <= 4;
717
                            end if;
718
                         when 4 =>
719
                            if spiDONE = '1' then
720
                                spiOP      <= spiCSH;
721
                                bytecnt    <= 0;
722
                                state      <= stateINIT17;
723
                            end if;
724
                         when others =>
725
                            null;
726
                    end case;
727
 
728
                --
729
                -- stateINIT17:
730
                --  Send 8 clock cycles
731
                --
732
 
733
                when stateINIT17 =>
734
                    timeout <= timeout - 1;
735
                    if bytecnt = 0 then
736
                        spiOP   <= spiTR;
737
                        spiTXD  <= x"ff";
738
                        bytecnt <= 1;
739
                    elsif spiDONE = '1' then
740
                        bytecnt <= 0;
741
--                      spiOP   <= spiFAST;
742
                        state   <= stateIDLE;
743
                    end if;
744
 
745
                --
746
                -- stateIDLE:
747
                --  Wait for a command to process.
748
                --  Once the SD card is initialized, it waits in this state
749
                --  for either a read (sdopRD) or a write (sdopWR) command.
750
                --
751
 
752
                when stateIDLE =>
753
                    abort   <= '0';
754
                    sdSTATE <= sdstateREADY;
755
                    case sdOP is
756
                        when sdopNOP =>
757
                            state <= stateIDLE;
758
                        when sdopRD =>
759
                            rdCNT <= std_logic_vector(unsigned(rdCNT) + 1);
760
                            state <= stateREAD00;
761
                        when sdopWR =>
762
                            wrCNT <= std_logic_vector(unsigned(wrCNT) + 1);
763
                            state <= stateWRITE00;
764
                        when others =>
765
                            state <= stateIDLE;
766
                    end case;
767
 
768
                --
769
                -- stateREAD00:
770
                --  Setup Read Single Block (CMD17)
771
                --
772
 
773
                when stateREAD00 =>
774
                    sdSTATE    <= sdstateREAD;
775
                    memADDR    <= sdMEMaddr;
776
                    sdCMD17(0) <= x"51";
777
                    sdCMD17(1) <= sdDISKaddr( 0 to  7);
778
                    sdCMD17(2) <= sdDISKaddr( 8 to 15);
779
                    sdCMD17(3) <= sdDISKaddr(16 to 23);
780
                    sdCMD17(4) <= sdDISKaddr(24 to 31);
781
                    sdCMD17(5) <= x"ff";
782
                    bytecnt    <= 0;
783
                    spiOP      <= spiCSL;
784
                    state      <= stateREAD01;
785
 
786
                --
787
                -- stateREAD01:
788
                --  Send Read Single Block (CMD17)
789
                --
790
 
791
                when stateREAD01 =>
792
                    if spiDONE = '1' or bytecnt = 0 then
793
                        if bytecnt = 6 then
794
                            bytecnt <= 0;
795
                            state   <= stateREAD02;
796
                        else
797
                            spiOP   <= spiTR;
798
                            spiTXD  <= sdCMD17(bytecnt);
799
                            bytecnt <= bytecnt + 1;
800
                        end if;
801
                    end if;
802
 
803
                --
804
                -- stateREAD02:
805
                --  Read R1 response from CMD17
806
                --  Response should be x"00"
807
                --
808
 
809
                when stateREAD02 =>
810
                    if bytecnt = 0 then
811
                        spiOP   <= spiTR;
812
                        spiTXD  <= x"ff";
813
                        bytecnt <= 1;
814
                    else
815
                        if spiDONE = '1' then
816
                            if spiRXD = x"ff" then
817
                                if bytecnt = nCR then
818
                                    spiOP   <= spiCSH;
819
                                    bytecnt <= 0;
820
                                    err     <= x"0c";
821
                                    state   <= stateRWFAIL;
822
                                else
823
                                    spiOP   <= spiTR;
824
                                    spiTXD  <= x"ff";
825
                                    bytecnt <= bytecnt + 1;
826
                                end if;
827
                            else
828
                                bytecnt <= 0;
829
                                if spiRXD = x"00" then
830
                                    state <= stateREAD03;
831
                                else
832
                                    spiOP <= spiCSH;
833
                                    err   <= x"0d";
834
                                    state <= stateRWFAIL;
835
                                end if;
836
                            end if;
837
                        end if;
838
                    end if;
839
 
840
                --
841
                -- stateREAD03:
842
                --  Find 'Read Start token' which should be x"fe"
843
                --
844
 
845
                when stateREAD03 =>
846
                    if bytecnt = 0 then
847
                        spiOP   <= spiTR;
848
                        spiTXD  <= x"ff";
849
                        bytecnt <= 1;
850
                    else
851
                        if spiDONE = '1' then
852
                            if spiRXD = x"ff" then
853
                                if bytecnt = nAC then
854
                                    spiOP   <= spiCSH;
855
                                    bytecnt <= 0;
856
                                    err     <= x"0e";
857
                                    state   <= stateRWFAIL;
858
                                else
859
                                    spiOP   <= spiTR;
860
                                    spiTXD  <= x"ff";
861
                                    bytecnt <= bytecnt + 1;
862
                                end if;
863
                            else
864
                                bytecnt <= 0;
865
                                if spiRXD = x"fe" then
866
                                    state <= stateREAD04;
867
                                else
868
                                    spiOP <= spiCSH;
869
                                    err   <= x"0f";
870
                                    val   <= spiRXD;
871
                                    state <= stateRWFAIL;
872
                                end if;
873
                            end if;
874
                        end if;
875
                    end if;
876
 
877
                --
878
                -- stateREAD04:
879
                --  Acquire DMA.  Setup for loop.
880
                --
881
 
882
                when stateREAD04 =>
883
                    memREQ <= '1';
884
                    if dmaGNT = '1' then
885
                        spiOP   <= spiTR;
886
                        spiTXD  <= x"ff";
887
                        bytecnt <= 0;
888
                        state   <= stateREAD05;
889
                    end if;
890
 
891
                --
892
                -- stateREAD05:
893
                --  Read LSBYTE of data from disk (even addresses)
894
                --  Loop destination
895
                --
896
 
897
                when stateREAD05 =>
898
                    if spiDONE = '1' then
899
                        spiOP   <= spiTR;
900
                        spiTXD  <= x"ff";
901
                        bytecnt <= bytecnt + 1;
902
                        dmaDOUT(4 to 11) <= spiRXD(0 to 7);
903
                        state <= stateREAD06;
904
                    end if;
905
 
906
                --
907
                -- stateREAD06:
908
                --  Read MSBYTE of data from disk (odd addresses).
909
                --  Discard the top four bits forming a 12-bit word
910
                --  from the two bytes.
911
                --
912
 
913
                when stateREAD06 =>
914
                    if spiDONE = '1' then
915
                        spiOP   <= spiTR;
916
                        spiTXD  <= x"ff";
917
                        dmaDOUT(0 to  3) <= spiRXD(4 to 7);
918
                        state <= stateREAD07;
919
                    end if;
920
 
921
                --
922
                -- stateREAD07:
923
                --  Write disk data to memory.
924
                --  If memREQ is not asserted, we are reading the second
925
                --  128 words of a 128 word read.  Notice no DMA occurs
926
                --  to memory and the bits are dropped.
927
                --
928
 
929
                when stateREAD07 =>
930
                    if memREQ = '1' then
931
                        dmaWR <= '1';
932
                    end if;
933
                    state <= stateREAD08;
934
 
935
                --
936
                -- stateREAD08:
937
                --  This state checks the loop conditions:
938
                --  1.  An abort command causes the loop to terminate immediately.
939
                --  2.  If sdLEN is asserted (128 word read) at byte 255, then
940
                --      the memory write DMA request is dropped.  The DMA address
941
                --      stops incrementing.  The state machine continues to read
942
                --      all 256 words (512 bytes).
943
                --  3.  At word 256 (byte 512), the loop terminates.
944
                --
945
 
946
                when stateREAD08 =>
947
                    if abort = '1' then
948
                        memREQ  <= '0';
949
                        spiOP   <= spiCSH;
950
                        bytecnt <= 0;
951
                        state   <= stateFINI;
952
                    elsif bytecnt = 511 then
953
                        memREQ  <= '0';
954
                        memADDR <= std_logic_vector(unsigned(memADDR) + 1);
955
                        bytecnt <= 0;
956
                        state   <= stateREAD09;
957
                    elsif bytecnt >= 255 and sdLEN = '1' then
958
                        memREQ  <= '0';
959
                        bytecnt <= bytecnt + 1;
960
                        state   <= stateREAD05;
961
                    else
962
                        memADDR <= std_logic_vector(unsigned(memADDR) + 1);
963
                        bytecnt <= bytecnt + 1;
964
                        state   <= stateREAD05;
965
                    end if;
966
 
967
                --
968
                -- stateREAD09:
969
                --  Read 2 bytes of CRC which is required for the SD Card.
970
                --
971
 
972
                when stateREAD09 =>
973
                    if bytecnt = 0 then
974
                        spiOP   <= spiTR;
975
                        spiTXD  <= x"ff";
976
                        bytecnt <= 1;
977
                    else
978
                        if spiDONE = '1' then
979
                            if bytecnt = 1 then
980
                                spiOP   <= spiTR;
981
                                spiTXD  <= x"ff";
982
                                bytecnt <= 2;
983
                            elsif bytecnt = 2 then
984
                                spiOP   <= spiCSH;
985
                                bytecnt <= 0;
986
                                state   <= stateFINI;
987
                            end if;
988
                        end if;
989
                    end if;
990
 
991
                --
992
                -- stateWRITE00:
993
                --  Setup Write Single Block (CMD24)
994
                --
995
 
996
                when stateWRITE00 =>
997
                    sdSTATE    <= sdstateWRITE;
998
                    memADDR    <= sdMEMaddr;
999
                    sdCMD24(0) <= x"58";
1000
                    sdCMD24(1) <= sdDISKaddr( 0 to  7);
1001
                    sdCMD24(2) <= sdDISKaddr( 8 to 15);
1002
                    sdCMD24(3) <= sdDISKaddr(16 to 23);
1003
                    sdCMD24(4) <= sdDISKaddr(24 to 31);
1004
                    sdCMD24(5) <= x"ff";
1005
                    bytecnt    <= 0;
1006
                    spiOP      <= spiCSL;
1007
                    state      <= stateWRITE01;
1008
 
1009
                --
1010
                -- stateWRITE01:
1011
                --  Send Write Single Block (CMD24)
1012
                --
1013
 
1014
                when stateWRITE01 =>
1015
                    if spiDONE = '1' or bytecnt = 0 then
1016
                        if bytecnt = 6 then
1017
                            bytecnt <= 0;
1018
                            state   <= stateWRITE02;
1019
                        else
1020
                            spiOP   <= spiTR;
1021
                            spiTXD  <= sdCMD24(bytecnt);
1022
                            bytecnt <= bytecnt + 1;
1023
                        end if;
1024
                    end if;
1025
 
1026
                --
1027
                -- stateWRITE02:
1028
                --  Read R1 response from CMD24
1029
                --  Response should be x"00"
1030
                --
1031
 
1032
                when stateWRITE02 =>
1033
                    if bytecnt = 0 then
1034
                        spiOP   <= spiTR;
1035
                        spiTXD  <= x"ff";
1036
                        bytecnt <= 1;
1037
                    else
1038
                        if spiDONE = '1' then
1039
                            if spiRXD = x"ff" then
1040
                                if bytecnt = nCR then
1041
                                    spiOP   <= spiCSH;
1042
                                    bytecnt <= 0;
1043
                                    err     <= x"10";
1044
                                    state   <= stateRWFAIL;
1045
                                else
1046
                                    spiOP   <= spiTR;
1047
                                    spiTXD  <= x"ff";
1048
                                    bytecnt <= bytecnt + 1;
1049
                                end if;
1050
                            else
1051
                                bytecnt <= 0;
1052
                                if spiRXD = x"00" then
1053
                                    state <= stateWRITE03;
1054
                                else
1055
                                    spiOP <= spiCSH;
1056
                                    val   <= spiRXD;
1057
                                    err   <= x"11";
1058
                                    state <= stateRWFAIL;
1059
                                end if;
1060
                            end if;
1061
                        end if;
1062
                    end if;
1063
 
1064
                --
1065
                -- stateWRITE03:
1066
                --  Send 8 clock cycles
1067
                --
1068
 
1069
                when stateWRITE03 =>
1070
                    if bytecnt = 0 then
1071
                        spiOP   <= spiTR;
1072
                        spiTXD  <= x"ff";
1073
                        bytecnt <= 1;
1074
                    elsif spiDONE = '1' then
1075
                        bytecnt <= 0;
1076
                        state   <= stateWRITE04;
1077
                    end if;
1078
 
1079
                --
1080
                -- stateWRITE04:
1081
                --  Send "Write Start Token".  The write start token is x"fe"
1082
                --
1083
 
1084
                when stateWRITE04 =>
1085
                    if bytecnt = 0 then
1086
                        spiOP   <= spiTR;
1087
                        spiTXD  <= x"fe";
1088
                        bytecnt <= 1;
1089
                    elsif spiDONE = '1' then
1090
                        bytecnt <= 0;
1091
                        state   <= stateWRITE05;
1092
                    end if;
1093
 
1094
                --
1095
                -- stateWRITE05:
1096
                --  Start a DMA Read Address Cycle
1097
                --
1098
 
1099
                when stateWRITE05 =>
1100
                    memREQ <= '1';
1101
                    if dmaGNT = '1' then
1102
                        state <= stateWRITE06;
1103
                    end if;
1104
 
1105
                --
1106
                -- stateWRITE06:
1107
                --  Loop destination
1108
                --  This is the data phase of the read cycle.
1109
                --  If memREQ is not asserted, we are writing the second
1110
                --  128 words of a 128 word write.  Notice no DMA occurs.
1111
                --
1112
 
1113
                when stateWRITE06 =>
1114
                    if memREQ = '1' then
1115
                        dmaRD <= '1';
1116
                    end if;
1117
                    state <= stateWRITE07;
1118
 
1119
                --
1120
                -- stateWRITE07:
1121
                --  Write LSBYTE of data to disk (even addresses)
1122
                --   This state has two modes:
1123
                --    If memREQ is asserted we are operating normally.
1124
                --    If memREQ is negated we are writing the last 128
1125
                --     words of a 128 word operation.  Therefore we
1126
                --     write zeros.  See file header.
1127
                --
1128
 
1129
                when stateWRITE07 =>
1130
                    spiOP  <= spiTR;
1131
                    if memREQ = '1' then
1132
                        memBUF <= dmaDIN(0 to 3);
1133
                        spiTXD <= dmaDIN(4 to 11);
1134
                    else
1135
                        memBUF <= b"0000";
1136
                        spiTXD <= b"0000_0000";
1137
                    end if;
1138
                    state  <= stateWRITE08;
1139
 
1140
                --
1141
                -- stateWRITE08:
1142
                --  Write MSBYTE of data to disk (odd addresses)
1143
                --  Note:  The top 4 bits of the MSBYTE are zero.
1144
                --
1145
 
1146
                when stateWRITE08 =>
1147
                    if spiDONE = '1' then
1148
                        spiOP   <= spiTR;
1149
                        spiTXD  <= b"0000" & memBUF;
1150
                        bytecnt <= bytecnt + 1;
1151
                        state   <= stateWRITE09;
1152
                    end if;
1153
 
1154
                --
1155
                -- stateWRITE09:
1156
                --  This is the addr phase of the read cycle.
1157
                --
1158
 
1159
                when stateWRITE09 =>
1160
                    if spiDONE = '1' then
1161
                        if abort = '1' then
1162
                            memREQ  <= '0';
1163
                            spiOP   <= spiCSH;
1164
                            bytecnt <= 0;
1165
                            state   <= stateFINI;
1166
                        elsif bytecnt = 511 then
1167
                            memREQ  <= '0';
1168
                            spiOP   <= spiTR;
1169
                            spiTXD  <= x"ff";
1170
                            bytecnt <= 0;
1171
                            memADDR <= std_logic_vector(unsigned(memADDR) + 1);
1172
                            state   <= stateWRITE10;
1173
                        elsif (bytecnt = 255 and sdLEN = '1') then
1174
                            memREQ  <= '0';
1175
                            spiOP   <= spiCSH;
1176
                            bytecnt <= bytecnt + 1;
1177
                            state   <= stateWRITE06;
1178
                        else
1179
                            bytecnt <= bytecnt + 1;
1180
                            memADDR <= std_logic_vector(unsigned(memADDR) + 1);
1181
                            state   <= stateWRITE06;
1182
                        end if;
1183
                    end if;
1184
 
1185
                --
1186
                -- stateWRITE10:
1187
                --  Write CRC bytes
1188
                --
1189
 
1190
                when stateWRITE10 =>
1191
                    if spiDONE = '1' then
1192
                        if bytecnt = 0 then
1193
                            spiOP   <= spiTR;
1194
                            spiTXD  <= x"ff";
1195
                            bytecnt <= 1;
1196
                        else
1197
                            spiOP   <= spiTR;
1198
                            spiTXD  <= x"ff";
1199
                            bytecnt <= 0;
1200
                            state   <= stateWRITE11;
1201
                        end if;
1202
                    end if;
1203
 
1204
                --
1205
                -- stateWRITE11:
1206
                --  Read Data Response.  The response is is one byte long
1207
                --   and has the following format:
1208
                --
1209
                --   xxx0sss1
1210
                --
1211
                --    Where x is don't-care and sss is a 3-bit status field.
1212
                --     010 is accepted,
1213
                --     101 is rejected due to CRC error and
1214
                --     110 is rejected due to write error.
1215
                --
1216
 
1217
                when stateWRITE11 =>
1218
                    if spiDONE = '1' then
1219
                        if spiRXD(3 to 7) = b"0_010_1" then
1220
                            spiOP   <= spiTR;
1221
                            spiTXD  <= x"ff";
1222
                            bytecnt <= 0;
1223
                            state   <= stateWRITE12;
1224
                        else
1225
                            spiOP   <= spiCSH;
1226
                            val     <= spiRXD;
1227
                            err     <= x"12";
1228
                            bytecnt <= 0;
1229
                            state   <= stateRWFAIL;
1230
                        end if;
1231
                    end if;
1232
 
1233
                --
1234
                -- stateWRITE12:
1235
                --  Wait for busy token to clear.   The disk reports
1236
                --  all zeros while the write is occurring.
1237
                --
1238
 
1239
                when stateWRITE12 =>
1240
                    if spiDONE = '1' then
1241
                        if spiRXD = x"00" then
1242
                            if bytecnt = 65535 then
1243
                                spiOP   <= spiCSH;
1244
                                bytecnt <= 0;
1245
                                err     <= x"13";
1246
                                state   <= stateRWFAIL;
1247
                            else
1248
                                spiOP   <= spiTR;
1249
                                spiTXD  <= x"ff";
1250
                                bytecnt <= bytecnt + 1;
1251
                            end if;
1252
                        else
1253
                            bytecnt <= 0;
1254
                            state   <= stateWRITE13;
1255
                        end if;
1256
                    end if;
1257
 
1258
                --
1259
                -- stateWRITE13:
1260
                --  Send "Send Status" Command (CMD13)
1261
                --
1262
 
1263
                when stateWRITE13 =>
1264
                    if spiDONE = '1' or bytecnt = 0 then
1265
                        if bytecnt = 6 then
1266
                            spiOP   <= spiTR;
1267
                            spiTXD  <= x"ff";
1268
                            bytecnt <= 0;
1269
                            state   <= stateWRITE14;
1270
                        else
1271
                            spiOP   <= spiTR;
1272
                            spiTXD  <= sdCMD13(bytecnt);
1273
                            bytecnt <= bytecnt + 1;
1274
                        end if;
1275
                    end if;
1276
 
1277
                --
1278
                -- stateWRITE14:
1279
                --  Check first byte of CMD13 response
1280
                --  Status:
1281
                --   Bit 0: Zero
1282
                --   Bit 1: Parameter Error
1283
                --   Bit 2: Address Error
1284
                --   Bit 3: Erase Sequence Error
1285
                --   Bit 4: COM CRC Error
1286
                --   Bit 5: Illegal Command
1287
                --   Bit 6: Erase Reset
1288
                --   Bit 7: Idle State
1289
                --
1290
 
1291
                when stateWRITE14 =>
1292
                    if spiDONE = '1' then
1293
                        if spiRXD = x"ff" then
1294
                            if bytecnt = nCR then
1295
                                spiOP   <= spiCSH;
1296
                                bytecnt <= 0;
1297
                                err     <= x"14";
1298
                                state   <= stateRWFAIL;
1299
                            else
1300
                                spiOP   <= spiTR;
1301
                                spiTXD  <= x"ff";
1302
                                bytecnt <= bytecnt + 1;
1303
                            end if;
1304
                        else
1305
                            if spiRXD = x"00" or spiRXD = x"01" then
1306
                                spiOP   <= spiTR;
1307
                                spiTXD  <= x"ff";
1308
                                bytecnt <= 0;
1309
                                state   <= stateWRITE15;
1310
                            else
1311
                                spiOP   <= spiCSH;
1312
                                bytecnt <= 0;
1313
                                val     <= spiRXD;
1314
                                err     <= x"15";
1315
                                state   <= stateRWFAIL;
1316
                            end if;
1317
                        end if;
1318
                    end if;
1319
 
1320
                --
1321
                -- stateWRITE15:
1322
                --  Check second byte of CMD13 response
1323
                --  Status:
1324
                --   Bit 0: Out of range
1325
                --   Bit 1: Erase Param
1326
                --   Bit 2: WP Violation
1327
                --   Bit 3: ECC Error
1328
                --   Bit 4: CC Error
1329
                --   Bit 5: Error
1330
                --   Bit 6: WP Erase Skip
1331
                --   Bit 7: Card is locked
1332
                --
1333
 
1334
                when stateWRITE15 =>
1335
                    if spiDONE = '1' then
1336
                        if spiRXD = x"00" then
1337
                            spiOP   <= spiTR;
1338
                            spiTXD  <= x"ff";
1339
                            bytecnt <= 1;
1340
                            state   <= stateWRITE16;
1341
                        else
1342
                            spiOP   <= spiCSH;
1343
                            bytecnt <= 0;
1344
                            val     <= spiRXD;
1345
                            err     <= x"16";
1346
                            state   <= stateRWFAIL;
1347
                        end if;
1348
                    end if;
1349
 
1350
                --
1351
                -- stateWRITE16:
1352
                --  Send 8 clock cycles.   Pull CS High.
1353
                --
1354
 
1355
                when stateWRITE16 =>
1356
                    if spiDONE = '1' then
1357
                        spiOP   <= spiCSH;
1358
                        bytecnt <= 0;
1359
                        state   <= stateFINI;
1360
                    end if;
1361
 
1362
                --
1363
                -- stateFINI:
1364
                --  Send 8 clock cycles
1365
                --
1366
 
1367
                when stateFINI =>
1368
                    if bytecnt = 0 then
1369
                        spiOP   <= spiTR;
1370
                        spiTXD  <= x"ff";
1371
                        bytecnt <= 1;
1372
                    elsif spiDONE = '1' then
1373
                        bytecnt <= 0;
1374
                        state   <= stateDONE;
1375
                    end if;
1376
 
1377
                --
1378
                -- stateDONE:
1379
                --
1380
 
1381
                when stateDONE =>
1382
                    sdSTATE <= sdstateDONE;
1383
                    state   <= stateIDLE;
1384
 
1385
                --
1386
                -- stateINFAIL:
1387
                --  Initialization failed somehow.
1388
                --
1389
 
1390
                when stateINFAIL =>
1391
                    sdSTATE <= sdstateINFAIL;
1392
                    state   <= stateINFAIL;
1393
 
1394
                --
1395
                -- stateRWFAIL:
1396
                --  Read or Write failed somehow.
1397
                --
1398
 
1399
                when stateRWFAIL =>
1400
                    sdSTATE <= sdstateRWFAIL;
1401
                    state   <= stateRWFAIL;
1402
 
1403
            end case;
1404
 
1405
            if timeout = 0 then
1406
                state  <= stateINFAIL;
1407
            end if;
1408
 
1409
        end if;
1410
    end process SD_STATE;
1411
 
1412
    --
1413
    --! SDSPI Instance
1414
    --
1415
 
1416
    iSDSPI : entity work.eSDSPI (rtl) port map (
1417
        sys     => sys,
1418
        spiOP   => spiOP,
1419
        spiTXD  => spiTXD,
1420
        spiRXD  => spiRXD,
1421
        spiMISO => sdMISO,
1422
        spiMOSI => sdMOSI,
1423
        spiSCLK => sdSCLK,
1424
        spiCS   => sdCS,
1425
        spiDONE => spiDONE
1426
    );
1427
 
1428
    with state select
1429
        sdSTAT.debug <= -- Initialization
1430
                        b"0000_0000" when stateINIT00,
1431
                        b"0000_0001" when stateINIT01,
1432
                        b"0000_0010" when stateINIT02,
1433
                        b"0000_0011" when stateINIT03,
1434
                        b"0000_0100" when stateINIT04,
1435
                        b"0000_0101" when stateINIT05,
1436
                        b"0000_0110" when stateINIT06,
1437
                        b"0000_0111" when stateINIT07,
1438
                        b"0000_1000" when stateINIT08,
1439
                        b"0000_1001" when stateINIT09,
1440
                        b"0000_1010" when stateINIT10,
1441
                        b"0000_1011" when stateINIT11,
1442
                        b"0000_1100" when stateINIT12,
1443
                        b"0000_1101" when stateINIT13,
1444
                        b"0000_1110" when stateINIT14,
1445
                        b"0000_1111" when stateINIT15,
1446
                        b"0001_0000" when stateINIT16,
1447
                        b"0001_0001" when stateINIT17,
1448
                        -- Read states
1449
                        b"0010_0000" when stateREAD00,
1450
                        b"0010_0001" when stateREAD01,
1451
                        b"0010_0010" when stateREAD02,
1452
                        b"0010_0011" when stateREAD03,
1453
                        b"0010_0100" when stateREAD04,
1454
                        b"0010_0101" when stateREAD05,
1455
                        b"0010_0110" when stateREAD06,
1456
                        b"0010_0110" when stateREAD07,
1457
                        b"0010_0110" when stateREAD08,
1458
                        b"0010_0110" when stateREAD09,
1459
                        -- Write states
1460
                        b"0011_0000" when stateWRITE00,
1461
                        b"0011_0001" when stateWRITE01,
1462
                        b"0011_0010" when stateWRITE02,
1463
                        b"0011_0011" when stateWRITE03,
1464
                        b"0011_0100" when stateWRITE04,
1465
                        b"0011_0101" when stateWRITE05,
1466
                        b"0011_0110" when stateWRITE06,
1467
                        b"0011_0111" when stateWRITE07,
1468
                        b"0011_1000" when stateWRITE08,
1469
                        b"0011_1001" when stateWRITE09,
1470
                        b"0011_1010" when stateWRITE10,
1471
                        b"0011_1010" when stateWRITE11,
1472
                        b"0011_1010" when stateWRITE12,
1473
                        b"0011_1010" when stateWRITE13,
1474
                        b"0011_1010" when stateWRITE14,
1475
                        b"0011_1010" when stateWRITE15,
1476
                        b"0011_1010" when stateWRITE16,
1477
                        -- Other states
1478
                        b"1111_0000" when stateRESET,
1479
                        b"1111_0001" when stateIDLE,
1480
                        b"1111_0010" when stateINFAIL,
1481
                        b"1111_0011" when stateRWFAIL,
1482
                        b"1111_0100" when others;
1483
 
1484
    dmaADDR       <= memADDR;
1485
    dmaREQ        <= memREQ;
1486
    sdSTAT.err    <= err;
1487
    sdSTAT.val    <= val;
1488
    sdSTAT.rdCNT  <= rdCNT;
1489
    sdSTAT.wrCNT  <= wrCNT;
1490
    sdSTAT.state  <= sdSTATE;
1491
 
1492
end rtl;

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