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[/] [pdp8/] [trunk/] [pdp8/] [uart/] [uart_tx.vhd] - Blame information for rev 2

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--------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--!      KL8E Generic UART Transmitter
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--!
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--! \details
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--!      The UART Transmitter is hard configured for:
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--!      - 8 data bits
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--!      - no parity
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--!      - 1 stop bit
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--!
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--!      To transmit a word of data, provide the data on the data
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--!      bus and assert the 'load' input for a clock cycle.  When
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--!      the data is sent, the 'intr' output will be asserted for
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--!      a single clock cycle.
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--!
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--! \note
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--!      This UART primitive transmitter is kept simple
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--!      intentionally and is therefore unbuffered.  If you
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--!      require a double buffered UART, then you will need to
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--!      layer a set of buffers on top of this device.
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--!
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--! \file
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--!      uart_tx.vhd
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--!
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--! \author
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--!      Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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--  Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee;                                   --! IEEE Library
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use ieee.std_logic_1164.all;                    --! IEEE 1164
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use work.uart_types.all;                        --! UART Types
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use work.cpu_types.all;                         --! CPU Types
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--
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--! KL8E Generic UART Transmitter Entity
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--
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entity eUART_TX is port (
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    sys   : in  sys_t;                          --! Clock/Reset
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    clkBR : in  std_logic;                      --! Clock Enable (for Baud Rate)
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    data  : in  ascii_t;                        --! Data Input
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    load  : in  std_logic;                      --! Load Data
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    intr  : out std_logic;                      --! Interrupt
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    txd   : out std_logic                       --! Serial Data Out
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);
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end eUART_TX;
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--
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--! KL8E Generic UART Transmitter RTL
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--
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architecture rtl of eUART_TX is
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    type   state_t is (stateIdle,               --! Idle
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                       stateStart,              --! Working on Start Bit
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                       stateBit0,               --! Working on Bit 0
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                       stateBit1,               --! Working on Bit 1
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                       stateBit2,               --! Working on Bit 2
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                       stateBit3,               --! Working on Bit 3
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                       stateBit4,               --! Working on Bit 4
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                       stateBit5,               --! Working on Bit 5
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                       stateBit6,               --! Working on Bit 6
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                       stateBit7,               --! Working on Bit 7
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                       stateStop1,              --! Working on Stop Bit
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                       stateDone);              --! Generate Interrupt
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    signal state   : state_t;                   --! Transmitter State
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    signal txReg   : ascii_t;                   --! Transmitter Register
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begin
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    --
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    --! UART Transmitter:
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    --!
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    --!  The clkBR is 16 clocks per bit.  The UART transmits LSB first.
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    --! 
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    --!  When the load input is asserted, the data is loaded into the
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    --!  Transmit Register and the state machine is started.
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    --!
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    --!  Once the state machine is started, it proceeds as follows:
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    --!   -# Send Start Bit, then
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    --!   -# Send bit 7 (LSB)
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    --!   -# Send bit 6
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    --!   -# Send bit 5
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    --!   -# Send bit 4
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    --!   -# Send bit 3
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    --!   -# Send bit 2
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    --!   -# Send bit 1
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    --!   -# Send bit 0 (MSB)
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    --!   -# Send Stop Bit 1
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    --!   -# Send Stop Bit 2
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    --!   -# Trigger Interrupt output
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    --
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    UARTTX : process(sys)
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        variable brdiv : integer range 0 to 15;
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    begin
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        if sys.rst = '1' then
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            brdiv := 0;
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            txReg <= (others => '0');
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            state <= stateIdle;
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        elsif rising_edge(sys.clk) then
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            case state is
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                --
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                -- Transmitter is sitting idle
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                --
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                when stateIdle =>
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                    if load = '1' then
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                        brdiv := 15;
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                        txReg <= data;
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                        state <= stateStart;
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                    end if;
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                --
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                -- Sending Start Bit
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                --
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                when stateStart =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit7;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 7 (LSB)
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                --
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                when stateBit7 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit6;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 6
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                --
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                when stateBit6 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit5;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 5
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                --
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                when stateBit5 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit4;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 4
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                --
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                when stateBit4 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit3;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 3
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                --
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                when stateBit3 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit2;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 2
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                --
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                when stateBit2 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit1;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 1
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                --
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                when stateBit1 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateBit0;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit 0
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                --
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                when stateBit0 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateStop1;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Sending Bit Stop Bit 1
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                --
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                when stateStop1 =>
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                    if clkBR = '1' then
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                        if brdiv = 0 then
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                            brdiv := 15;
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                            state <= stateDone;
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                        else
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                            brdiv := brdiv - 1;
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                        end if;
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                    end if;
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                --
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                -- Done State.  Trigger Interrupt output.
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                --
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                when stateDone =>
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                    state <= stateIdle;
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            end case;
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        end if;
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    end process UARTTX;
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    --
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    -- Data selector for TXD
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    --
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    with state select
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        txd <= '1'      when stateIdle,
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               '0'      when stateStart,
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               txReg(7) when stateBit7,
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               txReg(6) when stateBit6,
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               txReg(5) when stateBit5,
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               txReg(4) when stateBit4,
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               txReg(3) when stateBit3,
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               txReg(2) when stateBit2,
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               txReg(1) when stateBit1,
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               txReg(0) when stateBit0,
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               '1'      when stateStop1,
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               '1'      when others;
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319
    --
320
    -- Interrupt
321
    --
322
 
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    intr <= '1' when state = stateDone else '0';
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end rtl;

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