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unicore |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// FFT/IFFT 128 points transform ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// DESCRIPTION : Normalization unit
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// FUNCTION: shifting left up to 3 bits
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// FILES: CNORM.v
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// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT
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// 2) Is registered
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// 3) Overflow detector detects the overflow event
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// by the given shift condition. The detector is zeroed by the START signal
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// 4) RDY is the START signal delayed to a single clock cycle
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// File :
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// Generated :
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//
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// Description :
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//
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//-----------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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`include "FFT128_CONFIG.inc"
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module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI );
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`FFT128paramnb
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output OVF ;
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reg OVF ;
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output RDY ;
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reg RDY ;
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output [nb+1:0] DOR ;
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wire [nb+1:0] DOR ;
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output [nb+1:0] DOI ;
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wire [nb+1:0] DOI ;
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input CLK ;
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wire CLK ;
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input ED ;
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wire ED ;
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input START ;
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wire START ;
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input [nb+2:0] DR ;
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wire [nb+2:0] DR ;
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input [nb+2:0] DI ;
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wire [nb+2:0] DI ;
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input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits
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wire [1:0] SHIFT ;
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wire signed [nb+3:0] diri,diii;
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assign diri = DR << SHIFT;
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assign diii = DI << SHIFT;
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reg [nb+2:0] dir,dii;
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`ifdef FFT128round //rounding
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always @( posedge CLK ) begin
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if (ED) begin
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if (diri[nb+2] && ~diri[0]) // <0 with LSB=00
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dir<=diri;
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else dir<=diri+2;
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if (diii[nb+2] && ~diii[0])
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dii<=diii;
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else dii<=diii+2;
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end
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end
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`else //truncation
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always @( posedge CLK ) begin
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if (ED) begin
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dir<=diri;
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dii<=diii;
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end
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end
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`endif
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always @( posedge CLK ) begin
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if (ED) begin
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RDY<=START;
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if (START)
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OVF<=0;
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else
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case (SHIFT)
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2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]);
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2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) ||
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(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
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2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])||
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(DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) ||
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(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
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endcase
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end
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end
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assign DOR= dir[nb+3:2];
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assign DOI= dii[nb+3:2];
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endmodule
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