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module tests;
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reg clk,rst;
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wire processor_out;
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single_cycle_microprocessor s1(processor_out , clk , rst );
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                // Emulate the master clock oscillator
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always #5 clk = ~clk;
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// Emulate the power-on reset, and initialize the clock
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initial begin
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        clk = 0;
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        rst = 1;
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        #10 rst = 0;
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end
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endmodule
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module single_cycle_microprocessor (processor_out , clk , rst );
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output [31:0] processor_out;
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input clk , rst;
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wire [31:0] pc_out,add4_out,instruction;
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wire [3:0] frm_pc;
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wire [5:0] opcode;
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wire [4:0] Rs , Rt , Rd , mux1_out;
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wire [15:0] Imm;
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wire [5:0] FC;
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wire [1:0] ALUOP;
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wire [31:0] regA_out,regB_out,mux2_out;
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wire [2:0] Operation;
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wire [31:0] sign_out,sh_left_out,add_out,mux3_out ;
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wire [31:0] ALU_OUT,data_out,mux4_out;
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wire [3:0] ALU_Out_Adress;
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wire PCSrc;
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wire Branch , ALU_zero;
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assign frm_pc = pc_out[5:2];
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assign Rs = instruction[25:21];
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assign Rt = instruction[20:16];
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assign Rd = instruction[15:11];
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assign opcode = instruction[31:26];
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assign Imm = instruction[15:0];
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assign  FC = Imm[5:0];
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assign ALU_Out_Adress = ALU_OUT[5:2];
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assign PCSrc = Branch & ALU_zero;
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assign processor_out=mux4_out;
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pc  PC(.out(pc_out) , .in(mux3_out) ,.clk(clk), .rst(rst));
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add_4   ADD_4(.out(add4_out) , .in(pc_out));
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instruction_memory  INST_MEM ( .data_out(instruction) , .address(frm_pc)) ;
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mux_5to1  MUX_1(.out(mux1_out),.a(Rt),.b(Rd),.sel(RegDST));
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Control  CONTROL(.RegDST(RegDST) , .Branch(Branch) , .MemRead(MemRead) , .MemtoReg(MemtoReg) ,.ALUOP(ALUOP) ,.MemWrite(MemWrite) ,.ALUSrc(ALUSrc) ,.RegWrite(RegWrite) ,.op(opcode) );
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register_file REGISTER(.data_out1(regA_out),.data_out2(regB_out),.data_in(mux4_out),.wr(mux1_out),.wr_enable(RegWrite),.rd1(Rs),.rd2(Rt),.clk(clk),.rst(rst));
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Sign_Ext  SIGN_EXT(.out (sign_out)  , .in(Imm) );
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mux_32to1  MUX_2(.out(mux2_out),.a(regB_out),.b(sign_out),.sel(ALUSrc));
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ALU_Control  ALU_CONTROL(.Operation(Operation), .F(FC), .ALUop(ALUOP));
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ALU  ALU_32bit( .OUT(ALU_OUT) ,.ALU_zero( ALU_zero) , .A(regA_out),.B(mux2_out) , .ALU_Control(Operation) );
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shift_left2  Shift_Left_2(.out(sh_left_out) , .in(sign_out)) ;
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add  ADD_32bit(.out(add_out),.a(add4_out),.b(sh_left_out));
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mux_32to1  MUX_3(.out(mux3_out), .a(add4_out),.b(add_out),.sel(PCSrc));
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data_memory   DATA_MEM(.data_out( data_out) ,.address( ALU_Out_Adress) ,.data_in(regB_out) ,.wr(MemWrite),.clk(clk) ) ;
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mux_32to1  MUX_4(.out(mux4_out),.a(ALU_OUT),.b(data_out),.sel(MemtoReg));
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endmodule
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/*
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This code is for 4 bit I/O. convert it to 32 I/O.
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*/
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module add (out,a,b);
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output [31:0] out;
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input [31:0] a,b;
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103
assign out=a+b;
104
endmodule
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/*
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This code is for 4 bit I/O. convert it to 32 I/O.
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*/
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module add_4  (out , in);
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output  [31:0] out;
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input   [31:0] in;
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assign out= in + 4;
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endmodule
116
 
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    module ALU ( OUT , ALU_zero ,  A , B , ALU_Control );
120
 
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    output [31:0] OUT ;
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    output        ALU_zero ;
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    input  [31:0] A , B;
124
    input  [2:0]  ALU_Control ;
125
 
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    reg    [31:0] OUT;
127
 
128
    assign ALU_zero  = ~ ( | OUT ) ;  // ALU_zero = 1  when  OUT =0 ;
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130
    wire   [31:0] DIFF = A - B ;
131
 
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    always @ ( A or B or ALU_Control or DIFF)
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134
    case(ALU_Control)
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    3'b000 :     OUT = A & B  ;
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    3'b001 :     OUT = A | B  ;
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    3'b010 :     OUT = A + B  ;
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    3'b110 :     OUT = DIFF  ;
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    3'b111 :     OUT = { {31{1'b0}} , DIFF[31] } ; // OUT  =00...001 when A < B 
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    ///3'b111 for slt instruction                  // DIFF[31] =1    when A < B
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    default :    OUT = 32'hxxxxxxxx ;
143
    endcase
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145
    endmodule
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/*
167
This code is for 4*4 data_memory. convert it to 16*32 data_memory.
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*/
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module data_memory ( data_out , address,data_in ,wr,clk ) ;
170
output [31:0] data_out;
171
input [31:0] data_in;
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input [3:0] address;
173
input wr,clk;
174
 
175
reg [31:0] data_mem [15:0];
176
 
177
assign data_out=data_mem[address];
178
 
179
always @ (posedge clk )
180
if (wr==1)
181
data_mem[address]=data_in;
182
 
183
endmodule
184
 
185
/*
186
This code is for 4*4 instruction_memory. convert it to 16*32 instruction_memory.
187
*/
188
 
189
module instruction_memory ( data_out , address) ;
190
output [31:0] data_out ;
191
reg [31:0] data_out ;
192
 
193
input [3:0] address ;
194
wire [3:0] address ;
195
 
196
//}} End of automatically maintained section
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always@( address )
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case(address)
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0:  data_out=32'h20010004;
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1:  data_out=32'h20020008;
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2:  data_out=32'h00411820;
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3:  data_out=32'h00622022;
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4:  data_out=32'h0083282a;
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5:  data_out=32'hac020004;
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6:  data_out=32'h8c020004;
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7:  data_out=32'h00000000;
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8:  data_out=32'h00000000;
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9:  data_out=32'h00000000;
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10:  data_out=32'h00000000;
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11:  data_out=32'h00000000;
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12:  data_out=32'h00000000;
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13:  data_out=32'h00000000;
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14:  data_out=32'h00000000;
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15:  data_out=32'h00000000;
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endcase
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endmodule
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/*
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This code is for 4 bit instruction lines. convert them to 32 bit instruction lines.
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*/
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module mux_32to1(out, a,b,sel);
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output [31:0] out;
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input [31:0] a,b;
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input sel;
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reg [31:0] out;
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always @ (sel or a or b)
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  if(sel==0)
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  out = a;
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  else
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  out = b;
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endmodule
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module mux_5to1(out, a,b,sel);
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output [4:0] out;
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input [4:0] a,b;
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input sel;
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reg [4:0] out;
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always @ (sel or a or b)
240
  if(sel==0)
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  out = a;
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  else
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  out = b;
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endmodule
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/*
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This code is for 4 bit I/O. convert it to 32 I/O.
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*/
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module pc (out , in ,clk, rst);
251
output [31:0] out;
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input [31:0] in;
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input clk,rst;
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reg [31:0]out;
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always @ (posedge clk or posedge rst)
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  if(rst==1)
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  out = 0;
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  else
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  out = in;
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endmodule
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/*
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This code is for 4*4 register file. convert it to 32*32 register file.
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*/
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module register_file (data_out1,data_out2,data_in,wr,wr_enable,rd1,rd2,clk,rst);
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output [31:0] data_out1,data_out2;
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input [31:0] data_in;
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input [4:0] wr,rd1,rd2;
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input wr_enable,clk,rst;
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reg [31:0] registers [31:0];
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wire [31:0] R0 = registers[0],
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            R1 = registers[1],
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            R2 = registers[2],
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            R3 = registers[3],
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            R4 = registers[4],
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            R5 = registers[5],
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            R6 = registers[6];
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assign data_out1=registers[rd1];
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assign data_out2=registers[rd2];
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integer i;
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always@(posedge clk  or posedge rst)
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if(rst==1) begin for(i=0;i<=31;i=i+1) registers[i]<=0;end
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else if (wr_enable==1)
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registers[wr]<=data_in;
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initial begin
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registers[0] = 0;
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registers[1] = 4;
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registers[2] = 8;
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registers[3] = 2;
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end
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295
endmodule
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/*
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This code is for 16 bit I/O. convert it to 32 bit I/O.
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*/
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module shift_left2( out , in) ;
301
output [31:0] out;
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input [31:0] in;
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304
assign out=in << 2;
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endmodule
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module Sign_Ext (out  , in );
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output [31:0] out;
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input [15:0] in;
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assign out = { {16{in[15]}} , in[15:0] };
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endmodule
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module ALU_Control(Operation, F, ALUop);
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    output [2:0] Operation;
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    input  [5:0] F;
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    input  [1:0] ALUop;
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    assign Operation[2] = (F[1] & ALUop[1]) | (ALUop[0]);
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    assign Operation[1] =  (~ALUop[1]) | (~F[2]);
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    assign Operation[0] = (F[3] | F[0]) & (ALUop[1]);
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// use   always  block  or  assign  statements   
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// only  3  statements   are  required   
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endmodule
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 module  Control (      RegDST ,
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                        Branch    ,
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                        MemRead   ,
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                        MemtoReg  ,
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                        ALUOP ,
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                        MemWrite  ,
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                        ALUSrc    ,
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                        RegWrite  ,
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                        op );
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 output          RegDST,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch;
348
output[1:0]     ALUOP;
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input [5:0]     op ;
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351
wire r_format,lw,sw,beq,addi;
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assign r_format  =(~op[5] ) & (~op[4] ) & (~op[3] ) & (~op[2] ) & (~op[1]) &(~op[0] ) ;
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assign lw        =(op[5] )  & (~op[4] ) & (~op[3] ) & (~op[2] ) & (op[1] ) &(op[0] ) ;
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assign sw        =(op[5] ) & (~op[4] ) & (op[3] ) & (~op[2] ) & (op[1]) &(op[0] ) ;
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assign beq       =(~op[5] ) & (~op[4] ) & (~op[3] ) & (op[2] ) & (~op[1]) &(~op[0] ) ;
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assign addi      =(~op[5] ) & (~op[4] ) & (op[3] ) & (~op[2] )  & (~op[1]) &(~op[0] ) ;
358
assign          RegDST=r_format,
359
                ALUSrc= (lw)|(sw)|(addi),
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                MemtoReg=lw,
361
                RegWrite=r_format|lw|addi,
362
                MemRead= lw      ,
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                MemWrite=sw      ,
364
                Branch=beq;
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366
assign  ALUOP[1]=r_format;
367
assign  ALUOP[0]=beq ;
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   endmodule

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