OpenCores
URL https://opencores.org/ocsvn/ram_wb/ram_wb/trunk

Subversion Repositories ram_wb

[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [Makefile] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 unneback
ACTEL:
2
        vppp +define+RAM_WB_DAT_WIDTH+32 +define+RAM_WB_ADR_WIDTH+11 +define+RAM_WB_MEM_SIZE+2048 --simple ram_wb_sc_dw.v > ram_wb_sc_dw_32x2048.v
3
        vppp +define+RAM_WB_DAT_WIDTH+32 +define+RAM_WB_ADR_WIDTH+10 +define+RAM_WB_MEM_SIZE+1024 --simple ram_wb_sc_dw.v > ram_wb_sc_dw_32x1024.v
4
 
5
all: ACTEL

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.