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[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [ram_wb_sc_dw_wrapper.v] - Blame information for rev 8

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1 7 unneback
// wrapper for the above dual port RAM
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module ram (dat_i, dat_o, adr_i, we_i, clk );
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   parameter dat_width = 32;
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   parameter adr_width = 11;
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   parameter mem_size  = 2048;
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   input [dat_width-1:0]      dat_i;
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   input [adr_width-1:0]      adr_i;
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   input                      we_i;
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   output [dat_width-1:0]     dat_o;
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   input                      clk;
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   wire [dat_width-1:0]       q_b;
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   ram_sc_dw
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     /*
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     #
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     (
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      .dat_width(dat_width),
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      .adr_width(adr_width),
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      .mem_size(mem_size)
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      )
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      */
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     ram0
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     (
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      .d_a(dat_i),
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      .q_a(dat_o),
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      .adr_a(adr_i),
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      .we_a(we_i),
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      .q_b(q_b),
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      .adr_b({adr_width{1'b0}}),
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      .d_b({dat_width{1'b0}}),
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      .we_b(1'b0),
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      .clk(clk)
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      );
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endmodule // ram

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