OpenCores
URL https://opencores.org/ocsvn/ram_wb/ram_wb/trunk

Subversion Repositories ram_wb

[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [wb_ram_sc_sw.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 unneback
module ram (dat_i, dat_o, adr_i, we_i, clk );
2
 
3
   parameter dat_width = 32;
4
   parameter adr_width = 11;
5
   parameter mem_size  = 2048;
6
 
7
   input [dat_width-1:0]      dat_i;
8
   input [adr_width-1:0]      adr_i;
9
   input                      we_i;
10
   output reg [dat_width-1:0] dat_o;
11
   input                      clk;
12
 
13
   reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */;
14
 
15
   always @ (posedge clk)
16
     begin
17
        dat_o <= ram[adr_i];
18
        if (we_i)
19
          ram[adr_i] <= dat_i;
20
     end
21
 
22
endmodule // ram

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.