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--! @file memblock.vhd
--! @brief Bloque de memoria.
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity memblock is
        generic (
 
                blocksize : integer := 512;
 
                external_readable_widthad       : integer := 3;
                external_writeable_widthad      : integer := 4
        );
        port (
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
                instrfifo_rd : in std_logic;
                resultfifo_wr: in std_logic_vector(8-1 downto 0);
                instrfifo_empty: out std_logic;
                ext_rd,ext_wr: in std_logic;
                ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
                ext_rd_add : in std_logic_vector(2 downto 0);
                ext_d: in std_logic_vector(floatwidth-1 downto 0);
                resultfifo_full  : out std_logic_vector(3 downto 0);
                int_d : in vectorblock08;
 
                --!Python
                ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
                int_q : out vectorblock12;
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
                dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
                dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
        );
end entity;
 
architecture memblock_arch of memblock is
 
 
 
 
 
        --!TXBXSTART:MEMBLOCK_EXTERNAL_WRITE
        signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La se&ntilde;al extra es para la escritura de la cola de instrucciones.
        signal s0ext_wr_add                     : std_logic_vector(4+widthadmemblock-1 downto 0);
        signal s0ext_wr                         : std_logic;
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
        --!TBXEND
        --! Se&ntilde;al de soporte
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
 
        --!TXBXSTART:MEMBLOCK_EXTERNAL_READ
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
        signal s0ext_rd                         : std_logic;
        signal s0ext_rd_ack                     : std_logic_vector(8-1 downto 0);
        signal s0ext_q                          : vectorblock08;
        --!TBXEND
        --! Se&ntilde;al de soporte
        signal s0ext_rd_add_choice      : std_logic_vector(3 downto 0);
 
 
        --!TBXSTART:MEMBLOCK_INTERNAL_READ
        signal sint_rd_add                      : vectorblockadd02;
        signal s1int_q                          : vectorblock12;
        --!TBXEND
 
        --!TXBXSTART:MEMBLOCK_INTERNAL_WRITE
        signal sint_d                           : vectorblock08;
        signal sresultfifo_full         : std_logic_vector(7 downto 0);
        --!TBXEND
 
begin
 
        --! Cola interna de producto cccccpunto, ubicada entre el pipe line aritm&eacute;co. 
        q0q1 : scfifo --! Debe ir registrada la salida.
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "CycloneIII",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 8,
                lpm_numwords                    => 8,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 64,
                lpm_widthu                              => 3,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => dpfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => dpfifo_q,
                wrreq           => dpfifo_wr,
                data            => dpfifo_d
        );
 
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
        qxqyqz : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCFIFO",
                lpm_width                               => 96,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => normfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => normfifo_q,
                wrreq           => normfifo_wr,
                data            => normfifo_d,
                almost_full => open,
                full            => open
        );
 
        --! Cola de instrucciones 
        qi : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 32,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => instrfifo_rd,
                aclr            => '0',
                empty           => instrfifo_empty,
                clock           => clk,
                q                       => instrfifo_q,
                wrreq           => s0ext_wr_add_one_hot(12),
                data            => s0ext_d,
                almost_full => open
        );
 
        --! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
        sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
        sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
 
        --! Instanciaci&oacute;n de la cola de resultados de salida.
        int_q <= s1int_q;
        operands_blocks:
        for i in 11 downto 0 generate
                --!int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
                operandsblock : altsyncram
                generic map (
                        address_aclr_b                                          => "NONE",
                        address_reg_b                                           => "CLOCK0",
                        clock_enable_input_a                            => "BYPASS",
                        clock_enable_input_b                            => "BYPASS",
                        clock_enable_output_b                           => "BYPASS",
                        intended_device_family                          => "Cyclone III",
                        lpm_type                                                        => "altsyncram",
                        numwords_a                                                      => 2**widthadmemblock,
                        numwords_b                                                      => 2**widthadmemblock,
                        operation_mode                                          => "DUAL_PORT",
                        outdata_aclr_b                                          => "NONE",
                        outdata_reg_b                                           => "CLOCK0",
                        power_up_uninitialized                          => "FALSE",
                        ram_block_type                                          => "M9K",
                        rdcontrol_reg_b                                         => "CLOCK0",
                        read_during_write_mode_mixed_ports      => "OLD_DATA",
                        widthad_a                                                       => widthadmemblock,
                        widthad_b                                                       => widthadmemblock,
                        width_a                                                         => floatwidth,
                        width_b                                                         => floatwidth,
                        width_byteena_a                                         => 1
                )
                port map (
                        wren_a          => s0ext_wr_add_one_hot(i),
                        clock0          => clk,
                        address_a       => s0ext_wr_add(widthadmemblock-1 downto 0),
                        address_b       => sint_rd_add((i/3) mod 2),
                        rden_b          => '1',
                        q_b                     => s1int_q(i),
                        data_a          => s0ext_d
                );
        end generate operands_blocks;
 
        --! Instanciaci&oacute;n de la cola de resultados.
        resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
        resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
        resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
        resultfifo_full(0) <= sresultfifo_full(0);
        sint_d <= int_d;
        results_blocks:
        for i in 7 downto 0 generate
                resultsfifo : scfifo
                generic map     (
                        add_ram_output_register => "OFF",
                        almost_full_value               => 480,
                        allow_rwcycle_when_full => "OFF",
                        intended_device_family  => "Cyclone III",
                        lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                        lpm_numwords                    => 512,
                        lpm_showahead                   => "ON",
                        lpm_type                                => "SCIFIFO",
                        lpm_width                               => 32,
                        lpm_widthu                              => 9,
                        overflow_checking               => "ON",
                        underflow_checking              => "ON",
                        use_eab                                 => "ON"
                )
                port    map (
                        rdreq           => s0ext_rd_ack(i),
                        aclr            => '0',
                        empty           => open,
                        clock           => clk,
                        q                       => s0ext_q(i),
                        wrreq           => resultfifo_wr(i),
                        data            => sint_d(i),
                        almost_full     => sresultfifo_full(i),
                        full            => open
                );
        end generate results_blocks;
 
        --! Escritura en registros de operandos de entrada.
        operands_block_proc: process (clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_wr_add    <= (others => '0');
                        s0ext_wr                <= '0';
                        s0ext_d                 <= (others => '0');
                elsif clk'event and clk='1' then
                        --! Registro de entrada
                        s0ext_wr_add <= ext_wr_add;
                        s0ext_wr  <= ext_wr;
                        s0ext_d  <= ext_d;
                end if;
        end process;
 
        --! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
        s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);
        operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
        begin
 
                --! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
                --! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
                case s0ext_wr_add_choice is
                        when "0000" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
                        when x"1" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
                        when x"2" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
                        when x"4" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
                        when x"5" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
                        when x"6" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
                        when x"8" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
                        when x"9" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
                        when x"A" =>
                                s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
                        when x"C" =>
                                s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
                        when x"D" =>
                                s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
                        when x"E" =>
                                s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
                        when others =>
                                s0ext_wr_add_one_hot <= s0ext_wr&x"000";
                end case;
 
        end process;
 
        --! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac. 
        s0ext_rd_add_choice <= '0'&s0ext_rd_add;
        results_block_proc: process(clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_rd_add    <= (others => '0');
                        s0ext_rd                <= '0';
                elsif clk'event and clk='1' then
                        --!Registrar entrada
                        s0ext_rd_add    <= ext_rd_add;
                        s0ext_rd                <= ext_rd;
                        --!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
                        case s0ext_rd_add_choice is
                                when x"0" => ext_q <= s0ext_q(0);
                                when x"1" => ext_q <= s0ext_q(1);
                                when x"2" => ext_q <= s0ext_q(2);
                                when x"3" => ext_q <= s0ext_q(3);
                                when x"4" => ext_q <= s0ext_q(4);
                                when x"5" => ext_q <= s0ext_q(5);
                                when x"6" => ext_q <= s0ext_q(6);
                                when others => ext_q <= s0ext_q(7);
                        end case;
                end if;
        end process;
 
        --! rdack decoder para las colas de resultados de salida.
        results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)
        begin
                case s0ext_rd_add_choice is
                        when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
                        when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
                        when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
                        when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
                        when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
                        when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
                        when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
                        when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
                end case;
        end process;
end architecture;
 

Line No.	Rev	Author	Line
1	150	jguarin200	`--! @file memblock.vhd`
2	152	jguarin200	`--! @brief Bloque de memoria.`
3	128	jguarin200	`--! @author Julián Andrés Guarín Reyes`
4			`--------------------------------------------------------------`
5			`-- RAYTRAC`
6			`-- Author Julian Andres Guarin`
7			`-- memblock.vhd`
8			`-- This file is part of raytrac.`
9			`--`
10			`-- raytrac is free software: you can redistribute it and/or modify`
11			`-- it under the terms of the GNU General Public License as published by`
12			`-- the Free Software Foundation, either version 3 of the License, or`
13			`-- (at your option) any later version.`
14			`--`
15			`-- raytrac is distributed in the hope that it will be useful,`
16			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`-- GNU General Public License for more details.`
19			`--`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
22
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25	151	jguarin200	`use work.arithpack.all;`
26	129	jguarin200
27	128	jguarin200	`entity memblock is`
28			`generic (`
29	129	jguarin200
30			`blocksize : integer := 512;`
31	152	jguarin200
32	129	jguarin200	`external_readable_widthad : integer := 3;`
33			`external_writeable_widthad : integer := 4`
34	128	jguarin200	`);`
35			`port (`
36
37	147	jguarin200	`clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;`
38	150	jguarin200	`instrfifo_rd : in std_logic;`
39	158	jguarin200	`resultfifo_wr: in std_logic_vector(8-1 downto 0);`
40	147	jguarin200	`instrfifo_empty: out std_logic;`
41	138	jguarin200	`ext_rd,ext_wr: in std_logic;`
42	158	jguarin200	`ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);`
43	157	jguarin200	`ext_rd_add : in std_logic_vector(2 downto 0);`
44	152	jguarin200	`ext_d: in std_logic_vector(floatwidth-1 downto 0);`
45	150	jguarin200	`resultfifo_full : out std_logic_vector(3 downto 0);`
46	158	jguarin200	`int_d : in vectorblock08;`
47	152	jguarin200
48			`--!Python`
49	153	jguarin200	`ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);`
50	158	jguarin200	`int_q : out vectorblock12;`
51	130	jguarin200	`int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);`
52	152	jguarin200	`dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);`
53			`normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);`
54			`dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);`
55			`normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)`
56	128	jguarin200	`);`
57	153	jguarin200	`end entity;`
58	128	jguarin200
59			`architecture memblock_arch of memblock is`
60
61	129	jguarin200
62
63	147	jguarin200
64	151	jguarin200
65	161	jguarin200	`--!TXBXSTART:MEMBLOCK_EXTERNAL_WRITE`
66	158	jguarin200	`signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.`
67			`signal s0ext_wr_add : std_logic_vector(4+widthadmemblock-1 downto 0);`
68	152	jguarin200	`signal s0ext_wr : std_logic;`
69			`signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);`
70			`--!TBXEND`
71	157	jguarin200	`--! Señal de soporte`
72			`signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);`
73	152	jguarin200
74	160	jguarin200	`--!TXBXSTART:MEMBLOCK_EXTERNAL_READ`
75	157	jguarin200	`signal s0ext_rd_add : std_logic_vector(2 downto 0);`
76	152	jguarin200	`signal s0ext_rd : std_logic;`
77	158	jguarin200	`signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);`
78	152	jguarin200	`signal s0ext_q : vectorblock08;`
79			`--!TBXEND`
80	157	jguarin200	`--! Señal de soporte`
81			`signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);`
82	152	jguarin200
83	157	jguarin200
84	152	jguarin200	`--!TBXSTART:MEMBLOCK_INTERNAL_READ`
85			`signal sint_rd_add : vectorblockadd02;`
86	138	jguarin200	`signal s1int_q : vectorblock12;`
87	152	jguarin200	`--!TBXEND`
88
89	160	jguarin200	`--!TXBXSTART:MEMBLOCK_INTERNAL_WRITE`
90	152	jguarin200	`signal sint_d : vectorblock08;`
91	150	jguarin200	`signal sresultfifo_full : std_logic_vector(7 downto 0);`
92	152	jguarin200	`--!TBXEND`
93	130	jguarin200
94	128	jguarin200	`begin`
95
96	152	jguarin200	`--! Cola interna de producto cccccpunto, ubicada entre el pipe line aritméco.`
97	140	jguarin200	`q0q1 : scfifo --! Debe ir registrada la salida.`
98	147	jguarin200	`generic map (`
99			`add_ram_output_register => "OFF",`
100	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
101	147	jguarin200	`intended_device_family => "CycloneIII",`
102			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
103			`almost_full_value => 8,`
104			`lpm_numwords => 8,`
105			`lpm_showahead => "ON",`
106			`lpm_type => "SCIFIFO",`
107			`lpm_width => 64,`
108			`lpm_widthu => 3,`
109			`overflow_checking => "ON",`
110			`underflow_checking => "ON",`
111			`use_eab => "ON"`
112			`)`
113			`port map (`
114			`rdreq => dpfifo_rd,`
115			`aclr => '0',`
116			`empty => open,`
117			`clock => clk,`
118			`q => dpfifo_q,`
119			`wrreq => dpfifo_wr,`
120			`data => dpfifo_d`
121			`);`
122	140	jguarin200
123	152	jguarin200	`--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético`
124	140	jguarin200	`qxqyqz : scfifo`
125	147	jguarin200	`generic map (`
126			`add_ram_output_register => "OFF",`
127	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
128	147	jguarin200	`intended_device_family => "Cyclone III",`
129			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
130			`almost_full_value => 32,`
131			`lpm_numwords => 32,`
132			`lpm_showahead => "ON",`
133			`lpm_type => "SCFIFO",`
134			`lpm_width => 96,`
135			`lpm_widthu => 5,`
136			`overflow_checking => "ON",`
137			`underflow_checking => "ON",`
138			`use_eab => "ON"`
139			`)`
140			`port map (`
141			`rdreq => normfifo_rd,`
142			`aclr => '0',`
143			`empty => open,`
144			`clock => clk,`
145			`q => normfifo_q,`
146			`wrreq => normfifo_wr,`
147			`data => normfifo_d,`
148			`almost_full => open,`
149			`full => open`
150			`);`
151	140	jguarin200
152			`--! Cola de instrucciones`
153			`qi : scfifo`
154	147	jguarin200	`generic map (`
155			`add_ram_output_register => "OFF",`
156	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
157	147	jguarin200	`intended_device_family => "Cyclone III",`
158			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
159			`almost_full_value => 32,`
160			`lpm_numwords => 32,`
161	160	jguarin200	`lpm_showahead => "ON",`
162	147	jguarin200	`lpm_type => "SCIFIFO",`
163			`lpm_width => 32,`
164			`lpm_widthu => 5,`
165			`overflow_checking => "ON",`
166			`underflow_checking => "ON",`
167			`use_eab => "ON"`
168			`)`
169			`port map (`
170			`rdreq => instrfifo_rd,`
171			`aclr => '0',`
172			`empty => instrfifo_empty,`
173			`clock => clk,`
174			`q => instrfifo_q,`
175	150	jguarin200	`wrreq => s0ext_wr_add_one_hot(12),`
176			`data => s0ext_d,`
177	147	jguarin200	`almost_full => open`
178			`);`
179	128	jguarin200
180	140	jguarin200	`--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de código, no influye en la sintesis del circuito.`
181	130	jguarin200	`sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);`
182			`sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);`
183
184	147	jguarin200	`--! Instanciación de la cola de resultados de salida.`
185	158	jguarin200	`int_q <= s1int_q;`
186	147	jguarin200	`operands_blocks:`
187			`for i in 11 downto 0 generate`
188	158	jguarin200	`--!int_q((i+1)floatwidth-1 downto floatwidthi) <= s1int_q(i);`
189	147	jguarin200	`operandsblock : altsyncram`
190			`generic map (`
191			`address_aclr_b => "NONE",`
192			`address_reg_b => "CLOCK0",`
193			`clock_enable_input_a => "BYPASS",`
194			`clock_enable_input_b => "BYPASS",`
195			`clock_enable_output_b => "BYPASS",`
196			`intended_device_family => "Cyclone III",`
197			`lpm_type => "altsyncram",`
198			`numwords_a => 2**widthadmemblock,`
199			`numwords_b => 2**widthadmemblock,`
200			`operation_mode => "DUAL_PORT",`
201			`outdata_aclr_b => "NONE",`
202			`outdata_reg_b => "CLOCK0",`
203			`power_up_uninitialized => "FALSE",`
204			`ram_block_type => "M9K",`
205			`rdcontrol_reg_b => "CLOCK0",`
206			`read_during_write_mode_mixed_ports => "OLD_DATA",`
207			`widthad_a => widthadmemblock,`
208			`widthad_b => widthadmemblock,`
209	152	jguarin200	`width_a => floatwidth,`
210			`width_b => floatwidth,`
211	147	jguarin200	`width_byteena_a => 1`
212			`)`
213			`port map (`
214			`wren_a => s0ext_wr_add_one_hot(i),`
215			`clock0 => clk,`
216			`address_a => s0ext_wr_add(widthadmemblock-1 downto 0),`
217			`address_b => sint_rd_add((i/3) mod 2),`
218			`rden_b => '1',`
219			`q_b => s1int_q(i),`
220			`data_a => s0ext_d`
221			`);`
222			`end generate operands_blocks;`
223
224	140	jguarin200	`--! Instanciación de la cola de resultados.`
225	150	jguarin200	`resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);`
226			`resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);`
227			`resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);`
228			`resultfifo_full(0) <= sresultfifo_full(0);`
229	158	jguarin200	`sint_d <= int_d;`
230	130	jguarin200	`results_blocks:`
231			`for i in 7 downto 0 generate`
232	138	jguarin200	`resultsfifo : scfifo`
233	147	jguarin200	`generic map (`
234			`add_ram_output_register => "OFF",`
235			`almost_full_value => 480,`
236	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
237	147	jguarin200	`intended_device_family => "Cyclone III",`
238			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
239			`lpm_numwords => 512,`
240			`lpm_showahead => "ON",`
241			`lpm_type => "SCIFIFO",`
242			`lpm_width => 32,`
243			`lpm_widthu => 9,`
244			`overflow_checking => "ON",`
245			`underflow_checking => "ON",`
246			`use_eab => "ON"`
247			`)`
248			`port map (`
249			`rdreq => s0ext_rd_ack(i),`
250			`aclr => '0',`
251	150	jguarin200	`empty => open,`
252	147	jguarin200	`clock => clk,`
253			`q => s0ext_q(i),`
254	150	jguarin200	`wrreq => resultfifo_wr(i),`
255	147	jguarin200	`data => sint_d(i),`
256	150	jguarin200	`almost_full => sresultfifo_full(i),`
257	147	jguarin200	`full => open`
258			`);`
259	130	jguarin200	`end generate results_blocks;`
260
261	140	jguarin200	`--! Escritura en registros de operandos de entrada.`
262	147	jguarin200	`operands_block_proc: process (clk,rst)`
263	129	jguarin200	`begin`
264	147	jguarin200	`if rst=rstMasterValue then`
265			`s0ext_wr_add <= (others => '0');`
266			`s0ext_wr <= '0';`
267			`s0ext_d <= (others => '0');`
268			`elsif clk'event and clk='1' then`
269			`--! Registro de entrada`
270			`s0ext_wr_add <= ext_wr_add;`
271			`s0ext_wr <= ext_wr;`
272			`s0ext_d <= ext_d;`
273	129	jguarin200	`end if;`
274			`end process;`
275	140	jguarin200
276			`--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.`
277	158	jguarin200	`s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);`
278	157	jguarin200	`operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)`
279	130	jguarin200	`begin`
280	138	jguarin200
281	140	jguarin200	`--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.`
282	141	jguarin200	`--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.`
283	157	jguarin200	`case s0ext_wr_add_choice is`
284			`when "0000" =>`
285			`s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;`
286			`when x"1" =>`
287			`s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';`
288			`when x"2" =>`
289			`s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";`
290			`when x"4" =>`
291			`s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";`
292			`when x"5" =>`
293			`s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";`
294			`when x"6" =>`
295			`s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";`
296			`when x"8" =>`
297			`s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";`
298			`when x"9" =>`
299			`s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";`
300			`when x"A" =>`
301			`s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";`
302			`when x"C" =>`
303			`s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";`
304			`when x"D" =>`
305			`s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";`
306			`when x"E" =>`
307			`s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";`
308			`when others =>`
309			`s0ext_wr_add_one_hot <= s0ext_wr&x"000";`
310	138	jguarin200	`end case;`
311
312			`end process;`
313	140	jguarin200
314			`--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.`
315	157	jguarin200	`s0ext_rd_add_choice <= '0'&s0ext_rd_add;`
316	147	jguarin200	`results_block_proc: process(clk,rst)`
317	138	jguarin200	`begin`
318	147	jguarin200	`if rst=rstMasterValue then`
319			`s0ext_rd_add <= (others => '0');`
320			`s0ext_rd <= '0';`
321			`elsif clk'event and clk='1' then`
322	130	jguarin200	`--!Registrar entrada`
323	138	jguarin200	`s0ext_rd_add <= ext_rd_add;`
324			`s0ext_rd <= ext_rd;`
325			`--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.`
326	157	jguarin200	`case s0ext_rd_add_choice is`
327	138	jguarin200	`when x"0" => ext_q <= s0ext_q(0);`
328			`when x"1" => ext_q <= s0ext_q(1);`
329			`when x"2" => ext_q <= s0ext_q(2);`
330			`when x"3" => ext_q <= s0ext_q(3);`
331			`when x"4" => ext_q <= s0ext_q(4);`
332			`when x"5" => ext_q <= s0ext_q(5);`
333			`when x"6" => ext_q <= s0ext_q(6);`
334			`when others => ext_q <= s0ext_q(7);`
335	130	jguarin200	`end case;`
336			`end if;`
337			`end process;`
338	140	jguarin200
339			`--! rdack decoder para las colas de resultados de salida.`
340	157	jguarin200	`results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)`
341	138	jguarin200	`begin`
342	157	jguarin200	`case s0ext_rd_add_choice is`
343	138	jguarin200	`when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;`
344			`when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';`
345			`when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";`
346			`when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";`
347			`when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";`
348			`when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";`
349			`when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";`
350			`when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";`
351			`end case;`
352			`end process;`
353	153	jguarin200	`end architecture;`
354	128	jguarin200

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