Subversion Repositories raytrac

# TCL File Generated by Component Editor 11.0

# Sat May 26 10:44:07 COT 2012

# DO NOT MODIFY

# +-----------------------------------

# | 

# | raytrac "raytrac" v1.0

# | null 2012.05.26.10:44:07

# | 

# | 

# | //IMACJULIAN/imac/Code/Indigo/fp/fp/raytrac.vhd

# | 

# |    ./arithblock.vhd syn

# |    ./arithpack.vhd syn

# |    ./customCounter.vhd syn

# |    ./dpc.vhd syn

# |    ./fadd32.vhd syn

# |    ./fmul32.vhd syn

# |    ./im.vhd syn

# |    ./invr32.vhd syn

# |    ./memblock.vhd syn

# |    ./meminvr.mif syn

# |    ./memsqrt.mif syn

# |    ./mulblock.vhd syn

# |    ./raytrac.vhd syn

# |    ./raytrac_hw.tcl 

# |    ./sm.vhd syn, sim

# |    ./sqrt32.vhd syn, sim

# | 

# +-----------------------------------

# +-----------------------------------

# | request TCL package from ACDS 11.0

# | 

package require -exact sopc 11.0

# | 

# +-----------------------------------

# +-----------------------------------

# | module raytrac

# | 

set_module_property NAME raytrac

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property DISPLAY_NAME raytrac

set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd

set_module_property TOP_LEVEL_HDL_MODULE raytrac

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL TRUE

set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""

set_module_property FIX_110_VIP_PATH false

# | 

# +-----------------------------------

# +-----------------------------------

# | files

# | 

add_file arithblock.vhd SYNTHESIS

add_file arithpack.vhd SYNTHESIS

add_file customCounter.vhd SYNTHESIS

add_file dpc.vhd SYNTHESIS

add_file fadd32.vhd SYNTHESIS

add_file fmul32.vhd SYNTHESIS

add_file im.vhd SYNTHESIS

add_file invr32.vhd SYNTHESIS

add_file memblock.vhd SYNTHESIS

add_file meminvr.mif SYNTHESIS

add_file memsqrt.mif SYNTHESIS

add_file mulblock.vhd SYNTHESIS

add_file raytrac.vhd SYNTHESIS

add_file raytrac_hw.tcl ""

add_file sm.vhd {SYNTHESIS SIMULATION}

add_file sqrt32.vhd {SYNTHESIS SIMULATION}

# | 

# +-----------------------------------

# +-----------------------------------

# | parameters

# | 

# | 

# +-----------------------------------

# +-----------------------------------

# | display items

# | 

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point clock

# | 

add_interface clock clock end

set_interface_property clock clockRate 50000000

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point avalon_slave_0

# | 

add_interface avalon_slave_0 avalon end

set_interface_property avalon_slave_0 addressAlignment DYNAMIC

set_interface_property avalon_slave_0 addressUnits WORDS

set_interface_property avalon_slave_0 associatedClock clock

set_interface_property avalon_slave_0 associatedReset reset_sink

set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false

set_interface_property avalon_slave_0 explicitAddressSpan 0

set_interface_property avalon_slave_0 holdTime 0

set_interface_property avalon_slave_0 isMemoryDevice false

set_interface_property avalon_slave_0 isNonVolatileStorage false

set_interface_property avalon_slave_0 linewrapBursts false

set_interface_property avalon_slave_0 maximumPendingReadTransactions 0

set_interface_property avalon_slave_0 printableDevice false

set_interface_property avalon_slave_0 readLatency 0

set_interface_property avalon_slave_0 readWaitTime 1

set_interface_property avalon_slave_0 setupTime 0

set_interface_property avalon_slave_0 timingUnits Cycles

set_interface_property avalon_slave_0 writeWaitTime 0

set_interface_property avalon_slave_0 ENABLED true

add_interface_port avalon_slave_0 wr write Input 1

add_interface_port avalon_slave_0 add address Input 13

add_interface_port avalon_slave_0 q readdata Output 32

add_interface_port avalon_slave_0 rd read Input 1

add_interface_port avalon_slave_0 d writedata Input 32

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point reset_sink

# | 

add_interface reset_sink reset end

set_interface_property reset_sink associatedClock clock

set_interface_property reset_sink synchronousEdges DEASSERT

set_interface_property reset_sink ENABLED true

add_interface_port reset_sink rst reset Input 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is06

# | 

add_interface is06 interrupt end

set_interface_property is06 associatedAddressablePoint avalon_slave_0

set_interface_property is06 associatedClock clock

set_interface_property is06 associatedReset reset_sink

set_interface_property is06 ENABLED true

add_interface_port is06 int06 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is04

# | 

add_interface is04 interrupt end

set_interface_property is04 associatedAddressablePoint avalon_slave_0

set_interface_property is04 associatedClock clock

set_interface_property is04 associatedReset reset_sink

set_interface_property is04 ENABLED true

add_interface_port is04 int04 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is03

# | 

add_interface is03 interrupt end

set_interface_property is03 associatedAddressablePoint avalon_slave_0

set_interface_property is03 associatedClock clock

set_interface_property is03 associatedReset reset_sink

set_interface_property is03 ENABLED true

add_interface_port is03 int03 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is02

# | 

add_interface is02 interrupt end

set_interface_property is02 associatedAddressablePoint avalon_slave_0

set_interface_property is02 associatedClock clock

set_interface_property is02 associatedReset reset_sink

set_interface_property is02 ENABLED true

add_interface_port is02 int02 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is01

# | 

add_interface is01 interrupt end

set_interface_property is01 associatedAddressablePoint avalon_slave_0

set_interface_property is01 associatedClock clock

set_interface_property is01 associatedReset reset_sink

set_interface_property is01 ENABLED true

add_interface_port is01 int01 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is00

# | 

add_interface is00 interrupt end

set_interface_property is00 associatedAddressablePoint avalon_slave_0

set_interface_property is00 associatedClock clock

set_interface_property is00 associatedReset reset_sink

set_interface_property is00 ENABLED true

add_interface_port is00 int00 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is07

# | 

add_interface is07 interrupt end

set_interface_property is07 associatedAddressablePoint avalon_slave_0

set_interface_property is07 associatedClock clock

set_interface_property is07 associatedReset reset_sink

set_interface_property is07 ENABLED true

add_interface_port is07 int07 irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point is05

# | 

add_interface is05 interrupt end

set_interface_property is05 associatedAddressablePoint avalon_slave_0

set_interface_property is05 associatedClock clock

set_interface_property is05 associatedReset reset_sink

set_interface_property is05 ENABLED true

add_interface_port is05 int05 irq Output 1

# | 

# +-----------------------------------