OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [ap_n_dpc.vhd] - Blame information for rev 220

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 219 jguarin200
--! @file ap_n_dpc.vhd
2 196 jguarin200
--! @brief Decodificador de operacién. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se es&eacutea; ejecutando en el momento.  
3 128 jguarin200
--! @author Julián Andrés Guarín Reyes
4 122 jguarin200
--------------------------------------------------------------
5
-- RAYTRAC
6
-- Author Julian Andres Guarin
7 219 jguarin200
-- ap_n_dpc.vhd
8 122 jguarin200
-- This file is part of raytrac.
9
-- 
10
--     raytrac is free software: you can redistribute it and/or modify
11
--     it under the terms of the GNU General Public License as published by
12
--     the Free Software Foundation, either version 3 of the License, or
13
--     (at your option) any later version.
14
-- 
15
--     raytrac is distributed in the hope that it will be useful,
16
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
17
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
--     GNU General Public License for more details.
19
-- 
20
--     You should have received a copy of the GNU General Public License
21
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
25 212 jguarin200
use ieee.std_logic_unsigned.all;
26 151 jguarin200
use work.arithpack.all;
27 134 jguarin200
 
28 212 jguarin200
library altera_mf;
29
use altera_mf.altera_mf_components.all;
30 158 jguarin200
 
31 212 jguarin200
 
32 219 jguarin200
entity ap_n_dpc is
33 152 jguarin200
 
34 122 jguarin200
        port (
35 204 jguarin200
                clk                                             : in    std_logic;
36
                rst                                             : in    std_logic;
37
 
38 196 jguarin200
                paraminput                              : in    vectorblock06;  --! Vectores A,B
39 204 jguarin200
 
40 196 jguarin200
                d,c,s                                   : in    std_logic;              --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
41 204 jguarin200
 
42 212 jguarin200
                sync_chain_1                    : in    std_logic;              --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
43 219 jguarin200
                sync_chain_pending              : out   std_logic;              --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.    
44 204 jguarin200
 
45 219 jguarin200
                qresult_w                               : out   std_logic;              --! Salidas de escritura y lectura en las colas de resultados.
46
                qresult_d                               : out   vectorblock04   --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores. 
47 204 jguarin200
 
48
 
49
 
50 122 jguarin200
        );
51 153 jguarin200
end entity;
52 122 jguarin200
 
53 219 jguarin200
architecture ap_n_dpc_arch of ap_n_dpc is
54 125 jguarin200
 
55 161 jguarin200
        --!TBXSTART:FACTORS_N_ADDENDS
56 212 jguarin200
        signal sfactor          : vectorblock12;
57
        signal ssumando         : vectorblock06;
58
        signal sdpfifo_q        : xfloat32;
59 161 jguarin200
        --!TBXEND
60 163 jguarin200
 
61
 
62
        --!TBXSTART:ARITHMETIC_RESULTS
63 212 jguarin200
        signal sresult          : vectorblock04;
64
        signal sprd32blk        : vectorblock06;
65
        signal sadd32blk        : vectorblock03;
66
        signal ssqr32blk        : xfloat32;
67
        signal sinv32blk        : xfloat32;
68
        signal sqxyz_q          : vectorblock03;
69
        signal sqxyz_e          : std_logic;
70 163 jguarin200
        --!TBXEND
71
 
72 160 jguarin200
 
73
        --!TBXSTART:SYNC_CHAIN
74 212 jguarin200
        signal ssync_chain      : std_logic_vector(25 downto 2);
75 171 jguarin200
        --!TBXEND
76 212 jguarin200
 
77
        signal qxyzd            : std_logic_vector(95 downto 0);
78
        signal qxyzq            : std_logic_vector(95 downto 0);
79
        signal sq1_d            : std_logic_vector(31 downto 0);
80
        signal sq1_q            : std_logic_vector(31 downto 0);
81
        signal sq1_w            : std_logic;
82
        signal sq1_e            : std_logic;
83 219 jguarin200
 
84
 
85
        signal sadd32blko       : vectorblock03;        --! Salidas de los 3 sumadores.
86
        signal sprd32blko       : vectorblock06;        --! Salidas de los 6 multiplicadores.
87
 
88
        signal sinv32blko       : xfloat32;             --! Salidas de la raiz cuadradas y el inversor.
89
        signal ssqr32blko       : xfloat32;             --! Salidas de la raiz cuadradas y el inversor.
90 163 jguarin200
 
91 219 jguarin200
        --! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
92
        component arithblock
93
        port (
94
 
95
                clk     : in std_logic;
96
                rst : in std_logic;
97
 
98
                sign            : in std_logic;
99
 
100
                prd32blki       : in vectorblock12;
101
                add32blki       : in vectorblock06;
102
 
103
                add32blko       : out vectorblock03;
104
                prd32blko       : out vectorblock06;
105
 
106
                sq32o           : out xfloat32;
107
                inv32o          : out xfloat32
108
 
109
        );
110
        end component;
111
 
112 123 jguarin200
begin
113 204 jguarin200
 
114 219 jguarin200
        --! Bloque Aritm&eacute;tico
115
        ap : arithblock
116
        port map (
117
                clk             => clk,
118
                rst                     => rst,
119 204 jguarin200
 
120 219 jguarin200
                sign            => s,
121
 
122
                prd32blki       => sfactor,
123
                add32blki       => ssumando,
124
 
125
                add32blko       => sadd32blko,
126
                prd32blko       => sprd32blko,
127
 
128
                sq32o           => ssqr32blko,
129
                inv32o          => sinv32blko
130
        );
131 122 jguarin200
 
132 142 jguarin200
        --! Cadena de sincronizaci&oacute;n: 29 posiciones.
133 219 jguarin200
        sync_chain_pending <= sync_chain_1 or not(sq1_e) or not(sqxyz_e);
134 140 jguarin200
        sync_chain_proc:
135 212 jguarin200
        process(clk,rst,sync_chain_1)
136 140 jguarin200
        begin
137
                if rst=rstMasterValue then
138 212 jguarin200
 
139
                        ssync_chain(25 downto 2) <= (others => '0');
140
 
141
                elsif clk'event and clk='1' then
142
 
143
 
144
                        for i in 25 downto 3 loop
145 142 jguarin200
                                ssync_chain(i) <= ssync_chain(i-1);
146 140 jguarin200
                        end loop;
147 212 jguarin200
                        ssync_chain(2) <= sync_chain_1;
148
 
149 140 jguarin200
                end if;
150 212 jguarin200
 
151
 
152 140 jguarin200
        end process sync_chain_proc;
153 144 jguarin200
 
154 163 jguarin200
 
155
 
156 140 jguarin200
        --! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, simplemente son abstracciones a nivel de c&oacute;digo y no representar&aacute; cambios en la s&iacute;ntesis.
157 212 jguarin200
        qresult_d <= sresult;
158 158 jguarin200
 
159
 
160 124 jguarin200
 
161 140 jguarin200
 
162
        --! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, son abstracciones de c&oacute;digo tambi&eacute;n, sin embargo se realizan a trav&eacute;s de registros. 
163
        register_products_outputs:
164
        process (clk)
165
        begin
166
                if clk'event and clk='1' then
167 219 jguarin200
                        sprd32blk <= sprd32blko;
168
                        sadd32blk <= sadd32blko;
169
                        sinv32blk <= sinv32blko;
170 204 jguarin200
                        --! Raiz Cuadrada.
171 219 jguarin200
                        ssqr32blk <= ssqr32blko;
172 140 jguarin200
                end if;
173
        end process;
174 148 jguarin200
 
175 196 jguarin200
        --! Decodificaci&oacute;n del Datapath.
176 212 jguarin200
        datapathproc:process(s,d,c,paraminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,sqxyz_q,ssync_chain,ssqr32blk,sq1_q)
177 196 jguarin200
        begin
178 204 jguarin200
                --Summador 0: DORC!
179
                if (d or c)='1' then
180
                        ssumando(s0) <= sprd32blk(p0);
181
                        ssumando(s1) <= sprd32blk(p1);
182
                else
183 212 jguarin200
                        ssumando(s0) <= paraminput(ax);
184
                        ssumando(s1) <= paraminput(bx);
185 204 jguarin200
                end if;
186
                --Sumador 1:
187
                if d='1' then
188
                        ssumando(s2) <= sadd32blk(a0);
189
                        ssumando(s3) <= sdpfifo_q;
190
                elsif c='0' then
191 212 jguarin200
                        ssumando(s2) <= paraminput(ay);
192
                        ssumando(s3) <= paraminput(by);
193 204 jguarin200
                else
194
                        ssumando(s2) <= sprd32blk(p2);
195
                        ssumando(s3) <= sprd32blk(p3);
196
                end if;
197
                --S2
198
                if c='0' then
199 212 jguarin200
                        ssumando(s4) <= paraminput(az);
200
                        ssumando(s5) <= paraminput(bz);
201 204 jguarin200
                else
202
                        ssumando(s4) <= sprd32blk(p4);
203
                        ssumando(s5) <= sprd32blk(p5);
204
                end if;
205
                --P0,P1,P2
206 212 jguarin200
                sfactor(f4) <= paraminput(az);
207 204 jguarin200
                if (not(d) and c)='1' then
208 212 jguarin200
                        sfactor(f0) <= paraminput(ay);
209
                        sfactor(f1) <= paraminput(bz);
210
                        sfactor(f2) <= paraminput(az);
211
                        sfactor(f3) <= paraminput(by);
212
                        sfactor(f5) <= paraminput(bx);
213 204 jguarin200
                else
214 212 jguarin200
                        sfactor(f0) <= paraminput(ax);
215
                        sfactor(f2) <= paraminput(ay);
216
                        sfactor(f1) <= paraminput(bx) ;
217
                        sfactor(f3) <= paraminput(by) ;
218
                        sfactor(f5) <= paraminput(bz) ;
219 204 jguarin200
                end if;
220
                --P3 P4 P5
221
                if (c and s)='1' then
222 212 jguarin200
                        sfactor(f6) <= paraminput(ax);
223
                        sfactor(f9) <= paraminput(by);
224 204 jguarin200
                else
225
                        sfactor(f6) <= sinv32blk;
226 212 jguarin200
                        sfactor(f9) <= sqxyz_q(qy);
227 204 jguarin200
                end if;
228
                if d='1' then
229 196 jguarin200
                        if s='0' then
230 212 jguarin200
                                sfactor(f7) <= sqxyz_q(qx);
231 196 jguarin200
                                sfactor(f8) <= sinv32blk;
232
                                sfactor(f10) <= sinv32blk;
233 212 jguarin200
                                sfactor(f11) <= sqxyz_q(qz);
234 196 jguarin200
                        else
235 212 jguarin200
                                sfactor(f7) <= paraminput(bx);
236
                                sfactor(f8) <= paraminput(ay);
237
                                sfactor(f10) <= paraminput(az);
238
                                sfactor(f11) <= paraminput(bz);
239 196 jguarin200
                        end if;
240 204 jguarin200
                else
241 212 jguarin200
                        sfactor(f7) <= paraminput(bz);
242
                        sfactor(f8) <= paraminput(ax);
243
                        sfactor(f10) <= paraminput(ay);
244
                        sfactor(f11) <= paraminput(bx);
245 204 jguarin200
                end if;
246
                --res0,1,2                      
247
                if d='1' then
248 212 jguarin200
                        sresult(qx) <= sprd32blk(p3);
249
                        sresult(qy) <= sprd32blk(p4);
250
                        sresult(qz) <= sprd32blk(p5);
251 204 jguarin200
                else
252 212 jguarin200
                        sresult(qx) <= sadd32blk(a0);
253
                        sresult(qy) <= sadd32blk(a1);
254
                        sresult(qz) <= sadd32blk(a2);
255 204 jguarin200
                end if;
256
                --res3
257 212 jguarin200
 
258 219 jguarin200
                sresult(qsc) <= sq1_q;
259
                if c='1'  then
260 212 jguarin200
                        sq1_d <= ssqr32blk;
261 219 jguarin200
                        sq1_w <= ssync_chain(20) and d;
262 204 jguarin200
                else
263 219 jguarin200
                        sq1_w <= ssync_chain(19) and d;
264 212 jguarin200
                        sq1_d <= sadd32blk(a1);
265 204 jguarin200
                end if;
266
 
267
                if d='1' then
268 212 jguarin200
                        if s='1'then
269
                                qresult_w <= ssync_chain(5);
270 196 jguarin200
                        else
271 212 jguarin200
                                qresult_w<= ssync_chain(25);
272 196 jguarin200
                        end if;
273
                else
274 198 jguarin200
                        if c='1' and s='1' then
275 212 jguarin200
                                qresult_w <= ssync_chain(12);
276 198 jguarin200
                        elsif c='0' then
277 212 jguarin200
                                qresult_w <= ssync_chain(8);
278 196 jguarin200
                        else
279 212 jguarin200
                                qresult_w <= '0';
280 196 jguarin200
                        end if;
281 125 jguarin200
                end if;
282 123 jguarin200
        end process;
283
 
284 204 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
285
        q0 : scfifo --! Debe ir registrada la salida.
286
        generic map (
287 212 jguarin200
                allow_rwcycle_when_full => "ON",
288
                lpm_widthu                              => 3,
289
                lpm_numwords                    => 6,
290 204 jguarin200
                lpm_showahead                   => "ON",
291
                lpm_width                               => 32,
292
                overflow_checking               => "ON",
293
                underflow_checking              => "ON",
294
                use_eab                                 => "OFF"
295
        )
296
        port    map (
297 212 jguarin200
                sclr            => '0',
298
                clock           => clk,
299 204 jguarin200
                rdreq           => ssync_chain(12),
300
                wrreq           => ssync_chain(5),
301 212 jguarin200
                data            => sprd32blk(p2),
302
                q                       => sdpfifo_q
303 204 jguarin200
        );
304 212 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
305
        q1 : scfifo --! Debe ir registrada la salida.
306
        generic map (
307
                allow_rwcycle_when_full => "ON",
308
                lpm_widthu                              => 3,
309
                lpm_numwords                    => 5,
310
                lpm_showahead                   => "ON",
311
                lpm_type                                => "SCIFIFO",
312
                lpm_width                               => 32,
313
                overflow_checking               => "ON",
314
                underflow_checking              => "ON",
315
                use_eab                                 => "OFF"
316
        )
317
        port map (
318
                rdreq           => ssync_chain(25),
319
                sclr            => '0',
320
                clock           => clk,
321 219 jguarin200
                empty           => sq1_e,
322 212 jguarin200
                q                       => sq1_q,
323
                wrreq           => sq1_w,
324
                data            => sq1_d
325
        );
326 123 jguarin200
 
327 204 jguarin200
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
328 212 jguarin200
        qxyzd(ax*32+31 downto ax*32) <= paraminput(ax);
329
        qxyzd(ay*32+31 downto ay*32) <= paraminput(ay);
330
        qxyzd(az*32+31 downto az*32) <= paraminput(az);
331
        sqxyz_q(ax) <= qxyzq(ax*32+31 downto ax*32);
332
        sqxyz_q(ay) <= qxyzq(ay*32+31 downto ay*32);
333
        sqxyz_q(az) <= qxyzq(az*32+31 downto az*32);
334 127 jguarin200
 
335 204 jguarin200
        qxqyqz : scfifo
336
        generic map (
337 212 jguarin200
                allow_rwcycle_when_full => "ON",
338
                lpm_widthu                              => 5,
339 204 jguarin200
                lpm_numwords                    => 32,
340 212 jguarin200
                lpm_showahead                   => "ON",
341 204 jguarin200
                lpm_width                               => 96,
342
                overflow_checking               => "ON",
343
                underflow_checking              => "ON",
344
                use_eab                                 => "ON"
345
        )
346
        port    map (
347
                aclr            => '0',
348
                clock           => clk,
349 212 jguarin200
                empty           => sqxyz_e,
350
                rdreq           => ssync_chain(21),
351
                wrreq           => sync_chain_1,
352
                data            => qxyzd,
353
                q                       => qxyzq
354 204 jguarin200
        );
355
 
356 196 jguarin200
 
357 204 jguarin200
 
358
 
359 153 jguarin200
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.