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1 219 jguarin200
--! @file ap_n_dpc.vhd
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--! @brief Decodificador de operacién. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se es&eacutea; ejecutando en el momento.  
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
5
-- RAYTRAC
6
-- Author Julian Andres Guarin
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-- ap_n_dpc.vhd
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-- This file is part of raytrac.
9
-- 
10
--     raytrac is free software: you can redistribute it and/or modify
11
--     it under the terms of the GNU General Public License as published by
12
--     the Free Software Foundation, either version 3 of the License, or
13
--     (at your option) any later version.
14
-- 
15
--     raytrac is distributed in the hope that it will be useful,
16
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
17
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
--     GNU General Public License for more details.
19
-- 
20
--     You should have received a copy of the GNU General Public License
21
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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library altera_mf;
29
use altera_mf.altera_mf_components.all;
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entity ap_n_dpc is
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        port (
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                clk                                             : in    std_logic;
36
                rst                                             : in    std_logic;
37
 
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                paraminput                              : in    vectorblock06;  --! Vectores A,B
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                d,c,s                                   : in    std_logic;              --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
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                sync_chain_1                    : in    std_logic;              --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
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                sync_chain_pending              : out   std_logic;              --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.    
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                qresult_w                               : out   std_logic;              --! Salidas de escritura y lectura en las colas de resultados.
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                qresult_d                               : out   vectorblock04   --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores. 
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48
 
49
 
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        );
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end entity;
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architecture ap_n_dpc_arch of ap_n_dpc is
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        --!Constantes de apoyo
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        constant ssync_chain_max : integer :=27;
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        constant ssync_chain_min : integer :=2;
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59
 
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        --!TBXSTART:FACTORS_N_ADDENDS
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        signal sfactor          : vectorblock12;
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        signal ssumando         : vectorblock06;
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        signal sdpfifo_q        : xfloat32;
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        --!TBXEND
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66
 
67
        --!TBXSTART:ARITHMETIC_RESULTS
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        signal sresult          : vectorblock04;
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        signal sprd32blk        : vectorblock06;
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        signal sadd32blk        : vectorblock03;
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        signal ssqr32blk        : xfloat32;
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        signal sinv32blk        : xfloat32;
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        signal sqxyz_q          : vectorblock03;
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        signal sqxyz_e          : std_logic;
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        --!TBXEND
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78
        --!TBXSTART:SYNC_CHAIN
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        signal ssync_chain      : std_logic_vector(ssync_chain_max downto ssync_chain_min);
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        --!TBXEND
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        signal qxyzd            : std_logic_vector(95 downto 0);
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        signal qxyzq            : std_logic_vector(95 downto 0);
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        signal sq2_d            : std_logic_vector(31 downto 0);
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        signal sq2_q            : std_logic_vector(31 downto 0);
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        signal sq2_w            : std_logic;
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        signal sq2_e            : std_logic;
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89
 
90
        signal sadd32blko       : vectorblock03;        --! Salidas de los 3 sumadores.
91
        signal sprd32blko       : vectorblock06;        --! Salidas de los 6 multiplicadores.
92
 
93
        signal sinv32blko       : xfloat32;             --! Salidas de la raiz cuadradas y el inversor.
94
        signal ssqr32blko       : xfloat32;             --! Salidas de la raiz cuadradas y el inversor.
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        --! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
97
        component arithblock
98
        port (
99
 
100
                clk     : in std_logic;
101
                rst : in std_logic;
102
 
103
                sign            : in std_logic;
104
 
105
                prd32blki       : in vectorblock12;
106
                add32blki       : in vectorblock06;
107
 
108
                add32blko       : out vectorblock03;
109
                prd32blko       : out vectorblock06;
110
 
111
                sq32o           : out xfloat32;
112
                inv32o          : out xfloat32
113
 
114
        );
115
        end component;
116
 
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begin
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        --! Bloque Aritm&eacute;tico
120
        ap : arithblock
121
        port map (
122
                clk             => clk,
123
                rst                     => rst,
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                sign            => s,
126
 
127
                prd32blki       => sfactor,
128
                add32blki       => ssumando,
129
 
130
                add32blko       => sadd32blko,
131
                prd32blko       => sprd32blko,
132
 
133
                sq32o           => ssqr32blko,
134
                inv32o          => sinv32blko
135
        );
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        --! Cadena de sincronizaci&oacute;n: 29 posiciones.
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        sync_chain_pending <= sync_chain_1 or not(sq2_e) or not(sqxyz_e);
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        sync_chain_proc:
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        process(clk,rst,sync_chain_1)
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        begin
142
                if rst=rstMasterValue then
143 212 jguarin200
 
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                        ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
145 212 jguarin200
 
146
                elsif clk'event and clk='1' then
147
 
148
 
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                        for i in ssync_chain_max downto ssync_chain_min+1 loop
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                                ssync_chain(i) <= ssync_chain(i-1);
151 140 jguarin200
                        end loop;
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                        ssync_chain(ssync_chain_min) <= sync_chain_1;
153 212 jguarin200
 
154 140 jguarin200
                end if;
155 212 jguarin200
 
156
 
157 140 jguarin200
        end process sync_chain_proc;
158 144 jguarin200
 
159 163 jguarin200
 
160
 
161 140 jguarin200
        --! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, simplemente son abstracciones a nivel de c&oacute;digo y no representar&aacute; cambios en la s&iacute;ntesis.
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        qresult_d <= sresult;
163 158 jguarin200
 
164
 
165 124 jguarin200
 
166 140 jguarin200
 
167
        --! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, son abstracciones de c&oacute;digo tambi&eacute;n, sin embargo se realizan a trav&eacute;s de registros. 
168
        register_products_outputs:
169
        process (clk)
170
        begin
171
                if clk'event and clk='1' then
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                        sprd32blk <= sprd32blko;
173
                        sadd32blk <= sadd32blko;
174
                        sinv32blk <= sinv32blko;
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                        --! Raiz Cuadrada.
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                        ssqr32blk <= ssqr32blko;
177 140 jguarin200
                end if;
178
        end process;
179 148 jguarin200
 
180 196 jguarin200
        --! Decodificaci&oacute;n del Datapath.
181 228 jguarin200
        datapathproc:process(s,d,c,paraminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,sqxyz_q,ssync_chain,ssqr32blk,sq2_q)
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        begin
183 204 jguarin200
                --Summador 0: DORC!
184
                if (d or c)='1' then
185
                        ssumando(s0) <= sprd32blk(p0);
186
                        ssumando(s1) <= sprd32blk(p1);
187
                else
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                        ssumando(s0) <= paraminput(ax);
189
                        ssumando(s1) <= paraminput(bx);
190 204 jguarin200
                end if;
191
                --Sumador 1:
192
                if d='1' then
193
                        ssumando(s2) <= sadd32blk(a0);
194
                        ssumando(s3) <= sdpfifo_q;
195
                elsif c='0' then
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                        ssumando(s2) <= paraminput(ay);
197
                        ssumando(s3) <= paraminput(by);
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                else
199
                        ssumando(s2) <= sprd32blk(p2);
200
                        ssumando(s3) <= sprd32blk(p3);
201
                end if;
202
                --S2
203
                if c='0' then
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                        ssumando(s4) <= paraminput(az);
205
                        ssumando(s5) <= paraminput(bz);
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                else
207
                        ssumando(s4) <= sprd32blk(p4);
208
                        ssumando(s5) <= sprd32blk(p5);
209
                end if;
210
                --P0,P1,P2
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                sfactor(f4) <= paraminput(az);
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                if (not(d) and c)='1' then
213 212 jguarin200
                        sfactor(f0) <= paraminput(ay);
214
                        sfactor(f1) <= paraminput(bz);
215
                        sfactor(f2) <= paraminput(az);
216
                        sfactor(f3) <= paraminput(by);
217
                        sfactor(f5) <= paraminput(bx);
218 204 jguarin200
                else
219 212 jguarin200
                        sfactor(f0) <= paraminput(ax);
220
                        sfactor(f2) <= paraminput(ay);
221
                        sfactor(f1) <= paraminput(bx) ;
222
                        sfactor(f3) <= paraminput(by) ;
223
                        sfactor(f5) <= paraminput(bz) ;
224 204 jguarin200
                end if;
225
                --P3 P4 P5
226
                if (c and s)='1' then
227 212 jguarin200
                        sfactor(f6) <= paraminput(ax);
228
                        sfactor(f9) <= paraminput(by);
229 204 jguarin200
                else
230
                        sfactor(f6) <= sinv32blk;
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                        sfactor(f9) <= sqxyz_q(qy);
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                end if;
233
                if d='1' then
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                        if s='0' then
235 212 jguarin200
                                sfactor(f7) <= sqxyz_q(qx);
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                                sfactor(f8) <= sinv32blk;
237
                                sfactor(f10) <= sinv32blk;
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                                sfactor(f11) <= sqxyz_q(qz);
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                        else
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                                sfactor(f7) <= paraminput(bx);
241
                                sfactor(f8) <= paraminput(ay);
242
                                sfactor(f10) <= paraminput(az);
243
                                sfactor(f11) <= paraminput(bz);
244 196 jguarin200
                        end if;
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                else
246 212 jguarin200
                        sfactor(f7) <= paraminput(bz);
247
                        sfactor(f8) <= paraminput(ax);
248
                        sfactor(f10) <= paraminput(ay);
249
                        sfactor(f11) <= paraminput(bx);
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                end if;
251
                --res0,1,2                      
252
                if d='1' then
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                        sresult(qx) <= sprd32blk(p3);
254
                        sresult(qy) <= sprd32blk(p4);
255
                        sresult(qz) <= sprd32blk(p5);
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                else
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                        sresult(qx) <= sadd32blk(a0);
258
                        sresult(qy) <= sadd32blk(a1);
259
                        sresult(qz) <= sadd32blk(a2);
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                end if;
261
                --res3
262 212 jguarin200
 
263 228 jguarin200
                sresult(qsc) <= sq2_q;
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                if c='1'  then
265 228 jguarin200
                        sq2_d <= ssqr32blk;
266
                        sq2_w <= ssync_chain(22) and d and not(s);
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                else
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                        sq2_w <= ssync_chain(21) and d and not(s);
269
                        sq2_d <= sadd32blk(a1);
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                end if;
271
 
272
                if d='1' then
273 212 jguarin200
                        if s='1'then
274
                                qresult_w <= ssync_chain(5);
275 196 jguarin200
                        else
276 228 jguarin200
                                qresult_w<= ssync_chain(27);
277 196 jguarin200
                        end if;
278
                else
279 198 jguarin200
                        if c='1' and s='1' then
280 228 jguarin200
                                qresult_w <= ssync_chain(13);
281 198 jguarin200
                        elsif c='0' then
282 228 jguarin200
                                qresult_w <= ssync_chain(9);
283 196 jguarin200
                        else
284 212 jguarin200
                                qresult_w <= '0';
285 196 jguarin200
                        end if;
286 125 jguarin200
                end if;
287 123 jguarin200
        end process;
288
 
289 204 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
290
        q0 : scfifo --! Debe ir registrada la salida.
291
        generic map (
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                allow_rwcycle_when_full => "ON",
293
                lpm_widthu                              => 3,
294
                lpm_numwords                    => 6,
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                lpm_showahead                   => "ON",
296
                lpm_width                               => 32,
297
                overflow_checking               => "ON",
298
                underflow_checking              => "ON",
299 228 jguarin200
                use_eab                                 => "ON"
300 204 jguarin200
        )
301
        port    map (
302 212 jguarin200
                sclr            => '0',
303
                clock           => clk,
304 228 jguarin200
                rdreq           => ssync_chain(13),
305 204 jguarin200
                wrreq           => ssync_chain(5),
306 212 jguarin200
                data            => sprd32blk(p2),
307
                q                       => sdpfifo_q
308 204 jguarin200
        );
309 212 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
310 228 jguarin200
        q2 : scfifo --! Debe ir registrada la salida.
311 212 jguarin200
        generic map (
312
                allow_rwcycle_when_full => "ON",
313
                lpm_widthu                              => 3,
314
                lpm_numwords                    => 5,
315
                lpm_showahead                   => "ON",
316
                lpm_type                                => "SCIFIFO",
317
                lpm_width                               => 32,
318
                overflow_checking               => "ON",
319
                underflow_checking              => "ON",
320 228 jguarin200
                use_eab                                 => "ON"
321 212 jguarin200
        )
322
        port map (
323 228 jguarin200
                rdreq           => ssync_chain(27),
324 212 jguarin200
                sclr            => '0',
325
                clock           => clk,
326 228 jguarin200
                empty           => sq2_e,
327
                q                       => sq2_q,
328
                wrreq           => sq2_w,
329
                data            => sq2_d
330 212 jguarin200
        );
331 123 jguarin200
 
332 204 jguarin200
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
333 212 jguarin200
        qxyzd(ax*32+31 downto ax*32) <= paraminput(ax);
334
        qxyzd(ay*32+31 downto ay*32) <= paraminput(ay);
335
        qxyzd(az*32+31 downto az*32) <= paraminput(az);
336
        sqxyz_q(ax) <= qxyzq(ax*32+31 downto ax*32);
337
        sqxyz_q(ay) <= qxyzq(ay*32+31 downto ay*32);
338
        sqxyz_q(az) <= qxyzq(az*32+31 downto az*32);
339 127 jguarin200
 
340 228 jguarin200
        q1xyz : scfifo
341 204 jguarin200
        generic map (
342 212 jguarin200
                allow_rwcycle_when_full => "ON",
343
                lpm_widthu                              => 5,
344 204 jguarin200
                lpm_numwords                    => 32,
345 212 jguarin200
                lpm_showahead                   => "ON",
346 204 jguarin200
                lpm_width                               => 96,
347
                overflow_checking               => "ON",
348
                underflow_checking              => "ON",
349
                use_eab                                 => "ON"
350
        )
351
        port    map (
352
                aclr            => '0',
353
                clock           => clk,
354 212 jguarin200
                empty           => sqxyz_e,
355 228 jguarin200
                rdreq           => ssync_chain(23),
356 212 jguarin200
                wrreq           => sync_chain_1,
357
                data            => qxyzd,
358
                q                       => qxyzq
359 204 jguarin200
        );
360
 
361 196 jguarin200
 
362 204 jguarin200
 
363
 
364 153 jguarin200
end architecture;

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