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1 219 jguarin200
--! @file ap_n_dpc.vhd
2 196 jguarin200
--! @brief Decodificador de operacién. Sistema de decodificaci√≥n de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se es&eacutea; ejecutando en el momento.  
3 128 jguarin200
--! @author Julián Andrés Guarín Reyes
4 122 jguarin200
--------------------------------------------------------------
5
-- RAYTRAC
6
-- Author Julian Andres Guarin
7 219 jguarin200
-- ap_n_dpc.vhd
8 122 jguarin200
-- This file is part of raytrac.
9
-- 
10
--     raytrac is free software: you can redistribute it and/or modify
11
--     it under the terms of the GNU General Public License as published by
12
--     the Free Software Foundation, either version 3 of the License, or
13
--     (at your option) any later version.
14
-- 
15
--     raytrac is distributed in the hope that it will be useful,
16
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
17
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
--     GNU General Public License for more details.
19
-- 
20
--     You should have received a copy of the GNU General Public License
21
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
25 212 jguarin200
use ieee.std_logic_unsigned.all;
26 151 jguarin200
use work.arithpack.all;
27 134 jguarin200
 
28 212 jguarin200
library altera_mf;
29
use altera_mf.altera_mf_components.all;
30 158 jguarin200
 
31 212 jguarin200
 
32 219 jguarin200
entity ap_n_dpc is
33 152 jguarin200
 
34 122 jguarin200
        port (
35 229 jguarin200
 
36 248 jguarin200
                p0,p1,p2,p3,p4,p5,p6,p7,p8: out std_logic_vector(31 downto 0);
37 242 jguarin200
 
38
 
39 204 jguarin200
                clk                                             : in    std_logic;
40
                rst                                             : in    std_logic;
41
 
42 229 jguarin200
                ax                                              : in    std_logic_vector(31 downto 0);
43
                ay                                              : in    std_logic_vector(31 downto 0);
44
                az                                              : in    std_logic_vector(31 downto 0);
45
                bx                                              : in    std_logic_vector(31 downto 0);
46
                by                                              : in    std_logic_vector(31 downto 0);
47
                bz                                              : in    std_logic_vector(31 downto 0);
48
                vx                                              : out   std_logic_vector(31 downto 0);
49
                vy                                              : out   std_logic_vector(31 downto 0);
50
                vz                                              : out   std_logic_vector(31 downto 0);
51
                sc                                              : out   std_logic_vector(31 downto 0);
52
                ack                                             : in    std_logic;
53
                empty                                   : out   std_logic;
54 256 jguarin200
                sign_switcheroo                 : in            std_logic;
55 204 jguarin200
 
56 229 jguarin200
                 --paraminput                           : in    vectorblock06;  --! Vectores A,B
57 204 jguarin200
 
58 229 jguarin200
                dcs                                             : in    std_logic_vector(2 downto 0);            --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
59
 
60 212 jguarin200
                sync_chain_1                    : in    std_logic;              --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
61 229 jguarin200
                pipeline_pending                : out   std_logic               --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.    
62 204 jguarin200
 
63 229 jguarin200
 
64
 
65
                --qresult_d                             : out   vectorblock04   --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores. 
66
 
67 204 jguarin200
 
68
 
69 122 jguarin200
        );
70 153 jguarin200
end entity;
71 122 jguarin200
 
72 219 jguarin200
architecture ap_n_dpc_arch of ap_n_dpc is
73 228 jguarin200
        --!Constantes de apoyo
74 248 jguarin200
        constant ssync_chain_max : integer :=32;
75 228 jguarin200
        constant ssync_chain_min : integer :=2;
76 125 jguarin200
 
77 235 jguarin200
        --! Tunnning delay
78
        constant adder2_delay: integer := 1;
79 242 jguarin200
        constant adder1_delay : integer := 1;
80 228 jguarin200
 
81 161 jguarin200
        --!TBXSTART:FACTORS_N_ADDENDS
82 242 jguarin200
        signal sfactor0 : std_logic_vector(31 downto 0);
83
        signal sfactor1 : std_logic_vector(31 downto 0);
84
        signal sfactor2 : std_logic_vector(31 downto 0);
85
        signal sfactor3 : std_logic_vector(31 downto 0);
86
        signal sfactor4 : std_logic_vector(31 downto 0);
87
        signal sfactor5 : std_logic_vector(31 downto 0);
88
        signal sfactor6 : std_logic_vector(31 downto 0);
89
        signal sfactor7 : std_logic_vector(31 downto 0);
90
        signal sfactor8 : std_logic_vector(31 downto 0);
91
        signal sfactor9 : std_logic_vector(31 downto 0);
92 229 jguarin200
        signal sfactor10        : std_logic_vector(31 downto 0);
93
        signal sfactor11        : std_logic_vector(31 downto 0);
94
        --signal sfactor                : vectorblock12;
95
 
96
        signal ssumando0        : std_logic_vector(31 downto 0);
97
        signal ssumando1        : std_logic_vector(31 downto 0);
98
        signal ssumando2        : std_logic_vector(31 downto 0);
99
        signal ssumando3        : std_logic_vector(31 downto 0);
100
        signal ssumando4        : std_logic_vector(31 downto 0);
101
        signal ssumando5        : std_logic_vector(31 downto 0);
102
        --signal ssumando               : vectorblock06;
103
 
104
        signal sq0_q            : std_logic_vector(31 downto 0);
105 161 jguarin200
        --!TBXEND
106 163 jguarin200
 
107
 
108
        --!TBXSTART:ARITHMETIC_RESULTS
109 229 jguarin200
 
110
        signal sp0                      : std_logic_vector(31 downto 0);
111
        signal sp1                      : std_logic_vector(31 downto 0);
112
        signal sp2                      : std_logic_vector(31 downto 0);
113
        signal sp3                      : std_logic_vector(31 downto 0);
114
        signal sp4                      : std_logic_vector(31 downto 0);
115
        signal sp5                      : std_logic_vector(31 downto 0);
116
        --signal sprd32blk      : vectorblock06;
117
 
118
        signal sa0                      : std_logic_vector(31 downto 0);
119
        signal sa1                      : std_logic_vector(31 downto 0);
120
        signal sa2                      : std_logic_vector(31 downto 0);
121
 
122
        --signal sadd32blk      : vectorblock03;
123
 
124
        signal ssq32    : std_logic_vector(31 downto 0);
125
        signal sinv32   : std_logic_vector(31 downto 0);
126
 
127
        signal sqx_q            : std_logic_vector(31 downto 0);
128
        signal sqy_q            : std_logic_vector(31 downto 0);
129
        signal sqz_q            : std_logic_vector(31 downto 0);
130
        --signal sqxyz_q                : vectorblock03;
131
 
132
        signal sq1_e            : std_logic;
133 163 jguarin200
        --!TBXEND
134
 
135 160 jguarin200
 
136
        --!TBXSTART:SYNC_CHAIN
137 228 jguarin200
        signal ssync_chain      : std_logic_vector(ssync_chain_max downto ssync_chain_min);
138 171 jguarin200
        --!TBXEND
139 212 jguarin200
 
140 229 jguarin200
        --signal qxyzd          : std_logic_vector(95 downto 0);
141
 
142
        --signal qxyzq          : std_logic_vector(95 downto 0);
143
 
144 228 jguarin200
        signal sq2_d            : std_logic_vector(31 downto 0);
145
        signal sq2_q            : std_logic_vector(31 downto 0);
146
        signal sq2_w            : std_logic;
147
        signal sq2_e            : std_logic;
148 219 jguarin200
 
149 229 jguarin200
        signal sqr_e            : std_logic;
150
        signal sqr_w            : std_logic;            --! Salidas de escritura y lectura en las colas de resultados.
151
        signal sqr_dx           : std_logic_vector(31 downto 0);
152
        signal sqr_dy           : std_logic_vector(31 downto 0);
153
        signal sqr_dz           : std_logic_vector(31 downto 0);
154
        signal sqr_dsc          : std_logic_vector(31 downto 0);
155
 
156 219 jguarin200
 
157
 
158 229 jguarin200
        signal sa0o                     : std_logic_vector(31 downto 0);
159
        signal sa1o                     : std_logic_vector(31 downto 0);
160
        signal sa2o                     : std_logic_vector(31 downto 0);
161
        --signal sadd32blko     : vectorblock03;        --! Salidas de los 3 sumadores.
162 163 jguarin200
 
163 229 jguarin200
        signal sp0o                     : std_logic_vector(31 downto 0);
164
        signal sp1o                     : std_logic_vector(31 downto 0);
165
        signal sp2o                     : std_logic_vector(31 downto 0);
166
        signal sp3o                     : std_logic_vector(31 downto 0);
167
        signal sp4o                     : std_logic_vector(31 downto 0);
168
        signal sp5o                     : std_logic_vector(31 downto 0);
169
        --signal sprd32blko     : vectorblock06;        --! Salidas de los 6 multiplicadores.
170
 
171
        signal sinv32o  : std_logic_vector(31 downto 0);         --! Salidas de la raiz cuadradas y el inversor.
172
        signal ssq32o   : std_logic_vector(31 downto 0);         --! Salidas de la raiz cuadradas y el inversor.
173
 
174 219 jguarin200
        --! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
175
        component arithblock
176
        port (
177
 
178
                clk     : in std_logic;
179
                rst : in std_logic;
180
 
181
                sign            : in std_logic;
182 256 jguarin200
                sign_switch     : in std_logic;
183 229 jguarin200
 
184
                factor0         : in std_logic_vector(31 downto 0);
185
                factor1         : in std_logic_vector(31 downto 0);
186
                factor2         : in std_logic_vector(31 downto 0);
187
                factor3         : in std_logic_vector(31 downto 0);
188
                factor4         : in std_logic_vector(31 downto 0);
189
                factor5         : in std_logic_vector(31 downto 0);
190
                factor6         : in std_logic_vector(31 downto 0);
191
                factor7         : in std_logic_vector(31 downto 0);
192
                factor8         : in std_logic_vector(31 downto 0);
193
                factor9         : in std_logic_vector(31 downto 0);
194
                factor10        : in std_logic_vector(31 downto 0);
195
                factor11        : in std_logic_vector(31 downto 0);
196
                --prd32blki     : in vectorblock06;
197 219 jguarin200
 
198 229 jguarin200
                sumando0        : in std_logic_vector(31 downto 0);
199
                sumando1        : in std_logic_vector(31 downto 0);
200
                sumando2        : in std_logic_vector(31 downto 0);
201
                sumando3        : in std_logic_vector(31 downto 0);
202
                sumando4        : in std_logic_vector(31 downto 0);
203
                sumando5        : in std_logic_vector(31 downto 0);
204
                --add32blki     : in vectorblock06;
205 219 jguarin200
 
206 229 jguarin200
                a0                      : out std_logic_vector(31 downto 0);
207
                a1                      : out std_logic_vector(31 downto 0);
208
                a2                      : out std_logic_vector(31 downto 0);
209
                --add32blko     : out vectorblock03;
210 219 jguarin200
 
211 229 jguarin200
                p0                      : out std_logic_vector(31 downto 0);
212
                p1                      : out std_logic_vector(31 downto 0);
213
                p2                      : out std_logic_vector(31 downto 0);
214
                p3                      : out std_logic_vector(31 downto 0);
215
                p4                      : out std_logic_vector(31 downto 0);
216
                p5                      : out std_logic_vector(31 downto 0);
217
                --prd32blko     : out vectorblock06;
218
 
219
                sq32o           : out std_logic_vector(31 downto 0);
220
                inv32o          : out std_logic_vector(31 downto 0)
221 219 jguarin200
 
222
        );
223
        end component;
224
 
225 123 jguarin200
begin
226 204 jguarin200
 
227 219 jguarin200
        --! Bloque Aritm&eacute;tico
228
        ap : arithblock
229
        port map (
230
                clk             => clk,
231
                rst                     => rst,
232 204 jguarin200
 
233 229 jguarin200
                sign            => dcs(0),
234 257 jguarin200
                sign_switch     => sign_switcheroo,
235 219 jguarin200
 
236 229 jguarin200
                factor0 =>sfactor0,
237
                factor1 =>sfactor1,
238
                factor2 =>sfactor2,
239
                factor3 =>sfactor3,
240
                factor4 =>sfactor4,
241
                factor5 =>sfactor5,
242
                factor6 =>sfactor6,
243
                factor7 =>sfactor7,
244
                factor8 =>sfactor8,
245
                factor9 =>sfactor9,
246
                factor10=>sfactor10,
247
                factor11=>sfactor11,
248
                --prd32blki     => sfactor,
249
 
250
                sumando0=>ssumando0,
251
                sumando1=>ssumando1,
252
                sumando2=>ssumando2,
253
                sumando3=>ssumando3,
254
                sumando4=>ssumando4,
255
                sumando5=>ssumando5,
256
                --add32blki     => ssumando,
257 219 jguarin200
 
258 229 jguarin200
                a0=>sa0o,
259
                a1=>sa1o,
260
                a2=>sa2o,
261
                --add32blko     => sadd32blko, 
262 219 jguarin200
 
263 229 jguarin200
                p0=>sp0o,
264
                p1=>sp1o,
265
                p2=>sp2o,
266
                p3=>sp3o,
267
                p4=>sp4o,
268
                p5=>sp5o,
269
                --prd32blko     => sprd32blko,
270
 
271
                sq32o=> ssq32o,
272
                inv32o=> sinv32o
273 219 jguarin200
        );
274 122 jguarin200
 
275 142 jguarin200
        --! Cadena de sincronizaci&oacute;n: 29 posiciones.
276 229 jguarin200
        pipeline_pending <= sync_chain_1 or not(sq2_e) or not(sq1_e) or not(sqr_e);
277
        empty <= sqr_e;
278 140 jguarin200
        sync_chain_proc:
279 212 jguarin200
        process(clk,rst,sync_chain_1)
280 140 jguarin200
        begin
281
                if rst=rstMasterValue then
282 228 jguarin200
                        ssync_chain(ssync_chain_max downto ssync_chain_min) <= (others => '0');
283 230 jguarin200
 
284 242 jguarin200
                        p0 <= (others => '0');
285
                        p1 <= (others => '0');
286
                        p2 <= (others => '0');
287
 
288 229 jguarin200
                elsif clk'event and clk='1' then
289 228 jguarin200
                        for i in ssync_chain_max downto ssync_chain_min+1 loop
290 142 jguarin200
                                ssync_chain(i) <= ssync_chain(i-1);
291 140 jguarin200
                        end loop;
292 228 jguarin200
                        ssync_chain(ssync_chain_min) <= sync_chain_1;
293 242 jguarin200
 
294
                        --! Salida de los multiplicadores p0 p1 p2 
295 248 jguarin200
                        if ssync_chain(23)='1' then
296
                                p0 <= ssq32; -- El resultado quedara consignado en VZ1=BASE+1
297
                        elsif ssync_chain(28)='1' then
298
                                p1 <= sq2_q; -- El resultado quedara consignado en VX1=BASE+3
299
                        elsif ssync_chain(24)='1' then
300
                                p2 <= sinv32; -- El resutlado quedara consignado en VY1=BASE+2
301
                                p3 <= sqx_q;
302
                                p4 <= sqy_q;
303
                                p5 <= sqz_q;
304
                        elsif ssync_chain(28)='1' then
305
                                p6 <= sp3o;
306
                                p7 <= sp4o;
307
                                p8 <= sp5o;
308 242 jguarin200
                        end if;
309
 
310 140 jguarin200
                end if;
311
        end process sync_chain_proc;
312 144 jguarin200
 
313 163 jguarin200
 
314 158 jguarin200
 
315
 
316 124 jguarin200
 
317 140 jguarin200
        --! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, son abstracciones de c&oacute;digo tambi&eacute;n, sin embargo se realizan a trav&eacute;s de registros. 
318
        register_products_outputs:
319
        process (clk)
320
        begin
321
                if clk'event and clk='1' then
322 229 jguarin200
                        sp0 <= sp0o;
323
                        sp1 <= sp1o;
324
                        sp2 <= sp2o;
325
                        sp3 <= sp3o;
326
                        sp4 <= sp4o;
327
                        sp5 <= sp5o;
328
                        sa0 <= sa0o;
329
                        sa1 <= sa1o;
330
                        sa2 <= sa2o;
331
                        sinv32 <= sinv32o;
332
                        ssq32 <= ssq32o;
333 140 jguarin200
                end if;
334
        end process;
335 148 jguarin200
 
336 196 jguarin200
        --! Decodificaci&oacute;n del Datapath.
337 229 jguarin200
        datapathproc:process(dcs,ax,bx,ay,by,az,bz,sinv32,sp0,sp1,sp2,sp3,sp4,sp5,sa0,sa1,sa2,sq0_q,sqx_q,sqy_q,sqz_q,ssync_chain,ssq32,sq2_q)
338 196 jguarin200
        begin
339 229 jguarin200
 
340
                case dcs is
341
                        when "011"  =>
342
 
343
                                sq2_w <= '0';
344
                                sq2_d <= ssq32;
345
 
346
                                sfactor0 <= ay;
347
                                sfactor1 <= bz;
348
                                sfactor2 <= az;
349
                                sfactor3 <= by;
350
                                sfactor4 <= az;
351
                                sfactor5 <= bx;
352
                                sfactor6 <= ax;
353
                                sfactor7 <= bz;
354
                                sfactor8 <= ax;
355
                                sfactor9 <= by;
356
                                sfactor10 <= ay;
357
                                sfactor11 <= bx;
358
 
359
                                ssumando0 <= sp0;
360
                                ssumando1 <= sp1;
361
                                ssumando2 <= sp2;
362
                                ssumando3 <= sp3;
363
                                ssumando4 <= sp4;
364
                                ssumando5 <= sp5;
365
 
366
                                sqr_dx <= sa0;
367
                                sqr_dy <= sa1;
368
                                sqr_dz <= sa2;
369
 
370 230 jguarin200
                                sqr_w <= ssync_chain(13+adder2_delay);
371 229 jguarin200
 
372
                        when"000"|"001" =>
373
 
374
                                sq2_w <= '0';
375
                                sq2_d <= ssq32;
376
 
377
                                sfactor0 <= ay;
378
                                sfactor1 <= bz;
379
                                sfactor2 <= az;
380
                                sfactor3 <= by;
381
                                sfactor4 <= az;
382
                                sfactor5 <= bx;
383
                                sfactor6 <= ax;
384
                                sfactor7 <= bz;
385
                                sfactor8 <= ax;
386
                                sfactor9 <= by;
387
                                sfactor10 <= ay;
388
                                sfactor11 <= bx;
389
 
390
 
391
                                ssumando0 <= ax;
392
                                ssumando1 <= bx;
393
                                ssumando2 <= ay;
394
                                ssumando3 <= by;
395
                                ssumando4 <= az;
396
                                ssumando5 <= bz;
397
 
398
                                sqr_dx <= sa0;
399
                                sqr_dy <= sa1;
400
                                sqr_dz <= sa2;
401
 
402 230 jguarin200
                                sqr_w <= ssync_chain(9+adder2_delay);
403 229 jguarin200
 
404
                        when"110" |"100" =>
405
 
406
 
407
 
408
                                sfactor0 <= ax;
409
                                sfactor1 <= bx;
410
                                sfactor2 <= ay;
411
                                sfactor3 <= by;
412
                                sfactor4 <= az;
413
                                sfactor5 <= bz;
414
 
415
                                sfactor6 <= sinv32;
416
                                sfactor7 <= sqx_q;
417
                                sfactor8 <= sinv32;
418
                                sfactor9 <= sqy_q;
419
                                sfactor10 <= sinv32;
420
                                sfactor11 <= sqz_q;
421
 
422
 
423
                                ssumando0 <= sp0;
424
                                ssumando1 <= sp1;
425
                                ssumando2 <= sa0;
426
                                ssumando3 <= sq0_q;
427
                                ssumando4 <= az;
428
                                ssumando5 <= bz;
429
 
430
                                if dcs(1)='1' then
431
                                        sq2_d <= ssq32;
432 242 jguarin200
                                        sq2_w <= ssync_chain(22+adder1_delay);
433 229 jguarin200
                                else
434
                                        sq2_d <= sa1;
435 242 jguarin200
                                        sq2_w <= ssync_chain(21+adder1_delay);
436 229 jguarin200
                                end if;
437
 
438
                                sqr_dx <= sp3;
439
                                sqr_dy <= sp4;
440
                                sqr_dz <= sp5;
441
 
442 248 jguarin200
                                sqr_w <= ssync_chain(27+adder1_delay);
443 229 jguarin200
 
444
                        when others =>
445
 
446
                                sq2_w <= '0';
447
                                sq2_d <= ssq32;
448
 
449
                                sfactor0 <= ax;
450
                                sfactor1 <= bx;
451
                                sfactor2 <= ay;
452
                                sfactor3 <= by;
453
                                sfactor4 <= az;
454
                                sfactor5 <= bz;
455
 
456
                                sfactor6 <= ax;
457
                                sfactor7 <= bx;
458
                                sfactor8 <= ay;
459
                                sfactor9 <= by;
460
                                sfactor10 <= az;
461
                                sfactor11 <= bz;
462
 
463
                                ssumando0 <= sp0;
464
                                ssumando1 <= sp1;
465
                                ssumando2 <= sa0;
466
                                ssumando3 <= sq0_q;
467
                                ssumando4 <= az;
468
                                ssumando5 <= bz;
469
 
470
                                sqr_dx <= sp3;
471
                                sqr_dy <= sp4;
472
                                sqr_dz <= sp5;
473
 
474
                                sqr_w <= ssync_chain(5);
475
 
476
                end case;
477
 
478
 
479
 
480
 
481 123 jguarin200
        end process;
482
 
483 204 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
484
        q0 : scfifo --! Debe ir registrada la salida.
485
        generic map (
486 212 jguarin200
                allow_rwcycle_when_full => "ON",
487 229 jguarin200
                lpm_widthu                              => 4,
488
                lpm_numwords                    => 16,
489 204 jguarin200
                lpm_showahead                   => "ON",
490
                lpm_width                               => 32,
491
                overflow_checking               => "ON",
492
                underflow_checking              => "ON",
493 228 jguarin200
                use_eab                                 => "ON"
494 204 jguarin200
        )
495
        port    map (
496 212 jguarin200
                sclr            => '0',
497
                clock           => clk,
498 228 jguarin200
                rdreq           => ssync_chain(13),
499 242 jguarin200
                wrreq           => ssync_chain(5),
500 229 jguarin200
                data            => sp2,
501
                q                       => sq0_q
502 204 jguarin200
        );
503 212 jguarin200
        --! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.  
504 228 jguarin200
        q2 : scfifo --! Debe ir registrada la salida.
505 212 jguarin200
        generic map (
506
                allow_rwcycle_when_full => "ON",
507 229 jguarin200
                lpm_widthu                              => 4,
508
                lpm_numwords                    => 16,
509 212 jguarin200
                lpm_showahead                   => "ON",
510
                lpm_type                                => "SCIFIFO",
511
                lpm_width                               => 32,
512
                overflow_checking               => "ON",
513
                underflow_checking              => "ON",
514 228 jguarin200
                use_eab                                 => "ON"
515 212 jguarin200
        )
516
        port map (
517 248 jguarin200
                rdreq           => ssync_chain(28),
518 212 jguarin200
                sclr            => '0',
519
                clock           => clk,
520 228 jguarin200
                empty           => sq2_e,
521 229 jguarin200
                q                       => sqr_dsc,
522 228 jguarin200
                wrreq           => sq2_w,
523
                data            => sq2_d
524 212 jguarin200
        );
525 123 jguarin200
 
526 204 jguarin200
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
527 229 jguarin200
        qx : scfifo
528 204 jguarin200
        generic map (
529 212 jguarin200
                allow_rwcycle_when_full => "ON",
530
                lpm_widthu                              => 5,
531 204 jguarin200
                lpm_numwords                    => 32,
532 212 jguarin200
                lpm_showahead                   => "ON",
533 229 jguarin200
                lpm_width                               => 32,
534 204 jguarin200
                overflow_checking               => "ON",
535
                underflow_checking              => "ON",
536
                use_eab                                 => "ON"
537
        )
538
        port    map (
539
                aclr            => '0',
540
                clock           => clk,
541 229 jguarin200
                empty           => sq1_e,
542 248 jguarin200
                rdreq           => ssync_chain(23+adder1_delay),
543 212 jguarin200
                wrreq           => sync_chain_1,
544 229 jguarin200
                data            => ax,
545
                q                       => sqx_q
546 204 jguarin200
        );
547 229 jguarin200
        qy : scfifo
548
        generic map (
549
                allow_rwcycle_when_full => "ON",
550
                lpm_widthu                              => 5,
551
                lpm_numwords                    => 32,
552
                lpm_showahead                   => "ON",
553
                lpm_width                               => 32,
554
                overflow_checking               => "ON",
555
                underflow_checking              => "ON",
556
                use_eab                                 => "ON"
557
        )
558
        port    map (
559
                aclr            => '0',
560
                clock           => clk,
561 248 jguarin200
                rdreq           => ssync_chain(23+adder1_delay),
562 229 jguarin200
                wrreq           => sync_chain_1,
563
                data            => ay,
564
                q                       => sqy_q
565
        );
566
        qz : scfifo
567
        generic map (
568
                allow_rwcycle_when_full => "ON",
569
                lpm_widthu                              => 5,
570
                lpm_numwords                    => 32,
571
                lpm_showahead                   => "ON",
572
                lpm_width                               => 32,
573
                overflow_checking               => "ON",
574
                underflow_checking              => "ON",
575
                use_eab                                 => "ON"
576
        )
577
        port    map (
578
                aclr            => '0',
579
                clock           => clk,
580 248 jguarin200
                rdreq           => ssync_chain(23+adder1_delay),
581 229 jguarin200
                wrreq           => sync_chain_1,
582
                data            => az,
583
                q                       => sqz_q
584
        );
585
--!***********************************************************************************************************
586
--!Q RESULT
587
--!***********************************************************************************************************
588 196 jguarin200
 
589 229 jguarin200
        --Colas de resultados
590
        rx : scfifo
591
        generic map (
592
                allow_rwcycle_when_full => "ON",
593
                lpm_widthu                              => 5,
594
                lpm_numwords                    => 32,
595
                lpm_showahead                   => "ON",
596
                lpm_width                               => 32,
597
                overflow_checking               => "ON",
598
                underflow_checking              => "ON",
599
                use_eab                                 => "ON"
600
        )
601
        port    map (
602
                aclr            => '0',
603
                clock           => clk,
604
                empty           => sqr_e,
605
                rdreq           => ack,
606
                wrreq           => sqr_w,
607
                data            => sqr_dx,
608
                q                       => vx
609
        );
610
        ry : scfifo
611
        generic map (
612
                allow_rwcycle_when_full => "ON",
613
                lpm_widthu                              => 5,
614
                lpm_numwords                    => 32,
615
                lpm_showahead                   => "ON",
616
                lpm_width                               => 32,
617
                overflow_checking               => "ON",
618
                underflow_checking              => "ON",
619
                use_eab                                 => "ON"
620
        )
621
        port    map (
622
                aclr            => '0',
623
                clock           => clk,
624
                rdreq           => ack,
625
                wrreq           => sqr_w,
626
                data            => sqr_dy,
627
                q                       => vy
628
        );
629
        rz : scfifo
630
        generic map (
631
                allow_rwcycle_when_full => "ON",
632
                lpm_widthu                              => 5,
633
                lpm_numwords                    => 32,
634
                lpm_showahead                   => "ON",
635
                lpm_width                               => 32,
636
                overflow_checking               => "ON",
637
                underflow_checking              => "ON",
638
                use_eab                                 => "ON"
639
        )
640
        port    map (
641
                aclr            => '0',
642
                clock           => clk,
643
                rdreq           => ack,
644
                wrreq           => sqr_w,
645
                data            => sqr_dz,
646
                q                       => vz
647
        );
648
        rsc : scfifo
649
        generic map (
650
                allow_rwcycle_when_full => "ON",
651
                lpm_widthu                              => 5,
652
                lpm_numwords                    => 32,
653
                lpm_showahead                   => "ON",
654
                lpm_width                               => 32,
655
                overflow_checking               => "ON",
656
                underflow_checking              => "ON",
657
                use_eab                                 => "ON"
658
        )
659
        port    map (
660
                aclr            => '0',
661
                clock           => clk,
662
                rdreq           => ack,
663
                wrreq           => sqr_w,
664
                data            => sqr_dsc,
665
                q                       => sc
666
        );
667 204 jguarin200
 
668
 
669 153 jguarin200
end architecture;

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