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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac_hw.tcl] - Blame information for rev 232

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# TCL File Generated by Component Editor 11.0
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# Thu Aug 30 11:19:35 COT 2012
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# DO NOT MODIFY
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# +-----------------------------------
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# | 
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# | raytrac "raytrac" v1.0
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# | null 2012.08.30.11:19:35
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# | 
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# | 
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# | J:/code/hworkspace/raytrac/fp_sgdma/raytrac.vhd
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# | 
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# |    ./raytrac.vhd syn
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# |    ./arithpack.vhd syn
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | request TCL package from ACDS 11.0
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# | 
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package require -exact sopc 11.0
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | module raytrac
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# | 
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set_module_property NAME raytrac
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property DISPLAY_NAME raytrac
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set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd
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set_module_property TOP_LEVEL_HDL_MODULE raytrac
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL TRUE
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set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""
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set_module_property FIX_110_VIP_PATH false
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | files
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# | 
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add_file raytrac.vhd SYNTHESIS
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add_file arithpack.vhd SYNTHESIS
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | parameters
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# | 
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add_parameter wd INTEGER 32
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set_parameter_property wd DEFAULT_VALUE 32
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set_parameter_property wd DISPLAY_NAME wd
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set_parameter_property wd TYPE INTEGER
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set_parameter_property wd UNITS None
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set_parameter_property wd AFFECTS_GENERATION false
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set_parameter_property wd HDL_PARAMETER true
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add_parameter fd INTEGER 8
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set_parameter_property fd DEFAULT_VALUE 8
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set_parameter_property fd DISPLAY_NAME fd
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set_parameter_property fd TYPE INTEGER
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set_parameter_property fd UNITS None
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set_parameter_property fd AFFECTS_GENERATION false
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set_parameter_property fd HDL_PARAMETER true
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add_parameter mb INTEGER 4
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set_parameter_property mb DEFAULT_VALUE 4
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set_parameter_property mb DISPLAY_NAME mb
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set_parameter_property mb TYPE INTEGER
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set_parameter_property mb UNITS None
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set_parameter_property mb AFFECTS_GENERATION false
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set_parameter_property mb HDL_PARAMETER true
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | display items
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# | 
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | connection point clock
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# | 
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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add_interface_port clock clk clk Input 1
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | connection point rtSlave
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# | 
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add_interface rtSlave avalon end
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set_interface_property rtSlave addressAlignment DYNAMIC
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set_interface_property rtSlave addressUnits WORDS
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set_interface_property rtSlave associatedClock clock
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set_interface_property rtSlave associatedReset reset_sink
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set_interface_property rtSlave burstOnBurstBoundariesOnly false
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set_interface_property rtSlave explicitAddressSpan 0
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set_interface_property rtSlave holdTime 0
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set_interface_property rtSlave isMemoryDevice false
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set_interface_property rtSlave isNonVolatileStorage false
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set_interface_property rtSlave linewrapBursts false
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set_interface_property rtSlave maximumPendingReadTransactions 0
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set_interface_property rtSlave printableDevice false
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set_interface_property rtSlave readLatency 2
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set_interface_property rtSlave readWaitStates 0
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set_interface_property rtSlave readWaitTime 0
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set_interface_property rtSlave setupTime 0
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set_interface_property rtSlave timingUnits Cycles
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set_interface_property rtSlave writeWaitTime 0
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set_interface_property rtSlave ENABLED true
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add_interface_port rtSlave slave_address address Input 4
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add_interface_port rtSlave slave_read read Input 1
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add_interface_port rtSlave slave_write write Input 1
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add_interface_port rtSlave slave_readdata readdata Output 32
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add_interface_port rtSlave slave_writedata writedata Input 32
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | connection point rtMaster
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# | 
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add_interface rtMaster avalon start
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set_interface_property rtMaster addressUnits SYMBOLS
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set_interface_property rtMaster associatedClock clock
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set_interface_property rtMaster associatedReset reset_sink
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set_interface_property rtMaster burstOnBurstBoundariesOnly false
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set_interface_property rtMaster doStreamReads false
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set_interface_property rtMaster doStreamWrites false
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set_interface_property rtMaster linewrapBursts false
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set_interface_property rtMaster readLatency 0
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set_interface_property rtMaster ENABLED true
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add_interface_port rtMaster master_address address Output 32
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add_interface_port rtMaster master_waitrequest waitrequest Input 1
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add_interface_port rtMaster master_burstcount burstcount Output 5
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add_interface_port rtMaster master_read read Output 1
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add_interface_port rtMaster master_readdata readdata Input 32
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add_interface_port rtMaster master_readdatavalid readdatavalid Input 1
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add_interface_port rtMaster master_write write Output 1
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add_interface_port rtMaster master_writedata writedata Output 32
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | connection point interrupt_sender
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# | 
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint rtSlave
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set_interface_property interrupt_sender associatedClock clock
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set_interface_property interrupt_sender associatedReset reset_sink
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set_interface_property interrupt_sender ENABLED true
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add_interface_port interrupt_sender irq irq Output 1
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# | 
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# +-----------------------------------
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# +-----------------------------------
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# | connection point reset_sink
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# | 
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges BOTH
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set_interface_property reset_sink ENABLED true
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add_interface_port reset_sink rst reset_n Input 1
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# | 
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# +-----------------------------------

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