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[/] [sata_phy/] [trunk/] [hdl/] [sata_phy_top_x6series.v] - Blame information for rev 13

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////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used
// only as authorized by a licensing agreement from
// Bean Digital Ltd
// In the event of publication, the following notice is
// applicable:
//
// (C)COPYRIGHT 2012 BEAN DIGITAL LTD.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all
// authorized copies.
//
// File        : sata_phy_top_x6series.v
// Author      : J.Bean
// Date        : Mar 2012
// Description : SATA PHY Layer Top Xilinx 6 Series
////////////////////////////////////////////////////////////
 
`resetall
`timescale 1ns/10ps
 
`include "sata_constants.v"
 
module sata_phy_top_x6series
  #(parameter DATA_BITS = 32,                         // Data Bits
    parameter IS_HOST   = 1,                          // 1 = Host, 0 = Device  
    parameter SATA_REV  = 1)(                         // SATA Revision (1, 2, 3)
  input  wire                     clk,                // Clock
  input  wire                     clk_phy,            // Clock PHY
  input  wire                     rst_n,              // Reset
  // Link Transmit
  input  wire [DATA_BITS-1:0]     lnk_tx_tdata_i,     // Link Transmit Data 
  input  wire                     lnk_tx_tvalid_i,    // Link Transmit Source Ready 
  output wire                     lnk_tx_tready_o,    // Link Transmit Destination Ready
  input  wire [3:0]               lnk_tx_tuser_i,     // Link Transmit User
  // Link Receive
  output wire [DATA_BITS-1:0]     lnk_rx_tdata_o,     // Link Receive Data 
  output wire                     lnk_rx_tvalid_o,    // Link Receive Source Ready     
  input  wire                     lnk_rx_tready_i,    // Link Receive Destination Ready     
  output wire [7:0]               lnk_rx_tuser_o,     // Link Receive User    
  // Status
  output wire [7:0]               phy_status_o,       // PHY Status      
  // Transceiver
  input  wire                     gt_rst_done_i,      // GT Reset Done
  input  wire [15:0]              gt_rx_data_i,       // GT Receive Data
  input  wire [1:0]               gt_rx_charisk_i,    // GT Receive K/D
  input  wire [1:0]               gt_rx_disp_err_i,   // GT Receive Disparity Error
  input  wire [1:0]               gt_rx_8b10b_err_i,  // GT Receive 8b10b Error
  input  wire                     gt_rx_elec_idle_i,  // GT Receive Electrical Idle
  input  wire [2:0]               gt_rx_status_i,     // GT Receive Status     
  output wire [15:0]              gt_tx_data_o,       // GT Transmit Data
  output wire [1:0]               gt_tx_charisk_o,    // GT Transmit K/D
  output wire                     gt_tx_elec_idle_o,  // GT Transmit Electrical Idle
  output wire                     gt_tx_com_strt_o,   // GT Transmit Com Start 
  output wire                     gt_tx_com_type_o    // GT Transmit Com Type
);
 
////////////////////////////////////////////////////////////
// Signals
//////////////////////////////////////////////////////////// 
 
wire                 link_up;         // Link Up
reg                  tx_data_mux_sel; // Transmit Mux Data Select
reg  [7:0]           rx_data_mux_sel; // Receive Mux Data Select
wire [31:0]          gt_rx_data;      // GT Receive Data
reg  [31:0]          gt_rx_data_r;    // GT Receive Data
wire [3:0]           gt_rx_charisk;   // GT Receive K/D
reg  [3:0]           gt_rx_charisk_r; // GT Receive K/D
wire [3:0]           gt_rx_err;       // GT Receive Error
reg  [3:0]           gt_rx_err_r;     // GT Receive Error
reg                  gt_rx_valid;     // GT Receive Valid
reg  [47:0]          gt_rx_data_sr;   // GT Receive Data Shift Reg
reg  [5:0]           gt_rx_k_sr;      // GT Receive K/D Shift Reg
reg  [5:0]           gt_rx_err_sr;    // GT Receive Error Shift Reg
wire [31:0]          gt_tx_data;      // GT Transmit Data
wire [3:0]           gt_tx_charisk;   // GT Transmit K/D
wire [DATA_BITS-1:0] lnk_tx_tdata;    // Link Transmit Data
wire                 lnk_tx_tvalid;   // Link Transmit Source Ready  
reg                  lnk_tx_tready;   // Link Transmit Destination Ready
wire [3:0]           lnk_tx_tuser;    // Link Transmit User 
wire [DATA_BITS-1:0] lnk_rx_tdata;    // Link Receive Data
wire                 lnk_rx_tvalid;   // Link Receive Source Ready  
wire                 lnk_rx_tready;   // Link Receive Destination Ready
wire [7:0]           lnk_rx_tuser;    // Link Receive User
 
////////////////////////////////////////////////////////////
// Comb Assign : PHY Status
// Description : 
////////////////////////////////////////////////////////////
 
assign phy_status_o = {7'd0, link_up};
 
////////////////////////////////////////////////////////////
// Comb Assign : Port Signals
// Description : 
////////////////////////////////////////////////////////////
 
assign lnk_rx_tdata      = gt_rx_data_r;
assign lnk_rx_tvalid     = gt_rx_valid;
assign lnk_rx_tuser[3:0] = gt_rx_charisk_r;
assign lnk_rx_tuser[7:4] = gt_rx_err_r;
 
////////////////////////////////////////////////////////////
// Instance    : PHY Transmit FIFO
// Description : 
////////////////////////////////////////////////////////////
 
axis_fifo_36W_16D U_phy_tx_fifo(
  .m_aclk        (clk_phy),
  .s_aclk        (clk),
  .s_aresetn     (rst_n),
  .s_axis_tdata  (lnk_tx_tdata_i),
  .s_axis_tuser  (lnk_tx_tuser_i),
  .s_axis_tvalid (lnk_tx_tvalid_i),
  .s_axis_tready (lnk_tx_tready_o),
  .m_axis_tdata  (lnk_tx_tdata),
  .m_axis_tuser  (lnk_tx_tuser),
  .m_axis_tvalid (lnk_tx_tvalid),
  .m_axis_tready (lnk_tx_tready));
 
////////////////////////////////////////////////////////////
// Instance    : PHY Receive FIFO
// Description : 
////////////////////////////////////////////////////////////
 
axis_fifo_40W_16D U_phy_rx_fifo(
  .m_aclk        (clk),
  .s_aclk        (clk_phy),
  .s_aresetn     (rst_n),
  .s_axis_tdata  (lnk_rx_tdata),
  .s_axis_tuser  (lnk_rx_tuser),
  .s_axis_tvalid (lnk_rx_tvalid),
  .s_axis_tready (lnk_rx_tready),
  .m_axis_tdata  (lnk_rx_tdata_o),
  .m_axis_tuser  (lnk_rx_tuser_o),
  .m_axis_tvalid (lnk_rx_tvalid_o),
  .m_axis_tready (lnk_rx_tready_i));
 
////////////////////////////////////////////////////////////
// Instance    : GT Receive Data
// Description : 
////////////////////////////////////////////////////////////
 
mux #(
  .DATA_BITS  (DATA_BITS),
  .IP_NUM     (2),
  .USE_OP_REG (0))
  U_rx_data_mux(
  .clk        (clk_phy),
  .data_i     ({gt_rx_data_sr[39:8], gt_rx_data_sr[31:0]}),
  .sel_i      (rx_data_mux_sel),
  .data_o     (gt_rx_data));
 
////////////////////////////////////////////////////////////
// Instance    : GT Receive K/D
// Description : 
////////////////////////////////////////////////////////////
 
mux #(
  .DATA_BITS  (4),
  .IP_NUM     (2),
  .USE_OP_REG (0))
  U_rx_charisk_mux(
  .clk        (clk_phy),
  .data_i     ({gt_rx_k_sr[4:1], gt_rx_k_sr[3:0]}),
  .sel_i      (rx_data_mux_sel),
  .data_o     (gt_rx_charisk));
 
////////////////////////////////////////////////////////////
// Instance    : GT Receive Error
// Description : 
////////////////////////////////////////////////////////////
 
mux #(
  .DATA_BITS  (4),
  .IP_NUM     (2),
  .USE_OP_REG (0))
  U_rx_err_mux(
  .clk        (clk_phy),
  .data_i     ({gt_rx_err_sr[4:1], gt_rx_err_sr[3:0]}),
  .sel_i      (rx_data_mux_sel),
  .data_o     (gt_rx_err));
 
////////////////////////////////////////////////////////////
// Instance    : GT Transmit Data
// Description : 
////////////////////////////////////////////////////////////
 
mux #(
  .DATA_BITS  (16),
  .IP_NUM     (4),
  .USE_OP_REG (1))
  U_txdata_mux(
  .clk        (clk_phy),
  .data_i     ({lnk_tx_tdata[31:16], lnk_tx_tdata[15:0], gt_tx_data[31:16], gt_tx_data[15:0]}),
  .sel_i      ({6'd0, link_up, tx_data_mux_sel}),
  .data_o     (gt_tx_data_o));
 
////////////////////////////////////////////////////////////
// Instance    : GT Transmit K/D
// Description : 
////////////////////////////////////////////////////////////
 
mux #(
  .DATA_BITS  (2),
  .IP_NUM     (4),
  .USE_OP_REG (1))
  U_txcharisk_mux(
  .clk        (clk_phy),
  .data_i     ({lnk_tx_tuser[3:2], lnk_tx_tuser[1:0], gt_tx_charisk[3:2], gt_tx_charisk[1:0]}),
  .sel_i      ({6'd0, link_up, tx_data_mux_sel}),
  .data_o     (gt_tx_charisk_o));
 
////////////////////////////////////////////////////////////
// Instance    : SATA Spartan 6 PHY Control
// Description : 
////////////////////////////////////////////////////////////
 
generate
  if (IS_HOST == 1) begin
    sata_phy_host_ctrl_x6series #(
      .SATA_REV          (SATA_REV))
      U_phy_host_ctrl_x6series(
      .clk_phy           (clk_phy),
      .rst_n                               (rst_n),
      .link_up_o         (link_up),
      .gt_rst_done_i     (gt_rst_done_i),
      .gt_tx_data_o      (gt_tx_data),
      .gt_tx_charisk_o   (gt_tx_charisk),
      .gt_tx_com_strt_o  (gt_tx_com_strt_o),
      .gt_tx_com_type_o  (gt_tx_com_type_o),
      .gt_tx_elec_idle_o (gt_tx_elec_idle_o),
      .gt_rx_data_i      (lnk_rx_tdata_o),
      .gt_rx_status_i    (gt_rx_status_i),
      .gt_rx_elec_idle_i (gt_rx_elec_idle_i));
  end else begin
    sata_phy_dev_ctrl_x6series #(
      .SATA_REV          (SATA_REV))
      U_phy_dev_ctrl_x6series(
      .clk_phy           (clk_phy),
      .rst_n                               (rst_n),
      .link_up_o         (link_up),
      .gt_rst_done_i     (gt_rst_done_i),
      .gt_tx_data_o      (gt_tx_data),
      .gt_tx_charisk_o   (gt_tx_charisk),
      .gt_tx_com_strt_o  (gt_tx_com_strt_o),
      .gt_tx_com_type_o  (gt_tx_com_type_o),
      .gt_tx_elec_idle_o (gt_tx_elec_idle_o),
      .gt_rx_data_i      (lnk_rx_tdata_o),
      .gt_rx_status_i    (gt_rx_status_i));
  end
endgenerate
 
////////////////////////////////////////////////////////////
// Seq Block   : Receive Data Shift Register
// Description : 
////////////////////////////////////////////////////////////
 
always@(posedge clk_phy)
begin
  gt_rx_data_sr[47:32] <= gt_rx_data_i;
  gt_rx_data_sr[31:0]  <= gt_rx_data_sr[47:16];
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Receive K Shift Register
// Description : 
////////////////////////////////////////////////////////////
 
always@(posedge clk_phy)
begin
  gt_rx_k_sr[5:4] <= gt_rx_charisk_i;
  gt_rx_k_sr[3:0] <= gt_rx_k_sr[5:2];
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Receive Error Shift Register
// Description : 
////////////////////////////////////////////////////////////
 
always@(posedge clk_phy)
begin
  gt_rx_err_sr[4]   <= gt_rx_disp_err_i[0] | gt_rx_8b10b_err_i[0];
  gt_rx_err_sr[5]   <= gt_rx_disp_err_i[1] | gt_rx_8b10b_err_i[1];
  gt_rx_err_sr[3:0] <= gt_rx_err_sr[5:2];
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Link Transmit Desrination Ready
// Description : 
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    lnk_tx_tready <= 0;
  end else begin
    if (lnk_tx_tready == 0) begin
      lnk_tx_tready <= 1;
    end else begin
      lnk_tx_tready <= 0;
    end
  end
end
 
////////////////////////////////////////////////////////////
// Comb Block  : Transmit Mux Data Select
// Description : Selects 16-bit data to send to the transceiver
//               from the 32-bit data on the mux input.
////////////////////////////////////////////////////////////
 
always @(*)
begin
  if ((lnk_tx_tvalid == 1) && (lnk_tx_tready == 1)) begin
    tx_data_mux_sel = 0;
  end else begin
    tx_data_mux_sel = 1;
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : Receive Mux Data Select
// Description : Determines the location of the data in the 
//               GT receive data, and then sets the select.
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    rx_data_mux_sel <= 0;
  end else begin
    // Test for the ALIGN primitive in bits 31:0
    if ((gt_rx_k_sr[3:0] == 4'b0001) && (gt_rx_data_sr[31:0] == `ALIGN_VAL)) begin
      rx_data_mux_sel <= 0;
    end else begin
      // Test for the ALIGN primitive in bits 39:8
      if ((gt_rx_k_sr[4:1] == 4'b0001) && (gt_rx_data_sr[39:8] == `ALIGN_VAL)) begin
        rx_data_mux_sel <= 1;
      end
    end
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Receive Valid
// Description : Indicates when the data is valid. It is 
//               synchronised to the ALIGN primitive.
////////////////////////////////////////////////////////////
 
always @(negedge rst_n or posedge clk_phy)
begin
  if (rst_n == 0) begin
    gt_rx_valid <= 0;
  end   else begin
    if ((gt_rx_charisk == 4'b0001) && (gt_rx_data == `ALIGN_VAL)) begin
      gt_rx_valid <= 1;
    end else begin
      if (gt_rx_valid == 1) begin
        gt_rx_valid <= 0;
      end else begin
        gt_rx_valid <= 1;
      end
    end
  end
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Receive Data
// Description :
////////////////////////////////////////////////////////////
 
always @(posedge clk_phy)
begin
  gt_rx_data_r <= gt_rx_data;
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Receive K/D
// Description :
////////////////////////////////////////////////////////////
 
always @(posedge clk_phy)
begin
  gt_rx_charisk_r <= gt_rx_charisk;
end
 
////////////////////////////////////////////////////////////
// Seq Block   : GT Receive Error
// Description :
////////////////////////////////////////////////////////////
 
always @(posedge clk_phy)
begin
  gt_rx_err_r <= gt_rx_err;
end
 
endmodule

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Subversion Repositories sata_phy

[/] [sata_phy/] [trunk/] [hdl/] [sata_phy_top_x6series.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	beandigita	`////////////////////////////////////////////////////////////`
2			`//`
3			`// This confidential and proprietary software may be used`
4			`// only as authorized by a licensing agreement from`
5			`// Bean Digital Ltd`
6			`// In the event of publication, the following notice is`
7			`// applicable:`
8			`//`
9			`// (C)COPYRIGHT 2012 BEAN DIGITAL LTD.`
10			`// ALL RIGHTS RESERVED`
11			`//`
12			`// The entire notice above must be reproduced on all`
13			`// authorized copies.`
14			`//`
15			`// File : sata_phy_top_x6series.v`
16			`// Author : J.Bean`
17			`// Date : Mar 2012`
18			`// Description : SATA PHY Layer Top Xilinx 6 Series`
19			`////////////////////////////////////////////////////////////`
20
21			`resetall
22			`timescale 1ns/10ps
23
24			`include "sata_constants.v"
25
26			`module sata_phy_top_x6series`
27			`#(parameter DATA_BITS = 32, // Data Bits`
28			`parameter IS_HOST = 1, // 1 = Host, 0 = Device`
29			`parameter SATA_REV = 1)( // SATA Revision (1, 2, 3)`
30			`input wire clk, // Clock`
31			`input wire clk_phy, // Clock PHY`
32			`input wire rst_n, // Reset`
33			`// Link Transmit`
34			`input wire [DATA_BITS-1:0] lnk_tx_tdata_i, // Link Transmit Data`
35			`input wire lnk_tx_tvalid_i, // Link Transmit Source Ready`
36			`output wire lnk_tx_tready_o, // Link Transmit Destination Ready`
37			`input wire [3:0] lnk_tx_tuser_i, // Link Transmit User`
38			`// Link Receive`
39			`output wire [DATA_BITS-1:0] lnk_rx_tdata_o, // Link Receive Data`
40			`output wire lnk_rx_tvalid_o, // Link Receive Source Ready`
41			`input wire lnk_rx_tready_i, // Link Receive Destination Ready`
42			`output wire [7:0] lnk_rx_tuser_o, // Link Receive User`
43			`// Status`
44			`output wire [7:0] phy_status_o, // PHY Status`
45			`// Transceiver`
46			`input wire gt_rst_done_i, // GT Reset Done`
47			`input wire [15:0] gt_rx_data_i, // GT Receive Data`
48			`input wire [1:0] gt_rx_charisk_i, // GT Receive K/D`
49			`input wire [1:0] gt_rx_disp_err_i, // GT Receive Disparity Error`
50			`input wire [1:0] gt_rx_8b10b_err_i, // GT Receive 8b10b Error`
51			`input wire gt_rx_elec_idle_i, // GT Receive Electrical Idle`
52			`input wire [2:0] gt_rx_status_i, // GT Receive Status`
53			`output wire [15:0] gt_tx_data_o, // GT Transmit Data`
54			`output wire [1:0] gt_tx_charisk_o, // GT Transmit K/D`
55			`output wire gt_tx_elec_idle_o, // GT Transmit Electrical Idle`
56			`output wire gt_tx_com_strt_o, // GT Transmit Com Start`
57			`output wire gt_tx_com_type_o // GT Transmit Com Type`
58			`);`
59
60			`////////////////////////////////////////////////////////////`
61			`// Signals`
62			`////////////////////////////////////////////////////////////`
63
64			`wire link_up; // Link Up`
65			`reg tx_data_mux_sel; // Transmit Mux Data Select`
66			`reg [7:0] rx_data_mux_sel; // Receive Mux Data Select`
67			`wire [31:0] gt_rx_data; // GT Receive Data`
68			`reg [31:0] gt_rx_data_r; // GT Receive Data`
69			`wire [3:0] gt_rx_charisk; // GT Receive K/D`
70			`reg [3:0] gt_rx_charisk_r; // GT Receive K/D`
71			`wire [3:0] gt_rx_err; // GT Receive Error`
72			`reg [3:0] gt_rx_err_r; // GT Receive Error`
73			`reg gt_rx_valid; // GT Receive Valid`
74			`reg [47:0] gt_rx_data_sr; // GT Receive Data Shift Reg`
75			`reg [5:0] gt_rx_k_sr; // GT Receive K/D Shift Reg`
76			`reg [5:0] gt_rx_err_sr; // GT Receive Error Shift Reg`
77			`wire [31:0] gt_tx_data; // GT Transmit Data`
78			`wire [3:0] gt_tx_charisk; // GT Transmit K/D`
79			`wire [DATA_BITS-1:0] lnk_tx_tdata; // Link Transmit Data`
80			`wire lnk_tx_tvalid; // Link Transmit Source Ready`
81			`reg lnk_tx_tready; // Link Transmit Destination Ready`
82			`wire [3:0] lnk_tx_tuser; // Link Transmit User`
83			`wire [DATA_BITS-1:0] lnk_rx_tdata; // Link Receive Data`
84			`wire lnk_rx_tvalid; // Link Receive Source Ready`
85			`wire lnk_rx_tready; // Link Receive Destination Ready`
86			`wire [7:0] lnk_rx_tuser; // Link Receive User`
87
88			`////////////////////////////////////////////////////////////`
89			`// Comb Assign : PHY Status`
90			`// Description :`
91			`////////////////////////////////////////////////////////////`
92
93			`assign phy_status_o = {7'd0, link_up};`
94
95			`////////////////////////////////////////////////////////////`
96			`// Comb Assign : Port Signals`
97			`// Description :`
98			`////////////////////////////////////////////////////////////`
99
100			`assign lnk_rx_tdata = gt_rx_data_r;`
101			`assign lnk_rx_tvalid = gt_rx_valid;`
102			`assign lnk_rx_tuser[3:0] = gt_rx_charisk_r;`
103			`assign lnk_rx_tuser[7:4] = gt_rx_err_r;`
104
105			`////////////////////////////////////////////////////////////`
106			`// Instance : PHY Transmit FIFO`
107			`// Description :`
108			`////////////////////////////////////////////////////////////`
109
110			`axis_fifo_36W_16D U_phy_tx_fifo(`
111			`.m_aclk (clk_phy),`
112			`.s_aclk (clk),`
113			`.s_aresetn (rst_n),`
114			`.s_axis_tdata (lnk_tx_tdata_i),`
115			`.s_axis_tuser (lnk_tx_tuser_i),`
116			`.s_axis_tvalid (lnk_tx_tvalid_i),`
117			`.s_axis_tready (lnk_tx_tready_o),`
118			`.m_axis_tdata (lnk_tx_tdata),`
119			`.m_axis_tuser (lnk_tx_tuser),`
120			`.m_axis_tvalid (lnk_tx_tvalid),`
121			`.m_axis_tready (lnk_tx_tready));`
122
123			`////////////////////////////////////////////////////////////`
124			`// Instance : PHY Receive FIFO`
125			`// Description :`
126			`////////////////////////////////////////////////////////////`
127
128			`axis_fifo_40W_16D U_phy_rx_fifo(`
129			`.m_aclk (clk),`
130			`.s_aclk (clk_phy),`
131			`.s_aresetn (rst_n),`
132			`.s_axis_tdata (lnk_rx_tdata),`
133			`.s_axis_tuser (lnk_rx_tuser),`
134			`.s_axis_tvalid (lnk_rx_tvalid),`
135			`.s_axis_tready (lnk_rx_tready),`
136			`.m_axis_tdata (lnk_rx_tdata_o),`
137			`.m_axis_tuser (lnk_rx_tuser_o),`
138			`.m_axis_tvalid (lnk_rx_tvalid_o),`
139			`.m_axis_tready (lnk_rx_tready_i));`
140
141			`////////////////////////////////////////////////////////////`
142			`// Instance : GT Receive Data`
143			`// Description :`
144			`////////////////////////////////////////////////////////////`
145
146			`mux #(`
147			`.DATA_BITS (DATA_BITS),`
148			`.IP_NUM (2),`
149			`.USE_OP_REG (0))`
150			`U_rx_data_mux(`
151			`.clk (clk_phy),`
152			`.data_i ({gt_rx_data_sr[39:8], gt_rx_data_sr[31:0]}),`
153			`.sel_i (rx_data_mux_sel),`
154			`.data_o (gt_rx_data));`
155
156			`////////////////////////////////////////////////////////////`
157			`// Instance : GT Receive K/D`
158			`// Description :`
159			`////////////////////////////////////////////////////////////`
160
161			`mux #(`
162			`.DATA_BITS (4),`
163			`.IP_NUM (2),`
164			`.USE_OP_REG (0))`
165			`U_rx_charisk_mux(`
166			`.clk (clk_phy),`
167			`.data_i ({gt_rx_k_sr[4:1], gt_rx_k_sr[3:0]}),`
168			`.sel_i (rx_data_mux_sel),`
169			`.data_o (gt_rx_charisk));`
170
171			`////////////////////////////////////////////////////////////`
172			`// Instance : GT Receive Error`
173			`// Description :`
174			`////////////////////////////////////////////////////////////`
175
176			`mux #(`
177			`.DATA_BITS (4),`
178			`.IP_NUM (2),`
179			`.USE_OP_REG (0))`
180			`U_rx_err_mux(`
181			`.clk (clk_phy),`
182			`.data_i ({gt_rx_err_sr[4:1], gt_rx_err_sr[3:0]}),`
183			`.sel_i (rx_data_mux_sel),`
184			`.data_o (gt_rx_err));`
185
186			`////////////////////////////////////////////////////////////`
187			`// Instance : GT Transmit Data`
188			`// Description :`
189			`////////////////////////////////////////////////////////////`
190
191			`mux #(`
192			`.DATA_BITS (16),`
193			`.IP_NUM (4),`
194			`.USE_OP_REG (1))`
195			`U_txdata_mux(`
196			`.clk (clk_phy),`
197			`.data_i ({lnk_tx_tdata[31:16], lnk_tx_tdata[15:0], gt_tx_data[31:16], gt_tx_data[15:0]}),`
198			`.sel_i ({6'd0, link_up, tx_data_mux_sel}),`
199			`.data_o (gt_tx_data_o));`
200
201			`////////////////////////////////////////////////////////////`
202			`// Instance : GT Transmit K/D`
203			`// Description :`
204			`////////////////////////////////////////////////////////////`
205
206			`mux #(`
207			`.DATA_BITS (2),`
208			`.IP_NUM (4),`
209			`.USE_OP_REG (1))`
210			`U_txcharisk_mux(`
211			`.clk (clk_phy),`
212			`.data_i ({lnk_tx_tuser[3:2], lnk_tx_tuser[1:0], gt_tx_charisk[3:2], gt_tx_charisk[1:0]}),`
213			`.sel_i ({6'd0, link_up, tx_data_mux_sel}),`
214			`.data_o (gt_tx_charisk_o));`
215
216			`////////////////////////////////////////////////////////////`
217			`// Instance : SATA Spartan 6 PHY Control`
218			`// Description :`
219			`////////////////////////////////////////////////////////////`
220
221			`generate`
222			`if (IS_HOST == 1) begin`
223			`sata_phy_host_ctrl_x6series #(`
224			`.SATA_REV (SATA_REV))`
225			`U_phy_host_ctrl_x6series(`
226			`.clk_phy (clk_phy),`
227			`.rst_n (rst_n),`
228			`.link_up_o (link_up),`
229			`.gt_rst_done_i (gt_rst_done_i),`
230			`.gt_tx_data_o (gt_tx_data),`
231			`.gt_tx_charisk_o (gt_tx_charisk),`
232			`.gt_tx_com_strt_o (gt_tx_com_strt_o),`
233			`.gt_tx_com_type_o (gt_tx_com_type_o),`
234			`.gt_tx_elec_idle_o (gt_tx_elec_idle_o),`
235			`.gt_rx_data_i (lnk_rx_tdata_o),`
236			`.gt_rx_status_i (gt_rx_status_i),`
237			`.gt_rx_elec_idle_i (gt_rx_elec_idle_i));`
238			`end else begin`
239			`sata_phy_dev_ctrl_x6series #(`
240			`.SATA_REV (SATA_REV))`
241			`U_phy_dev_ctrl_x6series(`
242			`.clk_phy (clk_phy),`
243			`.rst_n (rst_n),`
244			`.link_up_o (link_up),`
245			`.gt_rst_done_i (gt_rst_done_i),`
246			`.gt_tx_data_o (gt_tx_data),`
247			`.gt_tx_charisk_o (gt_tx_charisk),`
248			`.gt_tx_com_strt_o (gt_tx_com_strt_o),`
249			`.gt_tx_com_type_o (gt_tx_com_type_o),`
250			`.gt_tx_elec_idle_o (gt_tx_elec_idle_o),`
251			`.gt_rx_data_i (lnk_rx_tdata_o),`
252			`.gt_rx_status_i (gt_rx_status_i));`
253			`end`
254			`endgenerate`
255
256			`////////////////////////////////////////////////////////////`
257			`// Seq Block : Receive Data Shift Register`
258			`// Description :`
259			`////////////////////////////////////////////////////////////`
260
261			`always@(posedge clk_phy)`
262			`begin`
263			`gt_rx_data_sr[47:32] <= gt_rx_data_i;`
264			`gt_rx_data_sr[31:0] <= gt_rx_data_sr[47:16];`
265			`end`
266
267			`////////////////////////////////////////////////////////////`
268			`// Seq Block : Receive K Shift Register`
269			`// Description :`
270			`////////////////////////////////////////////////////////////`
271
272			`always@(posedge clk_phy)`
273			`begin`
274			`gt_rx_k_sr[5:4] <= gt_rx_charisk_i;`
275			`gt_rx_k_sr[3:0] <= gt_rx_k_sr[5:2];`
276			`end`
277
278			`////////////////////////////////////////////////////////////`
279			`// Seq Block : Receive Error Shift Register`
280			`// Description :`
281			`////////////////////////////////////////////////////////////`
282
283			`always@(posedge clk_phy)`
284			`begin`
285			`gt_rx_err_sr[4] <= gt_rx_disp_err_i[0] \| gt_rx_8b10b_err_i[0];`
286			`gt_rx_err_sr[5] <= gt_rx_disp_err_i[1] \| gt_rx_8b10b_err_i[1];`
287			`gt_rx_err_sr[3:0] <= gt_rx_err_sr[5:2];`
288			`end`
289
290			`////////////////////////////////////////////////////////////`
291			`// Seq Block : Link Transmit Desrination Ready`
292			`// Description :`
293			`////////////////////////////////////////////////////////////`
294
295			`always @(negedge rst_n or posedge clk_phy)`
296			`begin`
297			`if (rst_n == 0) begin`
298			`lnk_tx_tready <= 0;`
299			`end else begin`
300			`if (lnk_tx_tready == 0) begin`
301			`lnk_tx_tready <= 1;`
302			`end else begin`
303			`lnk_tx_tready <= 0;`
304			`end`
305			`end`
306			`end`
307
308			`////////////////////////////////////////////////////////////`
309			`// Comb Block : Transmit Mux Data Select`
310			`// Description : Selects 16-bit data to send to the transceiver`
311			`// from the 32-bit data on the mux input.`
312			`////////////////////////////////////////////////////////////`
313
314			`always @(*)`
315			`begin`
316			`if ((lnk_tx_tvalid == 1) && (lnk_tx_tready == 1)) begin`
317			`tx_data_mux_sel = 0;`
318			`end else begin`
319			`tx_data_mux_sel = 1;`
320			`end`
321			`end`
322
323			`////////////////////////////////////////////////////////////`
324			`// Seq Block : Receive Mux Data Select`
325			`// Description : Determines the location of the data in the`
326			`// GT receive data, and then sets the select.`
327			`////////////////////////////////////////////////////////////`
328
329			`always @(negedge rst_n or posedge clk_phy)`
330			`begin`
331			`if (rst_n == 0) begin`
332			`rx_data_mux_sel <= 0;`
333			`end else begin`
334			`// Test for the ALIGN primitive in bits 31:0`
335			if ((gt_rx_k_sr[3:0] == 4'b0001) && (gt_rx_data_sr[31:0] == `ALIGN_VAL)) begin
336			`rx_data_mux_sel <= 0;`
337			`end else begin`
338			`// Test for the ALIGN primitive in bits 39:8`
339			if ((gt_rx_k_sr[4:1] == 4'b0001) && (gt_rx_data_sr[39:8] == `ALIGN_VAL)) begin
340			`rx_data_mux_sel <= 1;`
341			`end`
342			`end`
343			`end`
344			`end`
345
346			`////////////////////////////////////////////////////////////`
347			`// Seq Block : GT Receive Valid`
348			`// Description : Indicates when the data is valid. It is`
349			`// synchronised to the ALIGN primitive.`
350			`////////////////////////////////////////////////////////////`
351
352			`always @(negedge rst_n or posedge clk_phy)`
353			`begin`
354			`if (rst_n == 0) begin`
355			`gt_rx_valid <= 0;`
356			`end else begin`
357			if ((gt_rx_charisk == 4'b0001) && (gt_rx_data == `ALIGN_VAL)) begin
358			`gt_rx_valid <= 1;`
359			`end else begin`
360			`if (gt_rx_valid == 1) begin`
361			`gt_rx_valid <= 0;`
362			`end else begin`
363			`gt_rx_valid <= 1;`
364			`end`
365			`end`
366			`end`
367			`end`
368
369			`////////////////////////////////////////////////////////////`
370			`// Seq Block : GT Receive Data`
371			`// Description :`
372			`////////////////////////////////////////////////////////////`
373
374			`always @(posedge clk_phy)`
375			`begin`
376			`gt_rx_data_r <= gt_rx_data;`
377			`end`
378
379			`////////////////////////////////////////////////////////////`
380			`// Seq Block : GT Receive K/D`
381			`// Description :`
382			`////////////////////////////////////////////////////////////`
383
384			`always @(posedge clk_phy)`
385			`begin`
386			`gt_rx_charisk_r <= gt_rx_charisk;`
387			`end`
388
389			`////////////////////////////////////////////////////////////`
390			`// Seq Block : GT Receive Error`
391			`// Description :`
392			`////////////////////////////////////////////////////////////`
393
394			`always @(posedge clk_phy)`
395			`begin`
396			`gt_rx_err_r <= gt_rx_err;`
397			`end`
398
399			`endmodule`