OpenCores
URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [01_or1200.yaml] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 feddischso
SOCM_CORE
2 10 feddischso
name: OpenRISC 1200
3 5 feddischso
description: OpenRISC CPU
4 10 feddischso
id: or1200,rel2
5 5 feddischso
license: LGPL
6
licensefile:
7
author:
8
authormail:
9
vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl
10
toplevel: or1200_top
11
interfaces:
12
  :clmode: SOCM_IFC
13
    name: single
14
    dir: 1
15 10 feddischso
    id: single,1
16 5 feddischso
    ports:
17
      :clmode_i: SOCM_PORT
18
        len: 2
19
        defn: single
20
 
21 7 feddischso
  :pic_ints: SOCM_IFC
22 5 feddischso
    name: single
23
    dir: 1
24 10 feddischso
    id: single,1
25 5 feddischso
    ports:
26 7 feddischso
      :pic_ints_i: SOCM_PORT
27
        len: 20
28 5 feddischso
        defn: single
29
 
30
  :clk: SOCM_IFC
31
    name: clk
32
    dir: 1
33 10 feddischso
    id: clk,1
34 5 feddischso
    ports:
35
      :clk_i: SOCM_PORT
36 7 feddischso
        len: 1
37 5 feddischso
        defn: clk
38
 
39
  :rst: SOCM_IFC
40
    name: rst
41
    dir: 1
42 10 feddischso
    id: rst,1
43 5 feddischso
    ports:
44
      :rst_i: SOCM_PORT
45 7 feddischso
        len: 1
46 5 feddischso
        defn: rst
47
 
48
  :wb_instruction: SOCM_IFC
49
    name: wishbone_ma
50
    dir: 1
51 10 feddischso
    id: wishbone_ma,b3
52 5 feddischso
    ports:
53 7 feddischso
      :iwb_clk_i: SOCM_PORT
54
        defn: clk
55
        len:  1
56
      :iwb_rst_i: SOCM_PORT
57
        defn: rst
58
        len:  1
59 5 feddischso
      :iwb_cyc_o: SOCM_PORT
60
        defn: cyc
61
        len:  1
62
      :iwb_stb_o: SOCM_PORT
63
        defn: stb
64
        len:  1
65
      :iwb_adr_o: SOCM_PORT
66
        defn: adr
67
        len:  32
68
      :iwb_sel_o: SOCM_PORT
69
        defn: sel
70 7 feddischso
        len:  4
71 5 feddischso
      :iwb_we_o: SOCM_PORT
72
        defn: we
73
        len:  1
74
      :iwb_dat_o: SOCM_PORT
75
        defn: dat_i
76
        len:  32
77
      :iwb_dat_i: SOCM_PORT
78
        defn: dat_o
79
        len:  32
80
      :iwb_ack_i: SOCM_PORT
81
        defn: ack
82
        len:  1
83
      :iwb_err_i: SOCM_PORT
84
        defn: err
85
        len:  1
86
      :iwb_rty_i: SOCM_PORT
87 7 feddischso
        defn: rty
88 5 feddischso
        len:  1
89
 
90
  :wb_data: SOCM_IFC
91
    name: wishbone_ma
92
    dir: 1
93 10 feddischso
    id: wishbone_ma,b3
94 5 feddischso
    ports:
95 7 feddischso
      :dwb_clk_i: SOCM_PORT
96
        defn: clk
97
        len:  1
98
      :dwb_rst_i: SOCM_PORT
99
        defn: rst
100
        len:  1
101 5 feddischso
      :dwb_cyc_o: SOCM_PORT
102
        defn: cyc
103
        len:  1
104
      :dwb_stb_o: SOCM_PORT
105
        defn: stb
106
        len:  1
107
      :dwb_adr_o: SOCM_PORT
108
        defn: adr
109
        len:  32
110
      :dwb_sel_o: SOCM_PORT
111
        defn: sel
112 7 feddischso
        len:  4
113 5 feddischso
      :dwb_we_o: SOCM_PORT
114
        defn: we
115
        len:  1
116
      :dwb_dat_o: SOCM_PORT
117
        defn: dat_i
118
        len:  32
119
      :dwb_dat_i: SOCM_PORT
120 7 feddischso
        defn: dat_o
121 5 feddischso
        len:  32
122
      :dwb_ack_i: SOCM_PORT
123
        defn: ack
124
        len:  1
125
      :dwb_err_i: SOCM_PORT
126
        defn: err
127
        len:  1
128
      :dwb_rty_i: SOCM_PORT
129 7 feddischso
        defn: rty
130 5 feddischso
        len:  1
131
 
132
  :ext_debug: SOCM_IFC
133
    name: debug
134
    dir: 1
135 10 feddischso
    id: debug,1
136 5 feddischso
    ports:
137
      :dbg_stall_i: SOCM_PORT
138
        defn: dbg_stall
139
        len: 1
140
      :dbg_ewt_i: SOCM_PORT
141
        len: 1
142
        defn: dbg_ewt
143
      :dbg_lss_o: SOCM_PORT
144
        len: 4
145
        defn: dbg_lss
146
      :dbg_is_o: SOCM_PORT
147
        len: 2
148
        defn: dbg_iso
149
      :dbg_wp_o: SOCM_PORT
150
        len: 11
151
        defn: dbg_wpo
152
      :dbg_bp_o: SOCM_PORT
153
        len: 1
154
        defn: dbg_bpo
155
      :dbg_stb_i: SOCM_PORT
156
        len: 1
157
        defn: dbg_stb
158
      :dbg_we_i: SOCM_PORT
159
        len: 1
160
        defn: dbg_we
161
      :dbg_adr_i: SOCM_PORT
162
        len: 32
163
        defn: dbg_adr
164
      :dbg_dat_i: SOCM_PORT
165
        len: 32
166 7 feddischso
        defn: dbg_dat_o
167 5 feddischso
      :dbg_dat_o: SOCM_PORT
168
        len: 32
169 7 feddischso
        defn: dbg_dat_i
170 5 feddischso
      :dbg_ack_o: SOCM_PORT
171
        len: 1
172
        defn: dbg_ack
173
 
174
  :pow_man: SOCM_IFC
175
    name: or_power_management
176
    dir: 1
177 10 feddischso
    id: or_power_management,1
178 5 feddischso
    ports:
179
      :pm_cpustall_i: SOCM_PORT
180
         len: 1
181
         defn: pm_cpustall
182
      :pm_clksd_o: SOCM_PORT
183
         len: 4
184
         defn: pm_clksd
185
      :pm_dc_gate_o: SOCM_PORT
186
         len: 1
187
         defn: pm_dc_gate
188
      :pm_ic_gate_o: SOCM_PORT
189
         len: 1
190
         defn: pm_ic_gate
191
      :pm_dmmu_gate_o: SOCM_PORT
192
         len: 1
193
         defn: pm_dmmu_gate
194
      :pm_immu_gate_o: SOCM_PORT
195
         len: 1
196
         defn: pm_immu_gate
197
      :pm_tt_gate_o: SOCM_PORT
198
         len: 1
199
         defn: pm_tt_gate
200
      :pm_cpu_gate_o: SOCM_PORT
201
         len: 1
202
         defn: pm_cpu_gate
203
      :pm_wakeup_o: SOCM_PORT
204
         len: 1
205
         defn: pm_wakeup
206
      :pm_lvolt_o: SOCM_PORT
207
         len: 1
208
         defn: pm_lvolt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.