Subversion Repositories soc_maker

SOCM_CORE

name: or1200

description: OpenRISC CPU

version: rel2

license: LGPL

licensefile:

author:

authormail:

vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl

toplevel: or1200_top

interfaces:

  :clmode: SOCM_IFC

    name: single

    dir: 1

    version: "1"

    ports:

      :clmode_i: SOCM_PORT

        len: 2

        defn: single

  :pic_inst: SOCM_IFC

    name: single

    dir: 1

    version: "1"

    ports:

      :pic_inst_i: SOCM_PORT

        len: 2

        defn: single

  :clk: SOCM_IFC

    name: clk

    dir: 1

    version: "1"

    ports:

      :clk_i: SOCM_PORT

        len: 2

        defn: clk

  :rst: SOCM_IFC

    name: rst

    dir: 1

    version: "1"

    ports:

      :rst_i: SOCM_PORT

        len: 2

        defn: rst

  :wb_instruction: SOCM_IFC

    name: wishbone_ma

    dir: 1

    version: "b3"

    ports:

      :iwb_cyc_o: SOCM_PORT

        defn: cyc

        len:  1

      :iwb_stb_o: SOCM_PORT

        defn: stb

        len:  1

      :iwb_adr_o: SOCM_PORT

        defn: adr

        len:  32

      :iwb_sel_o: SOCM_PORT

        defn: sel

        len:  1

      :iwb_we_o: SOCM_PORT

        defn: we

        len:  1

      :iwb_dat_o: SOCM_PORT

        defn: dat_i

        len:  32

      :iwb_dat_i: SOCM_PORT

        defn: dat_o

        len:  32

      :iwb_ack_i: SOCM_PORT

        defn: ack

        len:  1

      :iwb_err_i: SOCM_PORT

        defn: err

        len:  1

      :iwb_rty_i: SOCM_PORT

        defn: err

        len:  1

  :wb_data: SOCM_IFC

    name: wishbone_ma

    dir: 1

    version: "b3"

    ports:

      :dwb_cyc_o: SOCM_PORT

        defn: cyc

        len:  1

      :dwb_stb_o: SOCM_PORT

        defn: stb

        len:  1

      :dwb_adr_o: SOCM_PORT

        defn: adr

        len:  32

      :dwb_sel_o: SOCM_PORT

        defn: sel

        len:  1

      :dwb_we_o: SOCM_PORT

        defn: we

        len:  1

      :dwb_dat_o: SOCM_PORT

        defn: dat_i

        len:  32

      :dwb_dat_i: SOCM_PORT

        defn: dat_i

        len:  32

      :dwb_ack_i: SOCM_PORT

        defn: ack

        len:  1

      :dwb_err_i: SOCM_PORT

        defn: err

        len:  1

      :dwb_rty_i: SOCM_PORT

        defn: err

        len:  1

  :ext_debug: SOCM_IFC

    name: debug

    dir: 1

    version: "1"

    ports:

      :dbg_stall_i: SOCM_PORT

        defn: dbg_stall

        len: 1

      :dbg_ewt_i: SOCM_PORT

        len: 1

        defn: dbg_ewt

      :dbg_lss_o: SOCM_PORT

        len: 4

        defn: dbg_lss

      :dbg_is_o: SOCM_PORT

        len: 2

        defn: dbg_iso

      :dbg_wp_o: SOCM_PORT

        len: 11

        defn: dbg_wpo

      :dbg_bp_o: SOCM_PORT

        len: 1

        defn: dbg_bpo

      :dbg_stb_i: SOCM_PORT

        len: 1

        defn: dbg_stb

      :dbg_we_i: SOCM_PORT

        len: 1

        defn: dbg_we

      :dbg_adr_i: SOCM_PORT

        len: 32

        defn: dbg_adr

      :dbg_dat_i: SOCM_PORT

        len: 32

        defn: dbg_dat

      :dbg_dat_o: SOCM_PORT

        len: 32

        defn: dbg_dat

      :dbg_ack_o: SOCM_PORT

        len: 1

        defn: dbg_ack

  :pow_man: SOCM_IFC

    name: or_power_management

    dir: 1

    version: "1"

    ports:

      :pm_cpustall_i: SOCM_PORT

         len: 1

         defn: pm_cpustall

      :pm_clksd_o: SOCM_PORT

         len: 4

         defn: pm_clksd

      :pm_dc_gate_o: SOCM_PORT

         len: 1

         defn: pm_dc_gate

      :pm_ic_gate_o: SOCM_PORT

         len: 1

         defn: pm_ic_gate

      :pm_dmmu_gate_o: SOCM_PORT

         len: 1

         defn: pm_dmmu_gate

      :pm_immu_gate_o: SOCM_PORT

         len: 1

         defn: pm_immu_gate

      :pm_tt_gate_o: SOCM_PORT

         len: 1

         defn: pm_tt_gate

      :pm_cpu_gate_o: SOCM_PORT

         len: 1

         defn: pm_cpu_gate

      :pm_wakeup_o: SOCM_PORT

         len: 1

         defn: pm_wakeup

      :pm_lvolt_o: SOCM_PORT

         len: 1

         defn: pm_lvolt