URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [02_or1200_files.yaml] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


hdlfiles:
  :alu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/or1200_alu.v
 
  :tlb: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/or1200_dmmu_tlb.v
 
  :ram: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_ram.v
 
  :operandmuxes: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_operandmuxes.v
 
  :spram_1024: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x32.v
 
  :spram_64_22: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x22.v
 
  :amultp2: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_amultp2_32x32.v
 
  :dmmu_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dmmu_top.v
 
  :ic_tag: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_tag.v
 
  :pic: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_pic.v
 
  :spram_1024_8: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x8.v
 
  :spram_64_24: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x24.v
 
  :cfgr: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_cfgr.v
 
  :dpram_256_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dpram_256x32.v
 
  :ic_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_top.v
 
  :pm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_pm.v
 
  :spram_128_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_128x32.v
 
  :sprs: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sprs.v
 
  :cpu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_cpu.v
 
  :dpram_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dpram_32x32.v
 
  :if: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_if.v
 
  :qmem_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_qmem_top.v
 
  :spram_2048_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x32_bw.v
 
  :top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_top.v
 
  :or1200_ctrl: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ctrl.v
 
  :du: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_du.v
 
  :immu_tlb: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_immu_tlb.v
 
  :reg2mem: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_reg2mem.v
 
  :spram_2048_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x32.v
 
  :tpram_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_tpram_32x32.v
 
  :dc_fsm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_fsm.v
 
  :except: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_except.v
 
  :immu_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_immu_top.v
 
  :rfram_generic: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_rfram_generic.v
 
  :spram_2048_8: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x8.v
 
  :tt: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_tt.v
 
  :dc_ram: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_ram.v
 
  :freeze: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_freeze.v
 
  :iwb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_iwb_biu.v
 
  :rf: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_rf.v
 
  :spram_256_21: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_256x21.v
 
  :wb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_wb_biu.v
 
  :dc_tag: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_tag.v
 
  :genpc: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_genpc.v
 
  :lsu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_lsu.v
 
  :fifo: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sb_fifo.v
 
  :spram_32_24: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_32x24.v
 
  :wbmux: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_wbmux.v
 
  :dc_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_top.v
 
  :gmultp2_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_gmultp2_32x32.v
 
  :mem2reg: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_mem2reg.v
 
  :sb: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sb.v
 
  :spram_512_20: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_512x20.v
 
  :xcv_ram32_8d: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_xcv_ram32x8d.v
 
  :defines: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_defines.v
 
  :ic_fsm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_fsm.v
 
  :mult_mac: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_mult_mac.v
 
  :spram_2014x32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x32_bw.v
 
  :spram_64_14: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x14.v
 
  :timescale: SOCM_HDL_FILE
    use_syn: false
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/timescale.v

Browse

Tools

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [02_or1200_files.yaml] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	feddischso	`hdlfiles:`
2			`:alu: SOCM_HDL_FILE`
3			`use_syn: true`
4			`use_sim: true`
5			`type: verilog`
6			`path: rtl/verilog/or1200_alu.v`
7
8			`:tlb: SOCM_HDL_FILE`
9			`use_syn: true`
10			`use_sim: true`
11			`type: verilog`
12			`path: rtl/verilog/or1200_dmmu_tlb.v`
13
14			`:ram: SOCM_HDL_FILE`
15			`use_syn: true`
16			`use_sys_sim: true`
17			`use_mod_sim: true`
18			`type: vhdl`
19			`path: rtl/verilog/or1200_ic_ram.v`
20
21			`:operandmuxes: SOCM_HDL_FILE`
22			`use_syn: true`
23			`use_sys_sim: true`
24			`use_mod_sim: true`
25			`type: vhdl`
26			`path: rtl/verilog/or1200_operandmuxes.v`
27
28			`:spram_1024: SOCM_HDL_FILE`
29			`use_syn: true`
30			`use_sys_sim: true`
31			`use_mod_sim: true`
32			`type: vhdl`
33			`path: rtl/verilog/or1200_spram_1024x32.v`
34
35			`:spram_64_22: SOCM_HDL_FILE`
36			`use_syn: true`
37			`use_sys_sim: true`
38			`use_mod_sim: true`
39			`type: vhdl`
40			`path: rtl/verilog/or1200_spram_64x22.v`
41
42			`:amultp2: SOCM_HDL_FILE`
43			`use_syn: true`
44			`use_sys_sim: true`
45			`use_mod_sim: true`
46			`type: vhdl`
47			`path: rtl/verilog/or1200_amultp2_32x32.v`
48
49			`:dmmu_top: SOCM_HDL_FILE`
50			`use_syn: true`
51			`use_sys_sim: true`
52			`use_mod_sim: true`
53			`type: vhdl`
54			`path: rtl/verilog/or1200_dmmu_top.v`
55
56			`:ic_tag: SOCM_HDL_FILE`
57			`use_syn: true`
58			`use_sys_sim: true`
59			`use_mod_sim: true`
60			`type: vhdl`
61			`path: rtl/verilog/or1200_ic_tag.v`
62
63			`:pic: SOCM_HDL_FILE`
64			`use_syn: true`
65			`use_sys_sim: true`
66			`use_mod_sim: true`
67			`type: vhdl`
68			`path: rtl/verilog/or1200_pic.v`
69
70			`:spram_1024_8: SOCM_HDL_FILE`
71			`use_syn: true`
72			`use_sys_sim: true`
73			`use_mod_sim: true`
74			`type: vhdl`
75			`path: rtl/verilog/or1200_spram_1024x8.v`
76
77			`:spram_64_24: SOCM_HDL_FILE`
78			`use_syn: true`
79			`use_sys_sim: true`
80			`use_mod_sim: true`
81			`type: vhdl`
82			`path: rtl/verilog/or1200_spram_64x24.v`
83
84			`:cfgr: SOCM_HDL_FILE`
85			`use_syn: true`
86			`use_sys_sim: true`
87			`use_mod_sim: true`
88			`type: vhdl`
89			`path: rtl/verilog/or1200_cfgr.v`
90
91			`:dpram_256_32: SOCM_HDL_FILE`
92			`use_syn: true`
93			`use_sys_sim: true`
94			`use_mod_sim: true`
95			`type: vhdl`
96			`path: rtl/verilog/or1200_dpram_256x32.v`
97
98			`:ic_top: SOCM_HDL_FILE`
99			`use_syn: true`
100			`use_sys_sim: true`
101			`use_mod_sim: true`
102			`type: vhdl`
103			`path: rtl/verilog/or1200_ic_top.v`
104
105			`:pm: SOCM_HDL_FILE`
106			`use_syn: true`
107			`use_sys_sim: true`
108			`use_mod_sim: true`
109			`type: vhdl`
110			`path: rtl/verilog/or1200_pm.v`
111
112			`:spram_128_32: SOCM_HDL_FILE`
113			`use_syn: true`
114			`use_sys_sim: true`
115			`use_mod_sim: true`
116			`type: vhdl`
117			`path: rtl/verilog/or1200_spram_128x32.v`
118
119			`:sprs: SOCM_HDL_FILE`
120			`use_syn: true`
121			`use_sys_sim: true`
122			`use_mod_sim: true`
123			`type: vhdl`
124			`path: rtl/verilog/or1200_sprs.v`
125
126			`:cpu: SOCM_HDL_FILE`
127			`use_syn: true`
128			`use_sys_sim: true`
129			`use_mod_sim: true`
130			`type: vhdl`
131			`path: rtl/verilog/or1200_cpu.v`
132
133			`:dpram_32_32: SOCM_HDL_FILE`
134			`use_syn: true`
135			`use_sys_sim: true`
136			`use_mod_sim: true`
137			`type: vhdl`
138			`path: rtl/verilog/or1200_dpram_32x32.v`
139
140			`:if: SOCM_HDL_FILE`
141			`use_syn: true`
142			`use_sys_sim: true`
143			`use_mod_sim: true`
144			`type: vhdl`
145			`path: rtl/verilog/or1200_if.v`
146
147			`:qmem_top: SOCM_HDL_FILE`
148			`use_syn: true`
149			`use_sys_sim: true`
150			`use_mod_sim: true`
151			`type: vhdl`
152			`path: rtl/verilog/or1200_qmem_top.v`
153
154			`:spram_2048_32: SOCM_HDL_FILE`
155			`use_syn: true`
156			`use_sys_sim: true`
157			`use_mod_sim: true`
158			`type: vhdl`
159			`path: rtl/verilog/or1200_spram_2048x32_bw.v`
160
161			`:top: SOCM_HDL_FILE`
162			`use_syn: true`
163			`use_sys_sim: true`
164			`use_mod_sim: true`
165			`type: vhdl`
166			`path: rtl/verilog/or1200_top.v`
167
168			`:or1200_ctrl: SOCM_HDL_FILE`
169			`use_syn: true`
170			`use_sys_sim: true`
171			`use_mod_sim: true`
172			`type: vhdl`
173			`path: rtl/verilog/or1200_ctrl.v`
174
175			`:du: SOCM_HDL_FILE`
176			`use_syn: true`
177			`use_sys_sim: true`
178			`use_mod_sim: true`
179			`type: vhdl`
180			`path: rtl/verilog/or1200_du.v`
181
182			`:immu_tlb: SOCM_HDL_FILE`
183			`use_syn: true`
184			`use_sys_sim: true`
185			`use_mod_sim: true`
186			`type: vhdl`
187			`path: rtl/verilog/or1200_immu_tlb.v`
188
189			`:reg2mem: SOCM_HDL_FILE`
190			`use_syn: true`
191			`use_sys_sim: true`
192			`use_mod_sim: true`
193			`type: vhdl`
194			`path: rtl/verilog/or1200_reg2mem.v`
195
196			`:spram_2048_32: SOCM_HDL_FILE`
197			`use_syn: true`
198			`use_sys_sim: true`
199			`use_mod_sim: true`
200			`type: vhdl`
201			`path: rtl/verilog/or1200_spram_2048x32.v`
202
203			`:tpram_32_32: SOCM_HDL_FILE`
204			`use_syn: true`
205			`use_sys_sim: true`
206			`use_mod_sim: true`
207			`type: vhdl`
208			`path: rtl/verilog/or1200_tpram_32x32.v`
209
210			`:dc_fsm: SOCM_HDL_FILE`
211			`use_syn: true`
212			`use_sys_sim: true`
213			`use_mod_sim: true`
214			`type: vhdl`
215			`path: rtl/verilog/or1200_dc_fsm.v`
216
217			`:except: SOCM_HDL_FILE`
218			`use_syn: true`
219			`use_sys_sim: true`
220			`use_mod_sim: true`
221			`type: vhdl`
222			`path: rtl/verilog/or1200_except.v`
223
224			`:immu_top: SOCM_HDL_FILE`
225			`use_syn: true`
226			`use_sys_sim: true`
227			`use_mod_sim: true`
228			`type: vhdl`
229			`path: rtl/verilog/or1200_immu_top.v`
230
231			`:rfram_generic: SOCM_HDL_FILE`
232			`use_syn: true`
233			`use_sys_sim: true`
234			`use_mod_sim: true`
235			`type: vhdl`
236			`path: rtl/verilog/or1200_rfram_generic.v`
237
238			`:spram_2048_8: SOCM_HDL_FILE`
239			`use_syn: true`
240			`use_sys_sim: true`
241			`use_mod_sim: true`
242			`type: vhdl`
243			`path: rtl/verilog/or1200_spram_2048x8.v`
244
245			`:tt: SOCM_HDL_FILE`
246			`use_syn: true`
247			`use_sys_sim: true`
248			`use_mod_sim: true`
249			`type: vhdl`
250			`path: rtl/verilog/or1200_tt.v`
251
252			`:dc_ram: SOCM_HDL_FILE`
253			`use_syn: true`
254			`use_sys_sim: true`
255			`use_mod_sim: true`
256			`type: vhdl`
257			`path: rtl/verilog/or1200_dc_ram.v`
258
259			`:freeze: SOCM_HDL_FILE`
260			`use_syn: true`
261			`use_sys_sim: true`
262			`use_mod_sim: true`
263			`type: vhdl`
264			`path: rtl/verilog/or1200_freeze.v`
265
266			`:iwb_biu: SOCM_HDL_FILE`
267			`use_syn: true`
268			`use_sys_sim: true`
269			`use_mod_sim: true`
270			`type: vhdl`
271			`path: rtl/verilog/or1200_iwb_biu.v`
272
273			`:rf: SOCM_HDL_FILE`
274			`use_syn: true`
275			`use_sys_sim: true`
276			`use_mod_sim: true`
277			`type: vhdl`
278			`path: rtl/verilog/or1200_rf.v`
279
280			`:spram_256_21: SOCM_HDL_FILE`
281			`use_syn: true`
282			`use_sys_sim: true`
283			`use_mod_sim: true`
284			`type: vhdl`
285			`path: rtl/verilog/or1200_spram_256x21.v`
286
287			`:wb_biu: SOCM_HDL_FILE`
288			`use_syn: true`
289			`use_sys_sim: true`
290			`use_mod_sim: true`
291			`type: vhdl`
292			`path: rtl/verilog/or1200_wb_biu.v`
293
294			`:dc_tag: SOCM_HDL_FILE`
295			`use_syn: true`
296			`use_sys_sim: true`
297			`use_mod_sim: true`
298			`type: vhdl`
299			`path: rtl/verilog/or1200_dc_tag.v`
300
301			`:genpc: SOCM_HDL_FILE`
302			`use_syn: true`
303			`use_sys_sim: true`
304			`use_mod_sim: true`
305			`type: vhdl`
306			`path: rtl/verilog/or1200_genpc.v`
307
308			`:lsu: SOCM_HDL_FILE`
309			`use_syn: true`
310			`use_sys_sim: true`
311			`use_mod_sim: true`
312			`type: vhdl`
313			`path: rtl/verilog/or1200_lsu.v`
314
315			`:fifo: SOCM_HDL_FILE`
316			`use_syn: true`
317			`use_sys_sim: true`
318			`use_mod_sim: true`
319			`type: vhdl`
320			`path: rtl/verilog/or1200_sb_fifo.v`
321
322			`:spram_32_24: SOCM_HDL_FILE`
323			`use_syn: true`
324			`use_sys_sim: true`
325			`use_mod_sim: true`
326			`type: vhdl`
327			`path: rtl/verilog/or1200_spram_32x24.v`
328
329			`:wbmux: SOCM_HDL_FILE`
330			`use_syn: true`
331			`use_sys_sim: true`
332			`use_mod_sim: true`
333			`type: vhdl`
334			`path: rtl/verilog/or1200_wbmux.v`
335
336			`:dc_top: SOCM_HDL_FILE`
337			`use_syn: true`
338			`use_sys_sim: true`
339			`use_mod_sim: true`
340			`type: vhdl`
341			`path: rtl/verilog/or1200_dc_top.v`
342
343			`:gmultp2_32_32: SOCM_HDL_FILE`
344			`use_syn: true`
345			`use_sys_sim: true`
346			`use_mod_sim: true`
347			`type: vhdl`
348			`path: rtl/verilog/or1200_gmultp2_32x32.v`
349
350			`:mem2reg: SOCM_HDL_FILE`
351			`use_syn: true`
352			`use_sys_sim: true`
353			`use_mod_sim: true`
354			`type: vhdl`
355			`path: rtl/verilog/or1200_mem2reg.v`
356
357			`:sb: SOCM_HDL_FILE`
358			`use_syn: true`
359			`use_sys_sim: true`
360			`use_mod_sim: true`
361			`type: vhdl`
362			`path: rtl/verilog/or1200_sb.v`
363
364			`:spram_512_20: SOCM_HDL_FILE`
365			`use_syn: true`
366			`use_sys_sim: true`
367			`use_mod_sim: true`
368			`type: vhdl`
369			`path: rtl/verilog/or1200_spram_512x20.v`
370
371			`:xcv_ram32_8d: SOCM_HDL_FILE`
372			`use_syn: true`
373			`use_sys_sim: true`
374			`use_mod_sim: true`
375			`type: vhdl`
376			`path: rtl/verilog/or1200_xcv_ram32x8d.v`
377
378			`:defines: SOCM_HDL_FILE`
379			`use_syn: true`
380			`use_sys_sim: true`
381			`use_mod_sim: true`
382			`type: vhdl`
383			`path: rtl/verilog/or1200_defines.v`
384
385			`:ic_fsm: SOCM_HDL_FILE`
386			`use_syn: true`
387			`use_sys_sim: true`
388			`use_mod_sim: true`
389			`type: vhdl`
390			`path: rtl/verilog/or1200_ic_fsm.v`
391
392			`:mult_mac: SOCM_HDL_FILE`
393			`use_syn: true`
394			`use_sys_sim: true`
395			`use_mod_sim: true`
396			`type: vhdl`
397			`path: rtl/verilog/or1200_mult_mac.v`
398
399			`:spram_2014x32: SOCM_HDL_FILE`
400			`use_syn: true`
401			`use_sys_sim: true`
402			`use_mod_sim: true`
403			`type: vhdl`
404			`path: rtl/verilog/or1200_spram_1024x32_bw.v`
405
406			`:spram_64_14: SOCM_HDL_FILE`
407			`use_syn: true`
408			`use_sys_sim: true`
409			`use_mod_sim: true`
410			`type: vhdl`
411			`path: rtl/verilog/or1200_spram_64x14.v`
412
413			`:timescale: SOCM_HDL_FILE`
414			`use_syn: false`
415			`use_sys_sim: true`
416			`use_mod_sim: true`
417			`type: vhdl`
418			`path: rtl/verilog/timescale.v`