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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [02_or1200_files.yaml] - Blame information for rev 8

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Line No. Rev Author Line
1 5 feddischso
hdlfiles:
2
  :alu: SOCM_HDL_FILE
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    use_syn: true
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    use_sim: true
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    type: verilog
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    path: rtl/verilog/or1200_alu.v
7
 
8
  :tlb: SOCM_HDL_FILE
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    use_syn: true
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    use_sim: true
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    type: verilog
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    path: rtl/verilog/or1200_dmmu_tlb.v
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14
  :ram: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_ic_ram.v
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21
  :operandmuxes: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_operandmuxes.v
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28
  :spram_1024: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_1024x32.v
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35
  :spram_64_22: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_64x22.v
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42
  :amultp2: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_amultp2_32x32.v
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49
  :dmmu_top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dmmu_top.v
55
 
56
  :ic_tag: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_ic_tag.v
62
 
63
  :pic: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_pic.v
69
 
70
  :spram_1024_8: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_1024x8.v
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77
  :spram_64_24: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_64x24.v
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84
  :cfgr: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_cfgr.v
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91
  :dpram_256_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dpram_256x32.v
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98
  :ic_top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
101
    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_ic_top.v
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105
  :pm: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_pm.v
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112
  :spram_128_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_128x32.v
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119
  :sprs: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_sprs.v
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126
  :cpu: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_cpu.v
132
 
133
  :dpram_32_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dpram_32x32.v
139
 
140
  :if: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_if.v
146
 
147
  :qmem_top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_qmem_top.v
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154
  :spram_2048_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_2048x32_bw.v
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161
  :top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_top.v
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168
  :or1200_ctrl: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_ctrl.v
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175
  :du: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_du.v
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182
  :immu_tlb: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_immu_tlb.v
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189
  :reg2mem: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_reg2mem.v
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196
  :spram_2048_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_2048x32.v
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203
  :tpram_32_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_tpram_32x32.v
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210
  :dc_fsm: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dc_fsm.v
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217
  :except: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_except.v
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224
  :immu_top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_immu_top.v
230
 
231
  :rfram_generic: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_rfram_generic.v
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238
  :spram_2048_8: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_2048x8.v
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245
  :tt: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_tt.v
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252
  :dc_ram: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dc_ram.v
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259
  :freeze: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_freeze.v
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266
  :iwb_biu: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_iwb_biu.v
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273
  :rf: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_rf.v
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280
  :spram_256_21: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_256x21.v
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287
  :wb_biu: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_wb_biu.v
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294
  :dc_tag: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dc_tag.v
300
 
301
  :genpc: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_genpc.v
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308
  :lsu: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_lsu.v
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315
  :fifo: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_sb_fifo.v
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322
  :spram_32_24: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_32x24.v
328
 
329
  :wbmux: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_wbmux.v
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336
  :dc_top: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_dc_top.v
342
 
343
  :gmultp2_32_32: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_gmultp2_32x32.v
349
 
350
  :mem2reg: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_mem2reg.v
356
 
357
  :sb: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_sb.v
363
 
364
  :spram_512_20: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_spram_512x20.v
370
 
371
  :xcv_ram32_8d: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/or1200_xcv_ram32x8d.v
377
 
378 8 feddischso
# Please note: the defines is automatically created
379
# see or1200_defines.v.in
380 5 feddischso
 
381 8 feddischso
# :defines: SOCM_HDL_FILE
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#   use_syn: true
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#   use_sys_sim: true
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#   use_mod_sim: true
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#   type: vhdl
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#   path: rtl/verilog/or1200_defines.v
387
 
388 5 feddischso
  :ic_fsm: SOCM_HDL_FILE
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    use_syn: true
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    use_sys_sim: true
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    use_mod_sim: true
392
    type: vhdl
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    path: rtl/verilog/or1200_ic_fsm.v
394
 
395
  :mult_mac: SOCM_HDL_FILE
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    use_syn: true
397
    use_sys_sim: true
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    use_mod_sim: true
399
    type: vhdl
400
    path: rtl/verilog/or1200_mult_mac.v
401
 
402
  :spram_2014x32: SOCM_HDL_FILE
403
    use_syn: true
404
    use_sys_sim: true
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    use_mod_sim: true
406
    type: vhdl
407
    path: rtl/verilog/or1200_spram_1024x32_bw.v
408
 
409
  :spram_64_14: SOCM_HDL_FILE
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    use_syn: true
411
    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
414
    path: rtl/verilog/or1200_spram_64x14.v
415
 
416
  :timescale: SOCM_HDL_FILE
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    use_syn: false
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    use_sys_sim: true
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    use_mod_sim: true
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    type: vhdl
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    path: rtl/verilog/timescale.v

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