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1 8 feddischso
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Parameters of the OR1200 core                               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
////                                                              ////
20
////         Modified for SOC-Maker as config-define              ////
21
////         28. Jul., 2014, feddischson@opencores.org            ////
22
////                                                              ////
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////                                                              ////
24
//////////////////////////////////////////////////////////////////////
25
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
27
////                                                              ////
28
//// This source file may be used and distributed without         ////
29
//// restriction provided that this copyright statement is not    ////
30
//// removed from the file and that any derivative work contains  ////
31
//// the original copyright notice and the associated disclaimer. ////
32
////                                                              ////
33
//// This source file is free software; you can redistribute it   ////
34
//// and/or modify it under the terms of the GNU Lesser General   ////
35
//// Public License as published by the Free Software Foundation; ////
36
//// either version 2.1 of the License, or (at your option) any   ////
37
//// later version.                                               ////
38
////                                                              ////
39
//// This source is distributed in the hope that it will be       ////
40
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
41
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
42
//// PURPOSE.  See the GNU Lesser General Public License for more ////
43
//// details.                                                     ////
44
////                                                              ////
45
//// You should have received a copy of the GNU Lesser General    ////
46
//// Public License along with this source; if not, download it   ////
47
//// from http://www.opencores.org/lgpl.shtml                     ////
48
////                                                              ////
49
//////////////////////////////////////////////////////////////////////
50
//
51
// CVS Revision History
52
//
53
// $Log: not supported by cvs2svn $
54
// Revision 1.44  2005/10/19 11:37:56  jcastillo
55
// Added support for RAMB16 Xilinx4/Spartan3 primitives
56
//
57
// Revision 1.43  2005/01/07 09:23:39  andreje
58
// l.ff1 and l.cmov instructions added
59
//
60
// Revision 1.42  2004/06/08 18:17:36  lampret
61
// Non-functional changes. Coding style fixes.
62
//
63
// Revision 1.41  2004/05/09 20:03:20  lampret
64
// By default l.cust5 insns are disabled
65
//
66
// Revision 1.40  2004/05/09 19:49:04  lampret
67
// Added some l.cust5 custom instructions as example
68
//
69
// Revision 1.39  2004/04/08 11:00:46  simont
70
// Add support for 512B instruction cache.
71
//
72
// Revision 1.38  2004/04/05 08:29:57  lampret
73
// Merged branch_qmem into main tree.
74
//
75
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
76
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
77
//
78
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
79
// interface to debug changed; no more opselect; stb-ack protocol
80
//
81
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
82
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
83
//
84
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
85
// Exception prefix configuration changed.
86
//
87
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
88
// Static exception prefix.
89
//
90
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
91
// Added embedded memory QMEM.
92
//
93
// Revision 1.35  2003/04/24 00:16:07  lampret
94
// No functional changes. Added defines to disable implementation of multiplier/MAC
95
//
96
// Revision 1.34  2003/04/20 22:23:57  lampret
97
// No functional change. Only added customization for exception vectors.
98
//
99
// Revision 1.33  2003/04/07 20:56:07  lampret
100
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
101
//
102
// Revision 1.32  2003/04/07 01:26:57  lampret
103
// RFRAM defines comments updated. Altera LPM option added.
104
//
105
// Revision 1.31  2002/12/08 08:57:56  lampret
106
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
107
//
108
// Revision 1.30  2002/10/28 15:09:22  mohor
109
// Previous check-in was done by mistake.
110
//
111
// Revision 1.29  2002/10/28 15:03:50  mohor
112
// Signal scanb_sen renamed to scanb_en.
113
//
114
// Revision 1.28  2002/10/17 20:04:40  lampret
115
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
116
//
117
// Revision 1.27  2002/09/16 03:13:23  lampret
118
// Removed obsolete comment.
119
//
120
// Revision 1.26  2002/09/08 05:52:16  lampret
121
// Added optional l.div/l.divu insns. By default they are disabled.
122
//
123
// Revision 1.25  2002/09/07 19:16:10  lampret
124
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
125
//
126
// Revision 1.24  2002/09/07 05:42:02  lampret
127
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
128
//
129
// Revision 1.23  2002/09/04 00:50:34  lampret
130
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
131
//
132
// Revision 1.22  2002/09/03 22:28:21  lampret
133
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
134
//
135
// Revision 1.21  2002/08/22 02:18:55  lampret
136
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
137
//
138
// Revision 1.20  2002/08/18 21:59:45  lampret
139
// Disable SB until it is tested
140
//
141
// Revision 1.19  2002/08/18 19:53:08  lampret
142
// Added store buffer.
143
//
144
// Revision 1.18  2002/08/15 06:04:11  lampret
145
// Fixed Xilinx trace buffer address. REported by Taylor Su.
146
//
147
// Revision 1.17  2002/08/12 05:31:44  lampret
148
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
149
//
150
// Revision 1.16  2002/07/14 22:17:17  lampret
151
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
152
//
153
// Revision 1.15  2002/06/08 16:20:21  lampret
154
// Added defines for enabling generic FF based memory macro for register file.
155
//
156
// Revision 1.14  2002/03/29 16:24:06  lampret
157
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
158
//
159
// Revision 1.13  2002/03/29 15:16:55  lampret
160
// Some of the warnings fixed.
161
//
162
// Revision 1.12  2002/03/28 19:25:42  lampret
163
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
164
//
165
// Revision 1.11  2002/03/28 19:13:17  lampret
166
// Updated defines.
167
//
168
// Revision 1.10  2002/03/14 00:30:24  lampret
169
// Added alternative for critical path in DU.
170
//
171
// Revision 1.9  2002/03/11 01:26:26  lampret
172
// Fixed async loop. Changed multiplier type for ASIC.
173
//
174
// Revision 1.8  2002/02/11 04:33:17  lampret
175
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
176
//
177
// Revision 1.7  2002/02/01 19:56:54  lampret
178
// Fixed combinational loops.
179
//
180
// Revision 1.6  2002/01/19 14:10:22  lampret
181
// Fixed OR1200_XILINX_RAM32X1D.
182
//
183
// Revision 1.5  2002/01/18 07:56:00  lampret
184
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
185
//
186
// Revision 1.4  2002/01/14 09:44:12  lampret
187
// Default ASIC configuration does not sample WB inputs.
188
//
189
// Revision 1.3  2002/01/08 00:51:08  lampret
190
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
191
//
192
// Revision 1.2  2002/01/03 21:23:03  lampret
193
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
194
//
195
// Revision 1.1  2002/01/03 08:16:15  lampret
196
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
197
//
198
// Revision 1.20  2001/12/04 05:02:36  lampret
199
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
200
//
201
// Revision 1.19  2001/11/27 19:46:57  lampret
202
// Now FPGA and ASIC target are separate.
203
//
204
// Revision 1.18  2001/11/23 21:42:31  simons
205
// Program counter divided to PPC and NPC.
206
//
207
// Revision 1.17  2001/11/23 08:38:51  lampret
208
// Changed DSR/DRR behavior and exception detection.
209
//
210
// Revision 1.16  2001/11/20 21:30:38  lampret
211
// Added OR1200_REGISTERED_INPUTS.
212
//
213
// Revision 1.15  2001/11/19 14:29:48  simons
214
// Cashes disabled.
215
//
216
// Revision 1.14  2001/11/13 10:02:21  lampret
217
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
218
//
219
// Revision 1.13  2001/11/12 01:45:40  lampret
220
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
221
//
222
// Revision 1.12  2001/11/10 03:43:57  lampret
223
// Fixed exceptions.
224
//
225
// Revision 1.11  2001/11/02 18:57:14  lampret
226
// Modified virtual silicon instantiations.
227
//
228
// Revision 1.10  2001/10/21 17:57:16  lampret
229
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
230
//
231
// Revision 1.9  2001/10/19 23:28:46  lampret
232
// Fixed some synthesis warnings. Configured with caches and MMUs.
233
//
234
// Revision 1.8  2001/10/14 13:12:09  lampret
235
// MP3 version.
236
//
237
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
238
// no message
239
//
240
// Revision 1.3  2001/08/17 08:01:19  lampret
241
// IC enable/disable.
242
//
243
// Revision 1.2  2001/08/13 03:36:20  lampret
244
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
245
//
246
// Revision 1.1  2001/08/09 13:39:33  lampret
247
// Major clean-up.
248
//
249
// Revision 1.2  2001/07/22 03:31:54  lampret
250
// Fixed RAM's oen bug. Cache bypass under development.
251
//
252
// Revision 1.1  2001/07/20 00:46:03  lampret
253
// Development version of RTL. Libraries are missing.
254
//
255
//
256
 
257
//
258
// Dump VCD
259
//
260
//`define OR1200_VCD_DUMP
261
TOK_VCD_DUMP
262
 
263
//
264
// Generate debug messages during simulation
265
//
266
//`define OR1200_VERBOSE
267
TOK_VERBOSE
268
 
269
 
270
//  `define OR1200_ASIC
271
TOK_ASIC
272
 
273
////////////////////////////////////////////////////////
274
//
275
// Typical configuration for an ASIC
276
//
277
`ifdef OR1200_ASIC
278
 
279
//
280
// Target ASIC memories
281
//
282
//`define OR1200_ARTISAN_SSP
283
//`define OR1200_ARTISAN_SDP
284
//`define OR1200_ARTISAN_STP
285
//`define OR1200_VIRTUALSILICON_SSP
286
//`define OR1200_VIRTUALSILICON_STP_T1
287
//`define OR1200_VIRTUALSILICON_STP_T2
288
TOK_ASIC_MEM_CHOICE
289
 
290
 
291
//
292
// Do not implement Data cache
293
//
294
//`define OR1200_NO_DC
295
TOK_ASIC_NO_DC
296
 
297
//
298
// Do not implement Insn cache
299
//
300
//`define OR1200_NO_IC
301
TOK_ASIC_NO_IC
302
 
303
 
304
//
305
// Do not implement Data MMU
306
//
307
//`define OR1200_NO_DMMU
308
TOK_ASIC_NO_DMMU
309
 
310
 
311
//
312
// Do not implement Insn MMU
313
//
314
//`define OR1200_NO_IMMU
315
TOK_ASIC_NO_IMMU
316
 
317
 
318
//
319
// Select between ASIC optimized and generic multiplier
320
//
321
//`define OR1200_ASIC_MULTP2_32X32
322
//`define OR1200_GENERIC_MULTP2_32X32
323
TOK_ASIC_MUL_CHOICE
324
 
325
 
326
//
327
// Size/type of insn/data cache if implemented
328
//
329
// `define OR1200_IC_1W_512B
330
// `define OR1200_IC_1W_4KB
331
// `define OR1200_IC_1W_8KB
332
TOK_ASIC_IC_CHOICE
333
 
334
// `define OR1200_DC_1W_4KB
335
// `define OR1200_DC_1W_8KB
336
TOK_ASIC_DC_CHOICE
337
 
338
 
339
`else
340
 
341
 
342
/////////////////////////////////////////////////////////
343
//
344
// Typical configuration for an FPGA
345
//
346
 
347
//
348
// Target FPGA memories
349
//
350
//`define OR1200_ALTERA_LPM
351
//`define OR1200_XILINX_RAMB16
352
//`define OR1200_XILINX_RAMB4
353
//`define OR1200_XILINX_RAM32X1D
354
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
355
TOK_FPGA_MEM_CHOICE
356
 
357
 
358
//
359
// Do not implement Data cache
360
//
361
//`define OR1200_NO_DC
362
TOK_FPGA_NO_DC
363
 
364
 
365
//
366
// Do not implement Insn cache
367
//
368
//`define OR1200_NO_IC
369
TOK_FPGA_NO_IC
370
 
371
 
372
//
373
// Do not implement Data MMU
374
//
375
//`define OR1200_NO_DMMU
376
TOK_FPGA_NO_DMMU
377
 
378
 
379
//
380
// Do not implement Insn MMU
381
//
382
//`define OR1200_NO_IMMU
383
TOK_FPGA_NO_IMMU
384
 
385
 
386
//
387
// Select between ASIC and generic multiplier
388
//
389
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
390
//
391
//`define OR1200_ASIC_MULTP2_32X32
392
//`define OR1200_GENERIC_MULTP2_32X32
393
TOK_FPGA_MUL_CHOICE
394
 
395
 
396
//
397
// Size/type of insn/data cache if implemented
398
// (consider available FPGA memory resources)
399
//
400
//`define OR1200_IC_1W_512B
401
//`define OR1200_IC_1W_4KB
402
//`define OR1200_IC_1W_8KB
403
TOK_FPGA_IC_CHOICE
404
 
405
//`define OR1200_DC_1W_4KB
406
//`define OR1200_DC_1W_8KB
407
TOK_FPGA_DC_CHOICE
408
 
409
 
410
`endif
411
 
412
 
413
//////////////////////////////////////////////////////////
414
//
415
// Do not change below unless you know what you are doing
416
//
417
 
418
//
419
// Enable RAM BIST
420
//
421
// At the moment this only works for Virtual Silicon
422
// single port RAMs. For other RAMs it has not effect.
423
// Special wrapper for VS RAMs needs to be provided
424
// with scan flops to facilitate bist scan.
425
//
426
//`define OR1200_BIST
427
 
428
//
429
// Register OR1200 WISHBONE outputs
430
// (must be defined/enabled)
431
//
432
`define OR1200_REGISTERED_OUTPUTS
433
 
434
//
435
// Register OR1200 WISHBONE inputs
436
//
437
// (must be undefined/disabled)
438
//
439
//`define OR1200_REGISTERED_INPUTS
440
 
441
//
442
// Disable bursts if they are not supported by the
443
// memory subsystem (only affect cache line fill)
444
//
445
//`define OR1200_NO_BURSTS
446
//
447
 
448
//
449
// WISHBONE retry counter range
450
//
451
// 2^value range for retry counter. Retry counter
452
// is activated whenever *wb_rty_i is asserted and
453
// until retry counter expires, corresponding
454
// WISHBONE interface is deactivated.
455
//
456
// To disable retry counters and *wb_rty_i all together,
457
// undefine this macro.
458
//
459
//`define OR1200_WB_RETRY 7
460
 
461
//
462
// WISHBONE Consecutive Address Burst
463
//
464
// This was used prior to WISHBONE B3 specification
465
// to identify bursts. It is no longer needed but
466
// remains enabled for compatibility with old designs.
467
//
468
// To remove *wb_cab_o ports undefine this macro.
469
//
470
// `define OR1200_WB_CAB
471
 
472
//
473
// WISHBONE B3 compatible interface
474
//
475
// This follows the WISHBONE B3 specification.
476
// It is not enabled by default because most
477
// designs still don't use WB b3.
478
//
479
// To enable *wb_cti_o/*wb_bte_o ports,
480
// define this macro.
481
//
482
//`define OR1200_WB_B3
483
 
484
//
485
// Enable additional synthesis directives if using
486
// _Synopsys_ synthesis tool
487
//
488
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
489
 
490
//
491
// Enables default statement in some case blocks
492
// and disables Synopsys synthesis directive full_case
493
//
494
// By default it is enabled. When disabled it
495
// can increase clock frequency.
496
//
497
`define OR1200_CASE_DEFAULT
498
 
499
//
500
// Operand width / register file address width
501
//
502
// (DO NOT CHANGE)
503
//
504
`define OR1200_OPERAND_WIDTH            32
505
`define OR1200_REGFILE_ADDR_WIDTH       5
506
 
507
//
508
// l.add/l.addi/l.and and optional l.addc/l.addic
509
// also set (compare) flag when result of their
510
// operation equals zero
511
//
512
// At the time of writing this, default or32
513
// C/C++ compiler doesn't generate code that
514
// would benefit from this optimization.
515
//
516
// By default this optimization is disabled to
517
// save area.
518
//
519
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
520
 
521
//
522
// Implement l.addc/l.addic instructions
523
//
524
// By default implementation of l.addc/l.addic
525
// instructions is enabled in case you need them.
526
// If you don't use them, then disable implementation
527
// to save area.
528
//
529
`define OR1200_IMPL_ADDC
530
 
531
//
532
// Implement carry bit SR[CY]
533
//
534
// By default implementation of SR[CY] is enabled
535
// to be compliant with the simulator. However
536
// SR[CY] is explicitly only used by l.addc/l.addic
537
// instructions and if these two insns are not
538
// implemented there is not much point having SR[CY].
539
//
540
`define OR1200_IMPL_CY
541
 
542
//
543
// Implement optional l.div/l.divu instructions
544
//
545
// By default divide instructions are not implemented
546
// to save area and increase clock frequency. or32 C/C++
547
// compiler can use soft library for division.
548
//
549
// To implement divide, multiplier needs to be implemented.
550
//
551
//`define OR1200_IMPL_DIV
552
 
553
//
554
// Implement rotate in the ALU
555
//
556
// At the time of writing this, or32
557
// C/C++ compiler doesn't generate rotate
558
// instructions. However or32 assembler
559
// can assemble code that uses rotate insn.
560
// This means that rotate instructions
561
// must be used manually inserted.
562
//
563
// By default implementation of rotate
564
// is disabled to save area and increase
565
// clock frequency.
566
//
567
//`define OR1200_IMPL_ALU_ROTATE
568
 
569
//
570
// Type of ALU compare to implement
571
//
572
// Try either one to find what yields
573
// higher clock frequencyin your case.
574
//
575
//`define OR1200_IMPL_ALU_COMP1
576
`define OR1200_IMPL_ALU_COMP2
577
 
578
//
579
// Implement multiplier
580
//
581
// By default multiplier is implemented
582
//
583
`define OR1200_MULT_IMPLEMENTED
584
 
585
//
586
// Implement multiply-and-accumulate
587
//
588
// By default MAC is implemented. To
589
// implement MAC, multiplier needs to be
590
// implemented.
591
//
592
`define OR1200_MAC_IMPLEMENTED
593
 
594
//
595
// Low power, slower multiplier
596
//
597
// Select between low-power (larger) multiplier
598
// and faster multiplier. The actual difference
599
// is only AND logic that prevents distribution
600
// of operands into the multiplier when instruction
601
// in execution is not multiply instruction
602
//
603
//`define OR1200_LOWPWR_MULT
604
 
605
//
606
// Clock ratio RISC clock versus WB clock
607
//
608
// If you plan to run WB:RISC clock fixed to 1:1, disable
609
// both defines
610
//
611
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
612
// and use clmode to set ratio
613
//
614
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
615
// clmode to set ratio
616
//
617
`define OR1200_CLKDIV_2_SUPPORTED
618
//`define OR1200_CLKDIV_4_SUPPORTED
619
 
620
//
621
// Type of register file RAM
622
//
623
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
624
//`define OR1200_RFRAM_TWOPORT
625
//
626
// Memory macro dual port (see or1200_dpram_32x32.v)
627
//`define OR1200_RFRAM_DUALPORT
628
//
629
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
630
`define OR1200_RFRAM_GENERIC
631
 
632
//
633
// Type of mem2reg aligner to implement.
634
//
635
// Once OR1200_IMPL_MEM2REG2 yielded faster
636
// circuit, however with today tools it will
637
// most probably give you slower circuit.
638
//
639
`define OR1200_IMPL_MEM2REG1
640
//`define OR1200_IMPL_MEM2REG2
641
 
642
//
643
// ALUOPs
644
//
645
`define OR1200_ALUOP_WIDTH      4
646
`define OR1200_ALUOP_NOP        4'd4
647
/* Order defined by arith insns that have two source operands both in regs
648
   (see binutils/include/opcode/or32.h) */
649
`define OR1200_ALUOP_ADD        4'd0
650
`define OR1200_ALUOP_ADDC       4'd1
651
`define OR1200_ALUOP_SUB        4'd2
652
`define OR1200_ALUOP_AND        4'd3
653
`define OR1200_ALUOP_OR         4'd4
654
`define OR1200_ALUOP_XOR        4'd5
655
`define OR1200_ALUOP_MUL        4'd6
656
`define OR1200_ALUOP_CUST5      4'd7
657
`define OR1200_ALUOP_SHROT      4'd8
658
`define OR1200_ALUOP_DIV        4'd9
659
`define OR1200_ALUOP_DIVU       4'd10
660
/* Order not specifically defined. */
661
`define OR1200_ALUOP_IMM        4'd11
662
`define OR1200_ALUOP_MOVHI      4'd12
663
`define OR1200_ALUOP_COMP       4'd13
664
`define OR1200_ALUOP_MTSR       4'd14
665
`define OR1200_ALUOP_MFSR       4'd15
666
`define OR1200_ALUOP_CMOV 4'd14
667
`define OR1200_ALUOP_FF1  4'd15
668
//
669
// MACOPs
670
//
671
`define OR1200_MACOP_WIDTH      2
672
`define OR1200_MACOP_NOP        2'b00
673
`define OR1200_MACOP_MAC        2'b01
674
`define OR1200_MACOP_MSB        2'b10
675
 
676
//
677
// Shift/rotate ops
678
//
679
`define OR1200_SHROTOP_WIDTH    2
680
`define OR1200_SHROTOP_NOP      2'd0
681
`define OR1200_SHROTOP_SLL      2'd0
682
`define OR1200_SHROTOP_SRL      2'd1
683
`define OR1200_SHROTOP_SRA      2'd2
684
`define OR1200_SHROTOP_ROR      2'd3
685
 
686
// Execution cycles per instruction
687
`define OR1200_MULTICYCLE_WIDTH 2
688
`define OR1200_ONE_CYCLE                2'd0
689
`define OR1200_TWO_CYCLES               2'd1
690
 
691
// Operand MUX selects
692
`define OR1200_SEL_WIDTH                2
693
`define OR1200_SEL_RF                   2'd0
694
`define OR1200_SEL_IMM                  2'd1
695
`define OR1200_SEL_EX_FORW              2'd2
696
`define OR1200_SEL_WB_FORW              2'd3
697
 
698
//
699
// BRANCHOPs
700
//
701
`define OR1200_BRANCHOP_WIDTH           3
702
`define OR1200_BRANCHOP_NOP             3'd0
703
`define OR1200_BRANCHOP_J               3'd1
704
`define OR1200_BRANCHOP_JR              3'd2
705
`define OR1200_BRANCHOP_BAL             3'd3
706
`define OR1200_BRANCHOP_BF              3'd4
707
`define OR1200_BRANCHOP_BNF             3'd5
708
`define OR1200_BRANCHOP_RFE             3'd6
709
 
710
//
711
// LSUOPs
712
//
713
// Bit 0: sign extend
714
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
715
// Bit 3: 0 load, 1 store
716
`define OR1200_LSUOP_WIDTH              4
717
`define OR1200_LSUOP_NOP                4'b0000
718
`define OR1200_LSUOP_LBZ                4'b0010
719
`define OR1200_LSUOP_LBS                4'b0011
720
`define OR1200_LSUOP_LHZ                4'b0100
721
`define OR1200_LSUOP_LHS                4'b0101
722
`define OR1200_LSUOP_LWZ                4'b0110
723
`define OR1200_LSUOP_LWS                4'b0111
724
`define OR1200_LSUOP_LD         4'b0001
725
`define OR1200_LSUOP_SD         4'b1000
726
`define OR1200_LSUOP_SB         4'b1010
727
`define OR1200_LSUOP_SH         4'b1100
728
`define OR1200_LSUOP_SW         4'b1110
729
 
730
// FETCHOPs
731
`define OR1200_FETCHOP_WIDTH            1
732
`define OR1200_FETCHOP_NOP              1'b0
733
`define OR1200_FETCHOP_LW               1'b1
734
 
735
//
736
// Register File Write-Back OPs
737
//
738
// Bit 0: register file write enable
739
// Bits 2-1: write-back mux selects
740
`define OR1200_RFWBOP_WIDTH             3
741
`define OR1200_RFWBOP_NOP               3'b000
742
`define OR1200_RFWBOP_ALU               3'b001
743
`define OR1200_RFWBOP_LSU               3'b011
744
`define OR1200_RFWBOP_SPRS              3'b101
745
`define OR1200_RFWBOP_LR                3'b111
746
 
747
// Compare instructions
748
`define OR1200_COP_SFEQ       3'b000
749
`define OR1200_COP_SFNE       3'b001
750
`define OR1200_COP_SFGT       3'b010
751
`define OR1200_COP_SFGE       3'b011
752
`define OR1200_COP_SFLT       3'b100
753
`define OR1200_COP_SFLE       3'b101
754
`define OR1200_COP_X          3'b111
755
`define OR1200_SIGNED_COMPARE 'd3
756
`define OR1200_COMPOP_WIDTH     4
757
 
758
//
759
// TAGs for instruction bus
760
//
761
`define OR1200_ITAG_IDLE        4'h0    // idle bus
762
`define OR1200_ITAG_NI          4'h1    // normal insn
763
`define OR1200_ITAG_BE          4'hb    // Bus error exception
764
`define OR1200_ITAG_PE          4'hc    // Page fault exception
765
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
766
 
767
//
768
// TAGs for data bus
769
//
770
`define OR1200_DTAG_IDLE        4'h0    // idle bus
771
`define OR1200_DTAG_ND          4'h1    // normal data
772
`define OR1200_DTAG_AE          4'ha    // Alignment exception
773
`define OR1200_DTAG_BE          4'hb    // Bus error exception
774
`define OR1200_DTAG_PE          4'hc    // Page fault exception
775
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
776
 
777
 
778
//////////////////////////////////////////////
779
//
780
// ORBIS32 ISA specifics
781
//
782
 
783
// SHROT_OP position in machine word
784
`define OR1200_SHROTOP_POS              7:6
785
 
786
// ALU instructions multicycle field in machine word
787
`define OR1200_ALUMCYC_POS              9:8
788
 
789
//
790
// Instruction opcode groups (basic)
791
//
792
`define OR1200_OR32_J                 6'b000000
793
`define OR1200_OR32_JAL               6'b000001
794
`define OR1200_OR32_BNF               6'b000011
795
`define OR1200_OR32_BF                6'b000100
796
`define OR1200_OR32_NOP               6'b000101
797
`define OR1200_OR32_MOVHI             6'b000110
798
`define OR1200_OR32_XSYNC             6'b001000
799
`define OR1200_OR32_RFE               6'b001001
800
/* */
801
`define OR1200_OR32_JR                6'b010001
802
`define OR1200_OR32_JALR              6'b010010
803
`define OR1200_OR32_MACI              6'b010011
804
/* */
805
`define OR1200_OR32_LWZ               6'b100001
806
`define OR1200_OR32_LBZ               6'b100011
807
`define OR1200_OR32_LBS               6'b100100
808
`define OR1200_OR32_LHZ               6'b100101
809
`define OR1200_OR32_LHS               6'b100110
810
`define OR1200_OR32_ADDI              6'b100111
811
`define OR1200_OR32_ADDIC             6'b101000
812
`define OR1200_OR32_ANDI              6'b101001
813
`define OR1200_OR32_ORI               6'b101010
814
`define OR1200_OR32_XORI              6'b101011
815
`define OR1200_OR32_MULI              6'b101100
816
`define OR1200_OR32_MFSPR             6'b101101
817
`define OR1200_OR32_SH_ROTI           6'b101110
818
`define OR1200_OR32_SFXXI             6'b101111
819
/* */
820
`define OR1200_OR32_MTSPR             6'b110000
821
`define OR1200_OR32_MACMSB            6'b110001
822
/* */
823
`define OR1200_OR32_SW                6'b110101
824
`define OR1200_OR32_SB                6'b110110
825
`define OR1200_OR32_SH                6'b110111
826
`define OR1200_OR32_ALU               6'b111000
827
`define OR1200_OR32_SFXX              6'b111001
828
//`define OR1200_OR32_CUST5             6'b111100
829
 
830
 
831
/////////////////////////////////////////////////////
832
//
833
// Exceptions
834
//
835
 
836
//
837
// Exception vectors per OR1K architecture:
838
// 0xPPPPP100 - reset
839
// 0xPPPPP200 - bus error
840
// ... etc
841
// where P represents exception prefix.
842
//
843
// Exception vectors can be customized as per
844
// the following formula:
845
// 0xPPPPPNVV - exception N
846
//
847
// P represents exception prefix
848
// N represents exception N
849
// VV represents length of the individual vector space,
850
//   usually it is 8 bits wide and starts with all bits zero
851
//
852
 
853
//
854
// PPPPP and VV parts
855
//
856
// Sum of these two defines needs to be 28
857
//
858
`define OR1200_EXCEPT_EPH0_P 20'h00000
859
`define OR1200_EXCEPT_EPH1_P 20'hF0000
860
`define OR1200_EXCEPT_V            8'h00
861
 
862
//
863
// N part width
864
//
865
`define OR1200_EXCEPT_WIDTH 4
866
 
867
//
868
// Definition of exception vectors
869
//
870
// To avoid implementation of a certain exception,
871
// simply comment out corresponding line
872
//
873
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
874
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
875
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
876
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
877
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
878
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
879
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
880
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
881
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
882
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
883
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
884
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
885
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
886
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
887
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
888
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
889
 
890
 
891
/////////////////////////////////////////////////////
892
//
893
// SPR groups
894
//
895
 
896
// Bits that define the group
897
`define OR1200_SPR_GROUP_BITS   15:11
898
 
899
// Width of the group bits
900
`define OR1200_SPR_GROUP_WIDTH  5
901
 
902
// Bits that define offset inside the group
903
`define OR1200_SPR_OFS_BITS 10:0
904
 
905
// List of groups
906
`define OR1200_SPR_GROUP_SYS    5'd00
907
`define OR1200_SPR_GROUP_DMMU   5'd01
908
`define OR1200_SPR_GROUP_IMMU   5'd02
909
`define OR1200_SPR_GROUP_DC     5'd03
910
`define OR1200_SPR_GROUP_IC     5'd04
911
`define OR1200_SPR_GROUP_MAC    5'd05
912
`define OR1200_SPR_GROUP_DU     5'd06
913
`define OR1200_SPR_GROUP_PM     5'd08
914
`define OR1200_SPR_GROUP_PIC    5'd09
915
`define OR1200_SPR_GROUP_TT     5'd10
916
 
917
 
918
/////////////////////////////////////////////////////
919
//
920
// System group
921
//
922
 
923
//
924
// System registers
925
//
926
`define OR1200_SPR_CFGR         7'd0
927
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
928
`define OR1200_SPR_NPC          11'd16
929
`define OR1200_SPR_SR           11'd17
930
`define OR1200_SPR_PPC          11'd18
931
`define OR1200_SPR_EPCR         11'd32
932
`define OR1200_SPR_EEAR         11'd48
933
`define OR1200_SPR_ESR          11'd64
934
 
935
//
936
// SR bits
937
//
938
`define OR1200_SR_WIDTH 16
939
`define OR1200_SR_SM   0
940
`define OR1200_SR_TEE  1
941
`define OR1200_SR_IEE  2
942
`define OR1200_SR_DCE  3
943
`define OR1200_SR_ICE  4
944
`define OR1200_SR_DME  5
945
`define OR1200_SR_IME  6
946
`define OR1200_SR_LEE  7
947
`define OR1200_SR_CE   8
948
`define OR1200_SR_F    9
949
`define OR1200_SR_CY   10       // Unused
950
`define OR1200_SR_OV   11       // Unused
951
`define OR1200_SR_OVE  12       // Unused
952
`define OR1200_SR_DSX  13       // Unused
953
`define OR1200_SR_EPH  14
954
`define OR1200_SR_FO   15
955
`define OR1200_SR_CID  31:28    // Unimplemented
956
 
957
//
958
// Bits that define offset inside the group
959
//
960
`define OR1200_SPROFS_BITS 10:0
961
 
962
//
963
// Default Exception Prefix
964
//
965
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
966
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
967
//
968
`define OR1200_SR_EPH_DEF       1'b0
969
 
970
/////////////////////////////////////////////////////
971
//
972
// Power Management (PM)
973
//
974
 
975
// Define it if you want PM implemented
976
`define OR1200_PM_IMPLEMENTED
977
 
978
// Bit positions inside PMR (don't change)
979
`define OR1200_PM_PMR_SDF 3:0
980
`define OR1200_PM_PMR_DME 4
981
`define OR1200_PM_PMR_SME 5
982
`define OR1200_PM_PMR_DCGE 6
983
`define OR1200_PM_PMR_UNUSED 31:7
984
 
985
// PMR offset inside PM group of registers
986
`define OR1200_PM_OFS_PMR 11'b0
987
 
988
// PM group
989
`define OR1200_SPRGRP_PM 5'd8
990
 
991
// Define if PMR can be read/written at any address inside PM group
992
`define OR1200_PM_PARTIAL_DECODING
993
 
994
// Define if reading PMR is allowed
995
`define OR1200_PM_READREGS
996
 
997
// Define if unused PMR bits should be zero
998
`define OR1200_PM_UNUSED_ZERO
999
 
1000
 
1001
/////////////////////////////////////////////////////
1002
//
1003
// Debug Unit (DU)
1004
//
1005
 
1006
// Define it if you want DU implemented
1007
`define OR1200_DU_IMPLEMENTED
1008
 
1009
//
1010
// Define if you want HW Breakpoints
1011
// (if HW breakpoints are not implemented
1012
// only default software trapping is
1013
// possible with l.trap insn - this is
1014
// however already enough for use
1015
// with or32 gdb)
1016
//
1017
//`define OR1200_DU_HWBKPTS
1018
 
1019
// Number of DVR/DCR pairs if HW breakpoints enabled
1020
`define OR1200_DU_DVRDCR_PAIRS 8
1021
 
1022
// Define if you want trace buffer
1023
//`define OR1200_DU_TB_IMPLEMENTED
1024
 
1025
//
1026
// Address offsets of DU registers inside DU group
1027
//
1028
// To not implement a register, doq not define its address
1029
//
1030
`ifdef OR1200_DU_HWBKPTS
1031
`define OR1200_DU_DVR0          11'd0
1032
`define OR1200_DU_DVR1          11'd1
1033
`define OR1200_DU_DVR2          11'd2
1034
`define OR1200_DU_DVR3          11'd3
1035
`define OR1200_DU_DVR4          11'd4
1036
`define OR1200_DU_DVR5          11'd5
1037
`define OR1200_DU_DVR6          11'd6
1038
`define OR1200_DU_DVR7          11'd7
1039
`define OR1200_DU_DCR0          11'd8
1040
`define OR1200_DU_DCR1          11'd9
1041
`define OR1200_DU_DCR2          11'd10
1042
`define OR1200_DU_DCR3          11'd11
1043
`define OR1200_DU_DCR4          11'd12
1044
`define OR1200_DU_DCR5          11'd13
1045
`define OR1200_DU_DCR6          11'd14
1046
`define OR1200_DU_DCR7          11'd15
1047
`endif
1048
`define OR1200_DU_DMR1          11'd16
1049
`ifdef OR1200_DU_HWBKPTS
1050
`define OR1200_DU_DMR2          11'd17
1051
`define OR1200_DU_DWCR0         11'd18
1052
`define OR1200_DU_DWCR1         11'd19
1053
`endif
1054
`define OR1200_DU_DSR           11'd20
1055
`define OR1200_DU_DRR           11'd21
1056
`ifdef OR1200_DU_TB_IMPLEMENTED
1057
`define OR1200_DU_TBADR         11'h0ff
1058
`define OR1200_DU_TBIA          11'h1xx
1059
`define OR1200_DU_TBIM          11'h2xx
1060
`define OR1200_DU_TBAR          11'h3xx
1061
`define OR1200_DU_TBTS          11'h4xx
1062
`endif
1063
 
1064
// Position of offset bits inside SPR address
1065
`define OR1200_DUOFS_BITS       10:0
1066
 
1067
// DCR bits
1068
`define OR1200_DU_DCR_DP        0
1069
`define OR1200_DU_DCR_CC        3:1
1070
`define OR1200_DU_DCR_SC        4
1071
`define OR1200_DU_DCR_CT        7:5
1072
 
1073
// DMR1 bits
1074
`define OR1200_DU_DMR1_CW0      1:0
1075
`define OR1200_DU_DMR1_CW1      3:2
1076
`define OR1200_DU_DMR1_CW2      5:4
1077
`define OR1200_DU_DMR1_CW3      7:6
1078
`define OR1200_DU_DMR1_CW4      9:8
1079
`define OR1200_DU_DMR1_CW5      11:10
1080
`define OR1200_DU_DMR1_CW6      13:12
1081
`define OR1200_DU_DMR1_CW7      15:14
1082
`define OR1200_DU_DMR1_CW8      17:16
1083
`define OR1200_DU_DMR1_CW9      19:18
1084
`define OR1200_DU_DMR1_CW10     21:20
1085
`define OR1200_DU_DMR1_ST       22
1086
`define OR1200_DU_DMR1_BT       23
1087
`define OR1200_DU_DMR1_DXFW     24
1088
`define OR1200_DU_DMR1_ETE      25
1089
 
1090
// DMR2 bits
1091
`define OR1200_DU_DMR2_WCE0     0
1092
`define OR1200_DU_DMR2_WCE1     1
1093
`define OR1200_DU_DMR2_AWTC     12:2
1094
`define OR1200_DU_DMR2_WGB      23:13
1095
 
1096
// DWCR bits
1097
`define OR1200_DU_DWCR_COUNT    15:0
1098
`define OR1200_DU_DWCR_MATCH    31:16
1099
 
1100
// DSR bits
1101
`define OR1200_DU_DSR_WIDTH     14
1102
`define OR1200_DU_DSR_RSTE      0
1103
`define OR1200_DU_DSR_BUSEE     1
1104
`define OR1200_DU_DSR_DPFE      2
1105
`define OR1200_DU_DSR_IPFE      3
1106
`define OR1200_DU_DSR_TTE       4
1107
`define OR1200_DU_DSR_AE        5
1108
`define OR1200_DU_DSR_IIE       6
1109
`define OR1200_DU_DSR_IE        7
1110
`define OR1200_DU_DSR_DME       8
1111
`define OR1200_DU_DSR_IME       9
1112
`define OR1200_DU_DSR_RE        10
1113
`define OR1200_DU_DSR_SCE       11
1114
`define OR1200_DU_DSR_BE        12
1115
`define OR1200_DU_DSR_TE        13
1116
 
1117
// DRR bits
1118
`define OR1200_DU_DRR_RSTE      0
1119
`define OR1200_DU_DRR_BUSEE     1
1120
`define OR1200_DU_DRR_DPFE      2
1121
`define OR1200_DU_DRR_IPFE      3
1122
`define OR1200_DU_DRR_TTE       4
1123
`define OR1200_DU_DRR_AE        5
1124
`define OR1200_DU_DRR_IIE       6
1125
`define OR1200_DU_DRR_IE        7
1126
`define OR1200_DU_DRR_DME       8
1127
`define OR1200_DU_DRR_IME       9
1128
`define OR1200_DU_DRR_RE        10
1129
`define OR1200_DU_DRR_SCE       11
1130
`define OR1200_DU_DRR_BE        12
1131
`define OR1200_DU_DRR_TE        13
1132
 
1133
// Define if reading DU regs is allowed
1134
`define OR1200_DU_READREGS
1135
 
1136
// Define if unused DU registers bits should be zero
1137
`define OR1200_DU_UNUSED_ZERO
1138
 
1139
// Define if IF/LSU status is not needed by devel i/f
1140
`define OR1200_DU_STATUS_UNIMPLEMENTED
1141
 
1142
/////////////////////////////////////////////////////
1143
//
1144
// Programmable Interrupt Controller (PIC)
1145
//
1146
 
1147
// Define it if you want PIC implemented
1148
`define OR1200_PIC_IMPLEMENTED
1149
 
1150
// Define number of interrupt inputs (2-31)
1151
`define OR1200_PIC_INTS 20
1152
 
1153
// Address offsets of PIC registers inside PIC group
1154
`define OR1200_PIC_OFS_PICMR 2'd0
1155
`define OR1200_PIC_OFS_PICSR 2'd2
1156
 
1157
// Position of offset bits inside SPR address
1158
`define OR1200_PICOFS_BITS 1:0
1159
 
1160
// Define if you want these PIC registers to be implemented
1161
`define OR1200_PIC_PICMR
1162
`define OR1200_PIC_PICSR
1163
 
1164
// Define if reading PIC registers is allowed
1165
`define OR1200_PIC_READREGS
1166
 
1167
// Define if unused PIC register bits should be zero
1168
`define OR1200_PIC_UNUSED_ZERO
1169
 
1170
 
1171
/////////////////////////////////////////////////////
1172
//
1173
// Tick Timer (TT)
1174
//
1175
 
1176
// Define it if you want TT implemented
1177
`define OR1200_TT_IMPLEMENTED
1178
 
1179
// Address offsets of TT registers inside TT group
1180
`define OR1200_TT_OFS_TTMR 1'd0
1181
`define OR1200_TT_OFS_TTCR 1'd1
1182
 
1183
// Position of offset bits inside SPR group
1184
`define OR1200_TTOFS_BITS 0
1185
 
1186
// Define if you want these TT registers to be implemented
1187
`define OR1200_TT_TTMR
1188
`define OR1200_TT_TTCR
1189
 
1190
// TTMR bits
1191
`define OR1200_TT_TTMR_TP 27:0
1192
`define OR1200_TT_TTMR_IP 28
1193
`define OR1200_TT_TTMR_IE 29
1194
`define OR1200_TT_TTMR_M 31:30
1195
 
1196
// Define if reading TT registers is allowed
1197
`define OR1200_TT_READREGS
1198
 
1199
 
1200
//////////////////////////////////////////////
1201
//
1202
// MAC
1203
//
1204
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1205
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1206
 
1207
//
1208
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1209
//
1210
// According to architecture manual there is no shift, so default value is 0.
1211
//
1212
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1213
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1214
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1215
// dest_GPR = {MACHI,MACLO}[59:28]
1216
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1217
 
1218
 
1219
//////////////////////////////////////////////
1220
//
1221
// Data MMU (DMMU)
1222
//
1223
 
1224
//
1225
// Address that selects between TLB TR and MR
1226
//
1227
`define OR1200_DTLB_TM_ADDR     7
1228
 
1229
//
1230
// DTLBMR fields
1231
//
1232
`define OR1200_DTLBMR_V_BITS    0
1233
`define OR1200_DTLBMR_CID_BITS  4:1
1234
`define OR1200_DTLBMR_RES_BITS  11:5
1235
`define OR1200_DTLBMR_VPN_BITS  31:13
1236
 
1237
//
1238
// DTLBTR fields
1239
//
1240
`define OR1200_DTLBTR_CC_BITS   0
1241
`define OR1200_DTLBTR_CI_BITS   1
1242
`define OR1200_DTLBTR_WBC_BITS  2
1243
`define OR1200_DTLBTR_WOM_BITS  3
1244
`define OR1200_DTLBTR_A_BITS    4
1245
`define OR1200_DTLBTR_D_BITS    5
1246
`define OR1200_DTLBTR_URE_BITS  6
1247
`define OR1200_DTLBTR_UWE_BITS  7
1248
`define OR1200_DTLBTR_SRE_BITS  8
1249
`define OR1200_DTLBTR_SWE_BITS  9
1250
`define OR1200_DTLBTR_RES_BITS  11:10
1251
`define OR1200_DTLBTR_PPN_BITS  31:13
1252
 
1253
//
1254
// DTLB configuration
1255
//
1256
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1257
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1258
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1259
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1260
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1261
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1262
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1263
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1264
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1265
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1266
 
1267
//
1268
// Cache inhibit while DMMU is not enabled/implemented
1269
//
1270
// cache inhibited 0GB-4GB              1'b1
1271
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1272
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1273
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1274
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1275
// cached 0GB-4GB                       1'b0
1276
//
1277
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1278
 
1279
 
1280
//////////////////////////////////////////////
1281
//
1282
// Insn MMU (IMMU)
1283
//
1284
 
1285
//
1286
// Address that selects between TLB TR and MR
1287
//
1288
`define OR1200_ITLB_TM_ADDR     7
1289
 
1290
//
1291
// ITLBMR fields
1292
//
1293
`define OR1200_ITLBMR_V_BITS    0
1294
`define OR1200_ITLBMR_CID_BITS  4:1
1295
`define OR1200_ITLBMR_RES_BITS  11:5
1296
`define OR1200_ITLBMR_VPN_BITS  31:13
1297
 
1298
//
1299
// ITLBTR fields
1300
//
1301
`define OR1200_ITLBTR_CC_BITS   0
1302
`define OR1200_ITLBTR_CI_BITS   1
1303
`define OR1200_ITLBTR_WBC_BITS  2
1304
`define OR1200_ITLBTR_WOM_BITS  3
1305
`define OR1200_ITLBTR_A_BITS    4
1306
`define OR1200_ITLBTR_D_BITS    5
1307
`define OR1200_ITLBTR_SXE_BITS  6
1308
`define OR1200_ITLBTR_UXE_BITS  7
1309
`define OR1200_ITLBTR_RES_BITS  11:8
1310
`define OR1200_ITLBTR_PPN_BITS  31:13
1311
 
1312
//
1313
// ITLB configuration
1314
//
1315
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1316
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1317
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1318
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1319
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1320
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1321
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1322
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1323
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1324
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1325
 
1326
//
1327
// Cache inhibit while IMMU is not enabled/implemented
1328
// Note: all combinations that use icpu_adr_i cause async loop
1329
//
1330
// cache inhibited 0GB-4GB              1'b1
1331
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1332
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1333
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1334
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1335
// cached 0GB-4GB                       1'b0
1336
//
1337
`define OR1200_IMMU_CI                  1'b0
1338
 
1339
 
1340
/////////////////////////////////////////////////
1341
//
1342
// Insn cache (IC)
1343
//
1344
 
1345
// 3 for 8 bytes, 4 for 16 bytes etc
1346
`define OR1200_ICLS             4
1347
 
1348
//
1349
// IC configurations
1350
//
1351
`ifdef OR1200_IC_1W_512B
1352
`define OR1200_ICSIZE   9     // 512
1353
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1354
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1355
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1356
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1357
`define OR1200_ICTAG_W  24
1358
`endif
1359
`ifdef OR1200_IC_1W_4KB
1360
`define OR1200_ICSIZE                   12                      // 4096
1361
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1362
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1363
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1364
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1365
`define OR1200_ICTAG_W                  21
1366
`endif
1367
`ifdef OR1200_IC_1W_8KB
1368
`define OR1200_ICSIZE                   13                      // 8192
1369
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1370
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1371
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1372
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1373
`define OR1200_ICTAG_W                  20
1374
`endif
1375
 
1376
 
1377
/////////////////////////////////////////////////
1378
//
1379
// Data cache (DC)
1380
//
1381
 
1382
// 3 for 8 bytes, 4 for 16 bytes etc
1383
`define OR1200_DCLS             4
1384
 
1385
// Define to perform store refill (potential performance penalty)
1386
// `define OR1200_DC_STORE_REFILL
1387
 
1388
//
1389
// DC configurations
1390
//
1391
`ifdef OR1200_DC_1W_4KB
1392
`define OR1200_DCSIZE                   12                      // 4096
1393
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1394
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1395
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1396
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1397
`define OR1200_DCTAG_W                  21
1398
`endif
1399
`ifdef OR1200_DC_1W_8KB
1400
`define OR1200_DCSIZE                   13                      // 8192
1401
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1402
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1403
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1404
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1405
`define OR1200_DCTAG_W                  20
1406
`endif
1407
 
1408
/////////////////////////////////////////////////
1409
//
1410
// Store buffer (SB)
1411
//
1412
 
1413
//
1414
// Store buffer
1415
//
1416
// It will improve performance by "caching" CPU stores
1417
// using store buffer. This is most important for function
1418
// prologues because DC can only work in write though mode
1419
// and all stores would have to complete external WB writes
1420
// to memory.
1421
// Store buffer is between DC and data BIU.
1422
// All stores will be stored into store buffer and immediately
1423
// completed by the CPU, even though actual external writes
1424
// will be performed later. As a consequence store buffer masks
1425
// all data bus errors related to stores (data bus errors
1426
// related to loads are delivered normally).
1427
// All pending CPU loads will wait until store buffer is empty to
1428
// ensure strict memory model. Right now this is necessary because
1429
// we don't make destinction between cached and cache inhibited
1430
// address space, so we simply empty store buffer until loads
1431
// can begin.
1432
//
1433
// It makes design a bit bigger, depending what is the number of
1434
// entries in SB FIFO. Number of entries can be changed further
1435
// down.
1436
//
1437
//`define OR1200_SB_IMPLEMENTED
1438
 
1439
//
1440
// Number of store buffer entries
1441
//
1442
// Verified number of entries are 4 and 8 entries
1443
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1444
// always match 2**OR1200_SB_LOG.
1445
// To disable store buffer, undefine
1446
// OR1200_SB_IMPLEMENTED.
1447
//
1448
`define OR1200_SB_LOG           2       // 2 or 3
1449
`define OR1200_SB_ENTRIES       4       // 4 or 8
1450
 
1451
 
1452
/////////////////////////////////////////////////
1453
//
1454
// Quick Embedded Memory (QMEM)
1455
//
1456
 
1457
//
1458
// Quick Embedded Memory
1459
//
1460
// Instantiation of dedicated insn/data memory (RAM or ROM).
1461
// Insn fetch has effective throughput 1insn / clock cycle.
1462
// Data load takes two clock cycles / access, data store
1463
// takes 1 clock cycle / access (if there is no insn fetch)).
1464
// Memory instantiation is shared between insn and data,
1465
// meaning if insn fetch are performed, data load/store
1466
// performance will be lower.
1467
//
1468
// Main reason for QMEM is to put some time critical functions
1469
// into this memory and to have predictable and fast access
1470
// to these functions. (soft fpu, context switch, exception
1471
// handlers, stack, etc)
1472
//
1473
// It makes design a bit bigger and slower. QMEM sits behind
1474
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1475
// used with QMEM and QMEM is seen by the CPU just like any other
1476
// memory in the system). IC/DC are sitting behind QMEM so the
1477
// whole design timing might be worse with QMEM implemented.
1478
//
1479
`define OR1200_QMEM_IMPLEMENTED
1480
 
1481
//
1482
// Base address and mask of QMEM
1483
//
1484
// Base address defines first address of QMEM. Mask defines
1485
// QMEM range in address space. Actual size of QMEM is however
1486
// determined with instantiated RAM/ROM. However bigger
1487
// mask will reserve more address space for QMEM, but also
1488
// make design faster, while more tight mask will take
1489
// less address space but also make design slower. If
1490
// instantiated RAM/ROM is smaller than space reserved with
1491
// the mask, instatiated RAM/ROM will also be shadowed
1492
// at higher addresses in reserved space.
1493
//
1494
`define OR1200_QMEM_IADDR       32'h0080_0000
1495
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1496
`define OR1200_QMEM_DADDR  32'h0080_0000
1497
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1498
 
1499
//
1500
// QMEM interface byte-select capability
1501
//
1502
// To enable qmem_sel* ports, define this macro.
1503
//
1504
//`define OR1200_QMEM_BSEL
1505
 
1506
//
1507
// QMEM interface acknowledge
1508
//
1509
// To enable qmem_ack port, define this macro.
1510
//
1511
//`define OR1200_QMEM_ACK
1512
 
1513
/////////////////////////////////////////////////////
1514
//
1515
// VR, UPR and Configuration Registers
1516
//
1517
//
1518
// VR, UPR and configuration registers are optional. If
1519
// implemented, operating system can automatically figure
1520
// out how to use the processor because it knows
1521
// what units are available in the processor and how they
1522
// are configured.
1523
//
1524
// This section must be last in or1200_defines.v file so
1525
// that all units are already configured and thus
1526
// configuration registers are properly set.
1527
//
1528
 
1529
// Define if you want configuration registers implemented
1530
`define OR1200_CFGR_IMPLEMENTED
1531
 
1532
// Define if you want full address decode inside SYS group
1533
`define OR1200_SYS_FULL_DECODE
1534
 
1535
// Offsets of VR, UPR and CFGR registers
1536
`define OR1200_SPRGRP_SYS_VR            4'h0
1537
`define OR1200_SPRGRP_SYS_UPR           4'h1
1538
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1539
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1540
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1541
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1542
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1543
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1544
 
1545
// VR fields
1546
`define OR1200_VR_REV_BITS              5:0
1547
`define OR1200_VR_RES1_BITS             15:6
1548
`define OR1200_VR_CFG_BITS              23:16
1549
`define OR1200_VR_VER_BITS              31:24
1550
 
1551
// VR values
1552
`define OR1200_VR_REV                   6'h01
1553
`define OR1200_VR_RES1                  10'h000
1554
`define OR1200_VR_CFG                   8'h00
1555
`define OR1200_VR_VER                   8'h12
1556
 
1557
// UPR fields
1558
`define OR1200_UPR_UP_BITS              0
1559
`define OR1200_UPR_DCP_BITS             1
1560
`define OR1200_UPR_ICP_BITS             2
1561
`define OR1200_UPR_DMP_BITS             3
1562
`define OR1200_UPR_IMP_BITS             4
1563
`define OR1200_UPR_MP_BITS              5
1564
`define OR1200_UPR_DUP_BITS             6
1565
`define OR1200_UPR_PCUP_BITS            7
1566
`define OR1200_UPR_PMP_BITS             8
1567
`define OR1200_UPR_PICP_BITS            9
1568
`define OR1200_UPR_TTP_BITS             10
1569
`define OR1200_UPR_RES1_BITS            23:11
1570
`define OR1200_UPR_CUP_BITS             31:24
1571
 
1572
// UPR values
1573
`define OR1200_UPR_UP                   1'b1
1574
`ifdef OR1200_NO_DC
1575
`define OR1200_UPR_DCP                  1'b0
1576
`else
1577
`define OR1200_UPR_DCP                  1'b1
1578
`endif
1579
`ifdef OR1200_NO_IC
1580
`define OR1200_UPR_ICP                  1'b0
1581
`else
1582
`define OR1200_UPR_ICP                  1'b1
1583
`endif
1584
`ifdef OR1200_NO_DMMU
1585
`define OR1200_UPR_DMP                  1'b0
1586
`else
1587
`define OR1200_UPR_DMP                  1'b1
1588
`endif
1589
`ifdef OR1200_NO_IMMU
1590
`define OR1200_UPR_IMP                  1'b0
1591
`else
1592
`define OR1200_UPR_IMP                  1'b1
1593
`endif
1594
`define OR1200_UPR_MP                   1'b1    // MAC always present
1595
`ifdef OR1200_DU_IMPLEMENTED
1596
`define OR1200_UPR_DUP                  1'b1
1597
`else
1598
`define OR1200_UPR_DUP                  1'b0
1599
`endif
1600
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1601
`ifdef OR1200_DU_IMPLEMENTED
1602
`define OR1200_UPR_PMP                  1'b1
1603
`else
1604
`define OR1200_UPR_PMP                  1'b0
1605
`endif
1606
`ifdef OR1200_DU_IMPLEMENTED
1607
`define OR1200_UPR_PICP                 1'b1
1608
`else
1609
`define OR1200_UPR_PICP                 1'b0
1610
`endif
1611
`ifdef OR1200_DU_IMPLEMENTED
1612
`define OR1200_UPR_TTP                  1'b1
1613
`else
1614
`define OR1200_UPR_TTP                  1'b0
1615
`endif
1616
`define OR1200_UPR_RES1                 13'h0000
1617
`define OR1200_UPR_CUP                  8'h00
1618
 
1619
// CPUCFGR fields
1620
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1621
`define OR1200_CPUCFGR_HGF_BITS 4
1622
`define OR1200_CPUCFGR_OB32S_BITS       5
1623
`define OR1200_CPUCFGR_OB64S_BITS       6
1624
`define OR1200_CPUCFGR_OF32S_BITS       7
1625
`define OR1200_CPUCFGR_OF64S_BITS       8
1626
`define OR1200_CPUCFGR_OV64S_BITS       9
1627
`define OR1200_CPUCFGR_RES1_BITS        31:10
1628
 
1629
// CPUCFGR values
1630
`define OR1200_CPUCFGR_NSGF             4'h0
1631
`define OR1200_CPUCFGR_HGF              1'b0
1632
`define OR1200_CPUCFGR_OB32S            1'b1
1633
`define OR1200_CPUCFGR_OB64S            1'b0
1634
`define OR1200_CPUCFGR_OF32S            1'b0
1635
`define OR1200_CPUCFGR_OF64S            1'b0
1636
`define OR1200_CPUCFGR_OV64S            1'b0
1637
`define OR1200_CPUCFGR_RES1             22'h000000
1638
 
1639
// DMMUCFGR fields
1640
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1641
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1642
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1643
`define OR1200_DMMUCFGR_CRI_BITS        8
1644
`define OR1200_DMMUCFGR_PRI_BITS        9
1645
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1646
`define OR1200_DMMUCFGR_HTR_BITS        11
1647
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1648
 
1649
// DMMUCFGR values
1650
`ifdef OR1200_NO_DMMU
1651
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1652
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1653
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1654
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1655
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1656
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1657
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1658
`define OR1200_DMMUCFGR_RES1            20'h00000
1659
`else
1660
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1661
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1662
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1663
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1664
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1665
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1666
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1667
`define OR1200_DMMUCFGR_RES1            20'h00000
1668
`endif
1669
 
1670
// IMMUCFGR fields
1671
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1672
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1673
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1674
`define OR1200_IMMUCFGR_CRI_BITS        8
1675
`define OR1200_IMMUCFGR_PRI_BITS        9
1676
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1677
`define OR1200_IMMUCFGR_HTR_BITS        11
1678
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1679
 
1680
// IMMUCFGR values
1681
`ifdef OR1200_NO_IMMU
1682
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1683
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1684
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1685
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1686
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1687
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1688
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1689
`define OR1200_IMMUCFGR_RES1            20'h00000
1690
`else
1691
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1692
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1693
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1694
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1695
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1696
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1697
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1698
`define OR1200_IMMUCFGR_RES1            20'h00000
1699
`endif
1700
 
1701
// DCCFGR fields
1702
`define OR1200_DCCFGR_NCW_BITS          2:0
1703
`define OR1200_DCCFGR_NCS_BITS          6:3
1704
`define OR1200_DCCFGR_CBS_BITS          7
1705
`define OR1200_DCCFGR_CWS_BITS          8
1706
`define OR1200_DCCFGR_CCRI_BITS         9
1707
`define OR1200_DCCFGR_CBIRI_BITS        10
1708
`define OR1200_DCCFGR_CBPRI_BITS        11
1709
`define OR1200_DCCFGR_CBLRI_BITS        12
1710
`define OR1200_DCCFGR_CBFRI_BITS        13
1711
`define OR1200_DCCFGR_CBWBRI_BITS       14
1712
`define OR1200_DCCFGR_RES1_BITS 31:15
1713
 
1714
// DCCFGR values
1715
`ifdef OR1200_NO_DC
1716
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1717
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1718
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1719
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1720
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1721
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1722
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1723
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1724
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1725
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1726
`define OR1200_DCCFGR_RES1              17'h00000
1727
`else
1728
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1729
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1730
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1731
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1732
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1733
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1734
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1735
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1736
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1737
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1738
`define OR1200_DCCFGR_RES1              17'h00000
1739
`endif
1740
 
1741
// ICCFGR fields
1742
`define OR1200_ICCFGR_NCW_BITS          2:0
1743
`define OR1200_ICCFGR_NCS_BITS          6:3
1744
`define OR1200_ICCFGR_CBS_BITS          7
1745
`define OR1200_ICCFGR_CWS_BITS          8
1746
`define OR1200_ICCFGR_CCRI_BITS         9
1747
`define OR1200_ICCFGR_CBIRI_BITS        10
1748
`define OR1200_ICCFGR_CBPRI_BITS        11
1749
`define OR1200_ICCFGR_CBLRI_BITS        12
1750
`define OR1200_ICCFGR_CBFRI_BITS        13
1751
`define OR1200_ICCFGR_CBWBRI_BITS       14
1752
`define OR1200_ICCFGR_RES1_BITS 31:15
1753
 
1754
// ICCFGR values
1755
`ifdef OR1200_NO_IC
1756
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1757
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1758
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1759
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1760
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1761
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1762
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1763
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1764
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1765
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1766
`define OR1200_ICCFGR_RES1              17'h00000
1767
`else
1768
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1769
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1770
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1771
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1772
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1773
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1774
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1775
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1776
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1777
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1778
`define OR1200_ICCFGR_RES1              17'h00000
1779
`endif
1780
 
1781
// DCFGR fields
1782
`define OR1200_DCFGR_NDP_BITS           2:0
1783
`define OR1200_DCFGR_WPCI_BITS          3
1784
`define OR1200_DCFGR_RES1_BITS          31:4
1785
 
1786
// DCFGR values
1787
`ifdef OR1200_DU_HWBKPTS
1788
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1789
`ifdef OR1200_DU_DWCR0
1790
`define OR1200_DCFGR_WPCI               1'b1
1791
`else
1792
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1793
`endif
1794
`else
1795
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1796
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1797
`endif
1798
`define OR1200_DCFGR_RES1               28'h0000000
1799
 

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