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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [ram_wb/] [ram_wb.yaml] - Blame information for rev 8

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Line No. Rev Author Line
1 7 feddischso
SOCM_CORE
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name: ram_wb
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description: Onchip-RAM
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version: b3
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license: LGPL
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licensefile:
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author:
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authormail:
9 8 feddischso
vccmd:
10 7 feddischso
toplevel: ram_wb_b3
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interfaces:
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  :wb_ifc: SOCM_IFC
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    name: wishbone_sl
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    dir: 1
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    version: "b3"
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    ports:
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      :wb_adr_i: SOCM_PORT
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        len: 32
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        defn: adr
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      :wb_bte_i: SOCM_PORT
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        len: 2
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        defn: bte
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      :wb_cti_i: SOCM_PORT
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        len: 3
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        defn: cti
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      :wb_cyc_i: SOCM_PORT
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        len: 1
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        defn: cyc
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      :wb_dat_i: SOCM_PORT
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        len: 32
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        defn: dat_o
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      :wb_sel_i: SOCM_PORT
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        len: 4
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        defn: sel
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      :wb_stb_i: SOCM_PORT
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        len: 1
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        defn: stb
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      :wb_we_i: SOCM_PORT
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        len: 1
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        defn: we
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      :wb_ack_o: SOCM_PORT
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        len: 1
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        defn: ack
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      :wb_err_o: SOCM_PORT
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        len: 1
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        defn: err
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      :wb_rty_o: SOCM_PORT
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        len: 1
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        defn: rty
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      :wb_dat_o: SOCM_PORT
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        len: 32
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        defn: dat_i
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      :wb_clk_i: SOCM_PORT
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        len: 1
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        defn: clk
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      :wb_rst_i: SOCM_PORT
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        len: 1
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        defn: rst
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static_parameters:
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  :ram_wb_b3: SOCM_SPARAM
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    dir: .
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    path: ./ram_wb_b3.v.in
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    file_dst: ram_wb_b3.v
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    parameters:
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      :MEM_SIZE: SOCM_SENTRY
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         token: TOK_MEM_SIZE
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         type:  integer
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         visible: true
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         editable: true
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         default: 20
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      :MEM_ADR_WIDTH: SOCM_SENTRY
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         token: TOK_MEM_ADR_WIDTH
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         type:  integer
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         visible: true
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         editable: true
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         default: 15
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