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[/] [soc_maker/] [trunk/] [lib/] [soc_maker/] [hdl_coder.rb] - Blame information for rev 8

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1 3 feddischso
###############################################################
2
#
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#  File:      hdl_coder.rb
4
#
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#  Author:    Christian Hättich
6
#
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#  Project:   System-On-Chip Maker
8
#
9
#  Target:    Linux / Windows / Mac
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#
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#  Language:  ruby
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#
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#
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###############################################################
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#
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#
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#   Copyright (C) 2014  Christian Hättich  - feddischson [ at ] opencores.org
18
#
19
#   This program is free software: you can redistribute it and/or modify
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#   it under the terms of the GNU General Public License as published by
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#   the Free Software Foundation, either version 3 of the License, or
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#   (at your option) any later version.
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#
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#   This program is distributed in the hope that it will be useful,
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#   but WITHOUT ANY WARRANTY; without even the implied warranty of
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#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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#   GNU General Public License for more details.
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#
29
#   You should have received a copy of the GNU General Public License
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#   along with this program.  If not, see .
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#
32
#
33
###############################################################
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#
35
#   Description:
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#     This file contains two HDL-coders:
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#      - VHDLCoder
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#      - VerilogCoder (not implemented, yet)
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#
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#
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#
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###############################################################
43
 
44
module SOCMaker
45
class HDLCoder
46
 
47
  def initialize
48
    @decl_part  = "";   # declaration
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    @asgn_part  = "";   # assignment
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    @inst_part  = "";   # instantiation
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52
 
53
 
54
  end
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56
 
57
end
58
 
59
 
60
class VerilogCoder < HDLCoder
61
  #TODO
62 7 feddischso
  #
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  #
64
 
65
  def filename( name )
66
    return name + ".v"
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  end
68
 
69 3 feddischso
end
70
 
71
 
72
class VHDLCoder < HDLCoder
73
 
74
 
75
 
76
 
77
  #
78
  # Add a component declaration to the declaration-string @decl_part
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  # This for example looks like
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  # component <> is
81
  #  generic(
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  #    g1 : ...
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  #    g2 : ...
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  #    ...
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  #    );
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  #  port(
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  #    p1 : ...
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  #    p2 : ...
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  #    p3 : ...
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  #    ...
91
  #    )
92
  #  end component <>;
93
  #
94
  # In addition, we add some VHDL comments (author, mail, license)
95
  #
96 7 feddischso
  def add_core_component( core_name, core_spec )
97 5 feddischso
 
98 3 feddischso
    @decl_part << "--\n"
99
    @decl_part << "-- core author: #{core_spec.author} - #{core_spec.authormail}\n"
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    @decl_part << "-- license: #{core_spec.license}\n"
101
    @decl_part << "--\n"
102
    @decl_part << "component #{core_spec.toplevel} is\n"
103
    generic_str = entity_generic_str( core_spec );
104
    @decl_part << "generic ( #{ generic_str  });\n" if generic_str.size > 0
105
    @decl_part << "port( \n" << entity_port_str( core_spec ) <<" );\n"
106
    @decl_part << "end component #{core_spec.toplevel};\n"
107 7 feddischso
    #entity_generic_str( core_spec )
108 3 feddischso
  end
109
 
110 7 feddischso
  def filename( name )
111
    return name + ".vhd"
112
  end
113 3 feddischso
 
114
 
115
  def entity_generic_str( core )
116
 
117
    generic_str = ""
118
    core.generics do |gen_name, gen_type, gen_val, is_last|
119
      generic_str     << gen_name << " : " << gen_type << " := " << gen_val.to_s
120
      generic_str     << ";" unless is_last
121
      generic_str     << "\n"
122
    end
123
    return generic_str
124
  end
125
 
126
 
127
  #
128
  # Create a string, which lists all signals of 'core'
129
  # We iterate over all interface:
130
  # For each interface, we iterate over all ports:
131
  # For each port, we lookup the definition in the 'soc_lib' and
132
  # add the VHDL code according to the definition as string to
133
  # port_string
134
  #
135
  def entity_port_str( core )
136
    port_string = ""
137
 
138 8 feddischso
    core.ports do |port_name, port_dir, port_len, port_default, is_last |
139 3 feddischso
 
140
      # The string we are add in every iteration looks for example like
141
      #    myportname1 :  out std_logic_vector( 6-1 downto 0 )
142
      #    or
143
      #    myportname2 :  in  std_logic
144
      #
145
      port_string << port_name.to_s << " : "
146
 
147 7 feddischso
 
148
 
149 3 feddischso
      # port direction
150
      if    port_dir == 2
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        port_string << " inout "
152
      elsif port_dir == 1
153
        port_string << " in "
154
      else
155
        port_string << " out "
156
      end
157
 
158
      # port type / length
159
      if(   port_len.is_a?( String ) ||
160
          ( port_len.is_a?( Fixnum ) && port_len > 1 )
161
        )
162
        port_string << " std_logic_vector( #{port_len}-1 downto 0 ) "
163
      elsif ( port_len.is_a?( Fixnum ) && port_len == 1 )
164
        port_string << " std_logic "
165
      else
166 7 feddischso
        puts "FAILED " + port_len.to_s #TODO
167 3 feddischso
      end
168
 
169
      # end of the line
170
      port_string << ";" unless is_last
171
      port_string << "\n"
172
    end
173
    return port_string
174
  end
175
 
176
 
177 7 feddischso
  def add_core_instance( inst_name, inst )
178 3 feddischso
 
179
    @inst_part << inst_name << " : " << inst.defn.toplevel << "\n"
180
    generic_str = ""
181
    inst.generics do |generic, type, value, is_last|
182
      generic_str << "#{generic} => #{value}"
183
      generic_str << "," unless is_last
184
      generic_str << "\n"
185
    end
186
    @inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
187
    port_str = ""
188 8 feddischso
    inst.ports do |port_name, dir, length, default, is_last|
189 3 feddischso
      port_str << "#{port_name} => #{inst_name}_#{port_name}"
190
      port_str << "," unless is_last
191
      port_str << "\n"
192
      if length > 1
193
        @decl_part << "signal #{inst_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
194
      else
195
        @decl_part << "signal #{inst_name}_#{port_name} : std_logic;\n"
196
      end
197
    end
198
    @inst_part << "port map( \n#{port_str} );\n\n\n" if port_str.size > 0
199
 
200
  end
201
 
202 8 feddischso
  def add_ifc_default_assignment( inst, inst_name, ifc_name, default  )
203 3 feddischso
 
204 8 feddischso
 
205
    tmp = ""
206
    inst.ports( ifc_name.to_s ) do |port_name, dir, length, default, is_last|
207
      if dir == 1 # assign default value only if it is an input
208
        if length > 1
209
          tmp << "#{inst_name}_#{port_name} <= ( others => '#{default}' );\n"
210
        else
211
          tmp << "#{inst_name}_#{port_name} <= '#{default}';\n"
212
        end
213
      end
214
    end
215
   @asgn_part << tmp
216
 
217
  end
218 3 feddischso
 
219 7 feddischso
  def add_ifc_connection( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
220 3 feddischso
 
221 7 feddischso
    ###
222
    #
223
    # declaration
224
    #
225
    #
226 3 feddischso
    ifc_spec.ports.each do |port_name, port|
227
      @decl_part << "signal #{ifc_name}_#{port_name.to_s} : "
228
      if length[ port_name ] > 1
229
        @decl_part << " std_logic_vector( #{length[ port_name ]}-1 downto 0 ) "
230
      else
231
        @decl_part << " std_logic "
232
      end
233
      # end of the line
234
      @decl_part << ";\n"
235
    end
236
 
237
 
238 7 feddischso
    ###
239
    #
240
    # assignment
241
    #
242
    #
243 8 feddischso
    ifc_spec.ports.each do |port_name, port_setup|
244
 
245
 
246
      if port_setup[ :dir ] == 0
247 3 feddischso
        src_inst_sel = src_inst
248
        dst_inst_sel = dst_inst
249
        src_ifc_sel  = src_ifc
250
        dst_ifc_sel  = dst_ifc
251
      else
252
        src_inst_sel = dst_inst
253
        dst_inst_sel = src_inst
254
        src_ifc_sel  = dst_ifc
255
        dst_ifc_sel  = src_ifc
256
      end
257
 
258
 
259 5 feddischso
      # length == 0 means, that no
260
      # signal is assigned to this connection
261
      if length[ port_name ] > 0
262 3 feddischso
 
263 5 feddischso
        port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
264 3 feddischso
 
265 5 feddischso
 
266
        # combine all sources
267
        tmp = "#{port_tmp_name} <= "
268
        # loop over instances
269
        src_inst_sel.each_with_index do |(inst_name, inst), i|
270
          ( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
271
          if port != nil
272 8 feddischso
            if port[ :len ] < length[ port_name ]
273
              tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & "
274
            end
275 5 feddischso
            tmp << "#{inst_name}_#{tmp_name}"
276
            tmp << " and \n" unless i == src_inst_sel.size-1
277 8 feddischso
          else
278
            puts "#{port_tmp_name}: #{length[port_name] > 1}"
279
            if length[ port_name ] > 1
280
              tmp << "( others => '0' )"
281
            else
282
              tmp << "'0'"
283
            end
284 5 feddischso
          end
285
        end
286 3 feddischso
        tmp << ";\n"
287 8 feddischso
        @asgn_part << tmp
288 5 feddischso
 
289 7 feddischso
        tmp = ""
290
        assigned = false
291 5 feddischso
        # assign to destination
292
        dst_inst_sel.each_with_index do |(inst_name, inst), i|
293 7 feddischso
          if not inst == nil  #TODO
294
            ( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
295
            if port != nil
296
              tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}"
297
              tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1
298
              tmp << ";\n"
299
              assigned = true
300
            end
301 5 feddischso
          end
302
        end
303 7 feddischso
        @asgn_part << tmp if assigned
304 8 feddischso
        puts "NOT ASSIGNED DST" if not assigned
305
      else
306
      #  puts "ifc #{ifc_name} port #{port_name.to_s} is not assigned"
307
      #  p src_ifc
308
      #  p dst_ifc
309
      #  tmp = ""
310
      #  dst_inst_sel.each_with_index do |(inst_name, inst), i|
311
      #    p inst_name
312
      #    p port_name
313
      #    ( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
314
      #    tmp << "#{inst_name}_#{tmp_name} <= ( others => 'X' );\n"
315
      #  end
316
      #  @asgn_part << tmp;
317 3 feddischso
      end
318
 
319
    end
320
  end
321
 
322
 
323
 
324 7 feddischso
  def get_hdl_code( soc, entity_name )
325 5 feddischso
    add_toplevel_sig( soc, entity_name )
326
    entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") + "\n"
327 3 feddischso
    entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n"
328
    entity_str << "-- Date: #{Time.now}\n"
329
    entity_str << SOCMaker::conf[ :vhdl_include ] + "\n"
330
    entity_str << "entity #{entity_name} is \n"
331
    tmp = entity_port_str( soc )
332
    entity_str << "port( \n" << tmp << " );\n" if tmp.size > 0
333
    entity_str << "end entity #{entity_name};\n\n\n"
334
    entity_str << "ARCHITECTURE IMPL of #{entity_name} is \n"
335
    entity_str << @decl_part
336
    entity_str << "\n\n"
337
    entity_str << "begin"
338
    entity_str << "\n\n"
339
    entity_str << "--"
340
    entity_str << "-- assignments "
341
    entity_str << "--"
342
    entity_str << "\n\n"
343
    entity_str << @asgn_part
344
    entity_str << "\n\n"
345
    entity_str << "--"
346
    entity_str << "-- instances "
347
    entity_str << "--"
348
    entity_str << "\n\n"
349
    entity_str << @inst_part
350
    entity_str << "end ARCHITECTURE IMPL;"
351
    return entity_str
352
  end
353
 
354 5 feddischso
  def add_toplevel_sig( soc, entity_name )
355 7 feddischso
    soc.ports do |port_name, dir, length, is_last|
356
      if dir == 0
357
        @asgn_part << "#{port_name} <= #{entity_name}_#{port_name}"
358
      else
359
        @asgn_part << "#{entity_name}_#{port_name} <= #{port_name} "
360
      end
361
      @asgn_part << ";\n"
362 5 feddischso
      if length > 1
363
        @decl_part << "signal #{entity_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
364
      else
365
        @decl_part << "signal #{entity_name}_#{port_name} : std_logic;\n"
366
      end
367
    end
368
  end
369 3 feddischso
 
370
 
371
 
372
  def asgn_str( ifc_spec, con,  ifc_name, core1, core1_name, core2, core2_name )
373
    port_string = ""
374
 
375
    { core1 => [ con[ :ifc1 ], :src1 ],
376
      core2 => [ con[ :ifc2 ], :src2 ] }.each do| core, tmp |
377
 
378
      core.ports( tmp[0] ) do | port_spec_name, port_name, port_dir |
379
 
380
        if port_dir  == 0
381
          port_string << "#{ifc_name}_#{port_spec_name}"
382
          port_string << " <= "
383
          port_string << "#{con[ tmp[1] ]}_#{port_name}"
384
          port_string << ";\n"
385
        else
386
          port_string << "#{con[ tmp[1] ]}_#{port_name}"
387
          port_string << " <= "
388
          port_string << "#{ifc_name}_#{port_spec_name }"
389
          port_string << ";\n"
390
        end
391
      end
392
 
393
    end
394
 
395
    return port_string
396
  end
397
 
398
 
399
 
400
 
401
 
402
end
403
end
404
 
405
# vim: noai:ts=2:sw=2

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