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[/] [soc_maker/] [trunk/] [spec/] [test_soc_lib/] [cores/] [core_B_rel1/] [core_b.vhd] - Blame information for rev 3

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1 3 feddischso
library ieee;
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use ieee.std_logic_1164.ALL;
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entity core_b is
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port(
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   mysig_con1a : out std_logic_vector( 7 downto 0 );
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   mysig_con1b : out std_logic_vector( 31 downto 0 );
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   mysig_con1c : in  std_logic
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);
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end entity core_b;
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architecture IMPL of core_b is
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begin
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   mysig_con1a <= "11001010";
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   mysig_con1b <= ( others => '1' );
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end architecture IMPL;
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