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jorisvr |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- Modified by Joris van Rantwijk for use with SpaceWire Light.
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------------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.can.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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use gaisler.spacewire.all;
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use gaisler.grusb.all;
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library esa;
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use esa.memoryctrl.all;
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library unisim;
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use unisim.vcomponents.DCM;
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use work.config.all;
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jorisvr |
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-- These statements are used in case SpaceWire Light is synthesized locally,
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-- separate from the rest of GRLIB.
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jorisvr |
use work.spwpkg.all;
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use work.spwambapkg.all;
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jorisvr |
---- The following statements should be used instead if SpaceWire Light
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---- has been integrated into GRLIB.
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-- library opencores;
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-- use opencores.spwpkg.all;
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-- use opencores.spwambapkg.all;
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jorisvr |
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic; -- 50 MHz main clock
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clk3 : in std_ulogic; -- 25 MHz ethernet clock
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pllref : in std_ulogic;
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errorn : out std_ulogic;
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wdogn : out std_ulogic;
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address : out std_logic_vector(27 downto 0);
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data : inout std_logic_vector(31 downto 0);
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ramsn : out std_logic_vector (4 downto 0);
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ramoen : out std_logic_vector (4 downto 0);
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rwen : out std_logic_vector (3 downto 0);
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oen : out std_ulogic;
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writen : out std_ulogic;
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read : out std_ulogic;
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iosn : out std_ulogic;
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bexcn : in std_ulogic; -- DSU rx data
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brdyn : in std_ulogic; -- DSU rx data
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romsn : out std_logic_vector (1 downto 0);
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sdclk : out std_ulogic;
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sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
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sdwen : out std_ulogic; -- sdram write enable
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sdrasn : out std_ulogic; -- sdram ras
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sdcasn : out std_ulogic; -- sdram cas
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sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
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dsuen : in std_ulogic;
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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txd1 : out std_ulogic; -- UART1 tx data
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rxd1 : in std_ulogic; -- UART1 rx data
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ctsn1 : in std_ulogic; -- UART1 rx data
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rtsn1 : out std_ulogic; -- UART1 rx data
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txd2 : out std_ulogic; -- UART2 tx data
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rxd2 : in std_ulogic; -- UART2 rx data
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ctsn2 : in std_ulogic; -- UART1 rx data
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rtsn2 : out std_ulogic; -- UART1 rx data
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pio : inout std_logic_vector(17 downto 0); -- I/O port
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emdio : inout std_logic; -- ethernet PHY interface
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etx_clk : in std_ulogic;
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erx_clk : in std_ulogic;
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erxd : in std_logic_vector(3 downto 0);
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erx_dv : in std_ulogic;
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erx_er : in std_ulogic;
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erx_col : in std_ulogic;
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erx_crs : in std_ulogic;
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emdint : in std_ulogic;
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etxd : out std_logic_vector(3 downto 0);
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etx_en : out std_ulogic;
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etx_er : out std_ulogic;
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emdc : out std_ulogic;
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ps2clk : inout std_logic_vector(1 downto 0);
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ps2data : inout std_logic_vector(1 downto 0);
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vid_clock : out std_ulogic;
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vid_blankn : out std_ulogic;
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vid_syncn : out std_ulogic;
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vid_hsync : out std_ulogic;
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vid_vsync : out std_ulogic;
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vid_r : out std_logic_vector(7 downto 0);
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vid_g : out std_logic_vector(7 downto 0);
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vid_b : out std_logic_vector(7 downto 0);
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spw_clk : in std_ulogic;
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spw_rxdp : in std_logic_vector(0 to 2);
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spw_rxdn : in std_logic_vector(0 to 2);
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spw_rxsp : in std_logic_vector(0 to 2);
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spw_rxsn : in std_logic_vector(0 to 2);
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spw_txdp : out std_logic_vector(0 to 2);
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spw_txdn : out std_logic_vector(0 to 2);
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spw_txsp : out std_logic_vector(0 to 2);
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spw_txsn : out std_logic_vector(0 to 2);
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usb_clkout : in std_ulogic;
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usb_d : inout std_logic_vector(15 downto 0);
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usb_linestate : in std_logic_vector(1 downto 0);
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usb_opmode : out std_logic_vector(1 downto 0);
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usb_reset : out std_ulogic;
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usb_rxactive : in std_ulogic;
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usb_rxerror : in std_ulogic;
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usb_rxvalid : in std_ulogic;
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usb_suspend : out std_ulogic;
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usb_termsel : out std_ulogic;
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usb_txready : in std_ulogic;
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usb_txvalid : out std_ulogic;
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usb_validh : inout std_ulogic;
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usb_xcvrsel : out std_ulogic;
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jorisvr |
usb_vbus : in std_ulogic
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5 |
jorisvr |
);
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end;
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architecture rtl of leon3mp is
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attribute syn_netlist_hierarchy : boolean;
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attribute syn_netlist_hierarchy of rtl : architecture is false;
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
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CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
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jorisvr |
CFG_GRUSBDC;
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jorisvr |
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdram_out_type;
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signal sdo2, sdo3 : sdctrl_out_type;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clkm, rstn, rstraw, sdclkl : std_ulogic;
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signal cgi, cgi2 : clkgen_in_type;
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signal cgo, cgo2 : clkgen_out_type;
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signal u1i, u2i, dui : uart_in_type;
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signal u1o, u2o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal ethi, ethi1, ethi2 : eth_in_type;
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signal etho, etho1, etho2 : eth_out_type;
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal can_lrx, can_ltx : std_logic_vector(0 to 7);
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signal lclk, rst, ndsuact, wdogl : std_ulogic;
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signal tck, tckn, tms, tdi, tdo : std_ulogic;
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signal ethclk : std_ulogic;
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signal kbdi : ps2_in_type;
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signal kbdo : ps2_out_type;
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signal moui : ps2_in_type;
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signal mouo : ps2_out_type;
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signal vgao : apbvga_out_type;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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jorisvr |
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
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jorisvr |
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signal stati : ahbstat_in_type;
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signal spw_clkl : std_ulogic;
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signal spw_tick_in: std_logic;
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signal spw_di: std_logic;
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signal spw_si: std_logic;
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signal spw_do: std_logic;
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signal spw_so: std_logic;
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signal uclk : std_ulogic;
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signal usbi : grusb_in_type;
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signal usbo : grusb_out_type;
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constant SPW_LOOP_BACK : integer := 0;
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signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
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signal clk_sel : std_logic_vector(1 downto 0);
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of clk50 : signal is true;
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attribute syn_preserve of clk50 : signal is true;
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attribute keep of clk50 : signal is true;
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attribute syn_keep of video_clk : signal is true;
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attribute syn_preserve of video_clk : signal is true;
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attribute keep of video_clk : signal is true;
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attribute keep of spw_clkl : signal is true;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
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ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
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clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
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port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
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sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
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port map (sdclk, sdclkl);
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resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
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rst0 : rstgen -- reset generator
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port map (rst, clkm, cgo.clklock, rstn, rstraw);
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
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306 |
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CFG_MMU_PAGE, CFG_BP)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
|
309 |
|
|
end generate;
|
310 |
|
|
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
|
311 |
|
|
|
312 |
|
|
dsugen : if CFG_DSU = 1 generate
|
313 |
|
|
dsu0 : dsu3 -- LEON3 Debug Support Unit
|
314 |
|
|
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
|
315 |
|
|
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
|
316 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
|
317 |
|
|
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
|
318 |
|
|
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
|
319 |
|
|
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
|
320 |
|
|
ndsuact <= not dsuo.active;
|
321 |
|
|
end generate;
|
322 |
|
|
end generate;
|
323 |
|
|
nodsu : if CFG_DSU = 0 generate
|
324 |
|
|
dsuo.tstop <= '0'; dsuo.active <= '0';
|
325 |
|
|
end generate;
|
326 |
|
|
|
327 |
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
328 |
|
|
dcom0: ahbuart -- Debug UART
|
329 |
|
|
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
|
330 |
|
|
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
|
331 |
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
|
332 |
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
|
333 |
|
|
end generate;
|
334 |
|
|
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
335 |
|
|
|
336 |
|
|
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
|
337 |
|
|
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
|
338 |
|
|
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
|
339 |
|
|
open, open, open, open, open, open, open, gnd(0));
|
340 |
|
|
end generate;
|
341 |
|
|
|
342 |
|
|
----------------------------------------------------------------------
|
343 |
|
|
--- Memory controllers ----------------------------------------------
|
344 |
|
|
----------------------------------------------------------------------
|
345 |
|
|
|
346 |
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
|
347 |
|
|
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
|
348 |
|
|
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
|
349 |
|
|
|
350 |
|
|
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
|
351 |
|
|
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
|
352 |
|
|
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
|
353 |
|
|
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
|
354 |
|
|
pageburst => CFG_MCTRL_PAGE)
|
355 |
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
|
356 |
|
|
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
|
357 |
|
|
sdwen_pad : outpad generic map (tech => padtech)
|
358 |
|
|
port map (sdwen, sdo.sdwen);
|
359 |
|
|
sdras_pad : outpad generic map (tech => padtech)
|
360 |
|
|
port map (sdrasn, sdo.rasn);
|
361 |
|
|
sdcas_pad : outpad generic map (tech => padtech)
|
362 |
|
|
port map (sdcasn, sdo.casn);
|
363 |
|
|
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
|
364 |
|
|
port map (sddqm, sdo.dqm(3 downto 0));
|
365 |
|
|
end generate;
|
366 |
|
|
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
|
367 |
|
|
port map (sdcsn, sdo.sdcsn);
|
368 |
|
|
|
369 |
|
|
addr_pad : outpadv generic map (width => 28, tech => padtech)
|
370 |
|
|
port map (address, memo.address(27 downto 0));
|
371 |
|
|
rams_pad : outpadv generic map (width => 5, tech => padtech)
|
372 |
|
|
port map (ramsn, memo.ramsn(4 downto 0));
|
373 |
|
|
roms_pad : outpadv generic map (width => 2, tech => padtech)
|
374 |
|
|
port map (romsn, memo.romsn(1 downto 0));
|
375 |
|
|
oen_pad : outpad generic map (tech => padtech)
|
376 |
|
|
port map (oen, memo.oen);
|
377 |
|
|
rwen_pad : outpadv generic map (width => 4, tech => padtech)
|
378 |
|
|
port map (rwen, memo.wrn);
|
379 |
|
|
roen_pad : outpadv generic map (width => 5, tech => padtech)
|
380 |
|
|
port map (ramoen, memo.ramoen(4 downto 0));
|
381 |
|
|
wri_pad : outpad generic map (tech => padtech)
|
382 |
|
|
port map (writen, memo.writen);
|
383 |
|
|
read_pad : outpad generic map (tech => padtech)
|
384 |
|
|
port map (read, memo.read);
|
385 |
|
|
iosn_pad : outpad generic map (tech => padtech)
|
386 |
|
|
port map (iosn, memo.iosn);
|
387 |
|
|
bdr : for i in 0 to 3 generate
|
388 |
|
|
data_pad : iopadv generic map (tech => padtech, width => 8)
|
389 |
|
|
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
|
390 |
|
|
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
|
391 |
|
|
end generate;
|
392 |
|
|
|
393 |
|
|
----------------------------------------------------------------------
|
394 |
|
|
--- APB Bridge and various periherals -------------------------------
|
395 |
|
|
----------------------------------------------------------------------
|
396 |
|
|
|
397 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
398 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
|
399 |
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
|
400 |
|
|
|
401 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
402 |
|
|
uart1 : apbuart -- UART 1
|
403 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
404 |
|
|
fifosize => CFG_UART1_FIFO)
|
405 |
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
406 |
|
|
u1i.extclk <= '0';
|
407 |
|
|
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
|
408 |
|
|
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
|
409 |
|
|
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
|
410 |
|
|
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
|
411 |
|
|
end generate;
|
412 |
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
413 |
|
|
|
414 |
|
|
ua2 : if CFG_UART2_ENABLE /= 0 generate
|
415 |
|
|
uart2 : apbuart -- UART 2
|
416 |
|
|
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
|
417 |
|
|
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
|
418 |
|
|
u2i.extclk <= '0';
|
419 |
|
|
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
|
420 |
|
|
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
|
421 |
|
|
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
|
422 |
|
|
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
|
423 |
|
|
end generate;
|
424 |
|
|
noua1 : if CFG_UART2_ENABLE = 0 generate
|
425 |
|
|
apbo(9) <= apb_none; rtsn2 <= '0';
|
426 |
|
|
end generate;
|
427 |
|
|
|
428 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
429 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
430 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
|
431 |
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
432 |
|
|
end generate;
|
433 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
434 |
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
435 |
|
|
irqi(i).irl <= "0000";
|
436 |
|
|
end generate;
|
437 |
|
|
apbo(2) <= apb_none;
|
438 |
|
|
end generate;
|
439 |
|
|
|
440 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
441 |
|
|
timer0 : gptimer -- timer unit
|
442 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
443 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
444 |
|
|
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
|
445 |
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
|
446 |
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
447 |
|
|
end generate;
|
448 |
|
|
wden : if CFG_GPT_WDOGEN /= 0 generate
|
449 |
|
|
wdogl <= gpto.wdogn or not rstn;
|
450 |
|
|
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
|
451 |
|
|
end generate;
|
452 |
|
|
wddis : if CFG_GPT_WDOGEN = 0 generate
|
453 |
|
|
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
|
454 |
|
|
end generate;
|
455 |
|
|
|
456 |
|
|
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
457 |
|
|
|
458 |
|
|
kbd : if CFG_KBD_ENABLE /= 0 generate
|
459 |
|
|
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
|
460 |
|
|
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
|
461 |
|
|
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
|
462 |
|
|
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
|
463 |
|
|
end generate;
|
464 |
|
|
nokbd : if CFG_KBD_ENABLE = 0 generate
|
465 |
|
|
apbo(4) <= apb_none; mouo <= ps2o_none;
|
466 |
|
|
apbo(5) <= apb_none; kbdo <= ps2o_none;
|
467 |
|
|
end generate;
|
468 |
|
|
kbdclk_pad : iopad generic map (tech => padtech)
|
469 |
|
|
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
|
470 |
|
|
kbdata_pad : iopad generic map (tech => padtech)
|
471 |
|
|
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
|
472 |
|
|
mouclk_pad : iopad generic map (tech => padtech)
|
473 |
|
|
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
|
474 |
|
|
mouata_pad : iopad generic map (tech => padtech)
|
475 |
|
|
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
|
476 |
|
|
|
477 |
|
|
vga : if CFG_VGA_ENABLE /= 0 generate
|
478 |
|
|
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
|
479 |
|
|
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
|
480 |
|
|
video_clock_pad : outpad generic map ( tech => padtech)
|
481 |
|
|
port map (vid_clock, video_clk);
|
482 |
|
|
video_clk <= not ethclk;
|
483 |
|
|
end generate;
|
484 |
|
|
|
485 |
|
|
-- Note: SVGA graphics support removed to make room for SpaceWire Light
|
486 |
|
|
assert CFG_SVGA_ENABLE = 0 report "SVGA graphics not supported";
|
487 |
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate
|
488 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) <= ahbm_none;
|
489 |
|
|
apbo(6) <= apb_none;
|
490 |
|
|
vgao <= vgao_none;
|
491 |
|
|
video_clk <= not clkm;
|
492 |
|
|
video_clock_pad : outpad generic map ( tech => padtech)
|
493 |
|
|
port map (vid_clock, video_clk);
|
494 |
|
|
end generate;
|
495 |
|
|
|
496 |
|
|
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
|
497 |
|
|
apbo(6) <= apb_none; vgao <= vgao_none;
|
498 |
|
|
video_clk <= not clkm;
|
499 |
|
|
video_clock_pad : outpad generic map ( tech => padtech)
|
500 |
|
|
port map (vid_clock, video_clk);
|
501 |
|
|
end generate;
|
502 |
|
|
|
503 |
|
|
blank_pad : outpad generic map (tech => padtech)
|
504 |
|
|
port map (vid_blankn, vgao.blank);
|
505 |
|
|
comp_sync_pad : outpad generic map (tech => padtech)
|
506 |
|
|
port map (vid_syncn, vgao.comp_sync);
|
507 |
|
|
vert_sync_pad : outpad generic map (tech => padtech)
|
508 |
|
|
port map (vid_vsync, vgao.vsync);
|
509 |
|
|
horiz_sync_pad : outpad generic map (tech => padtech)
|
510 |
|
|
port map (vid_hsync, vgao.hsync);
|
511 |
|
|
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
|
512 |
|
|
port map (vid_r, vgao.video_out_r);
|
513 |
|
|
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
|
514 |
|
|
port map (vid_g, vgao.video_out_g);
|
515 |
|
|
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
|
516 |
|
|
port map (vid_b, vgao.video_out_b);
|
517 |
|
|
|
518 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
|
519 |
|
|
grgpio0: grgpio
|
520 |
|
|
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
|
521 |
|
|
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
|
522 |
|
|
gpioi => gpioi, gpioo => gpioo);
|
523 |
|
|
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
|
524 |
|
|
pio_pads : for i in 1 to 2 generate
|
525 |
|
|
pio_pad : iopad generic map (tech => padtech)
|
526 |
|
|
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
527 |
|
|
end generate;
|
528 |
|
|
end generate;
|
529 |
|
|
p1 : if (CFG_CAN = 0) generate
|
530 |
|
|
pio_pads : for i in 4 to 5 generate
|
531 |
|
|
pio_pad : iopad generic map (tech => padtech)
|
532 |
|
|
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
533 |
|
|
end generate;
|
534 |
|
|
end generate;
|
535 |
|
|
pio_pad0 : iopad generic map (tech => padtech)
|
536 |
|
|
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
|
537 |
|
|
pio_pad1 : iopad generic map (tech => padtech)
|
538 |
|
|
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
|
539 |
|
|
pio_pads : for i in 6 to 17 generate
|
540 |
|
|
pio_pad : iopad generic map (tech => padtech)
|
541 |
|
|
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
542 |
|
|
end generate;
|
543 |
|
|
|
544 |
|
|
end generate;
|
545 |
|
|
|
546 |
|
|
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
|
547 |
|
|
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
|
548 |
|
|
nftslv => CFG_AHBSTATN)
|
549 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
|
550 |
|
|
end generate;
|
551 |
|
|
|
552 |
|
|
-----------------------------------------------------------------------
|
553 |
|
|
--- ETHERNET ---------------------------------------------------------
|
554 |
|
|
-----------------------------------------------------------------------
|
555 |
|
|
|
556 |
|
|
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
|
557 |
|
|
e1 : grethm generic map(
|
558 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
559 |
|
|
pindex => 13, paddr => 13, pirq => 13, memtech => memtech,
|
560 |
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
561 |
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
562 |
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
|
563 |
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
|
564 |
|
|
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
|
565 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
|
566 |
|
|
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
|
567 |
|
|
end generate;
|
568 |
|
|
|
569 |
|
|
ethpads : if (CFG_GRETH = 1) generate -- eth pads
|
570 |
|
|
emdio_pad : iopad generic map (tech => padtech)
|
571 |
|
|
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
572 |
|
|
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
573 |
|
|
port map (etx_clk, ethi.tx_clk);
|
574 |
|
|
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
575 |
|
|
port map (erx_clk, ethi.rx_clk);
|
576 |
|
|
erxd_pad : inpadv generic map (tech => padtech, width => 4)
|
577 |
|
|
port map (erxd, ethi.rxd(3 downto 0));
|
578 |
|
|
erxdv_pad : inpad generic map (tech => padtech)
|
579 |
|
|
port map (erx_dv, ethi.rx_dv);
|
580 |
|
|
erxer_pad : inpad generic map (tech => padtech)
|
581 |
|
|
port map (erx_er, ethi.rx_er);
|
582 |
|
|
erxco_pad : inpad generic map (tech => padtech)
|
583 |
|
|
port map (erx_col, ethi.rx_col);
|
584 |
|
|
erxcr_pad : inpad generic map (tech => padtech)
|
585 |
|
|
port map (erx_crs, ethi.rx_crs);
|
586 |
|
|
emdint_pad : inpad generic map (tech => padtech)
|
587 |
|
|
port map (emdint, ethi.mdint);
|
588 |
|
|
|
589 |
|
|
etxd_pad : outpadv generic map (tech => padtech, width => 4)
|
590 |
|
|
port map (etxd, etho.txd(3 downto 0));
|
591 |
|
|
etxen_pad : outpad generic map (tech => padtech)
|
592 |
|
|
port map ( etx_en, etho.tx_en);
|
593 |
|
|
etxer_pad : outpad generic map (tech => padtech)
|
594 |
|
|
port map (etx_er, etho.tx_er);
|
595 |
|
|
emdc_pad : outpad generic map (tech => padtech)
|
596 |
|
|
port map (emdc, etho.mdc);
|
597 |
|
|
end generate;
|
598 |
|
|
|
599 |
|
|
-----------------------------------------------------------------------
|
600 |
|
|
--- AHB RAM ----------------------------------------------------------
|
601 |
|
|
-----------------------------------------------------------------------
|
602 |
|
|
|
603 |
|
|
ocram : if CFG_AHBRAMEN = 1 generate
|
604 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
605 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
606 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(7));
|
607 |
|
|
end generate;
|
608 |
|
|
|
609 |
|
|
-----------------------------------------------------------------------
|
610 |
|
|
--- Multi-core CAN ---------------------------------------------------
|
611 |
|
|
-----------------------------------------------------------------------
|
612 |
|
|
|
613 |
|
|
can0 : if CFG_CAN = 1 generate
|
614 |
|
|
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
|
615 |
|
|
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
|
616 |
|
|
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
|
617 |
|
|
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
|
618 |
|
|
can_tx_pad1 : iopad generic map (tech => padtech)
|
619 |
|
|
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
|
620 |
|
|
can_rx_pad1 : iopad generic map (tech => padtech)
|
621 |
|
|
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
|
622 |
|
|
canpas : if CFG_CAN_NUM = 2 generate
|
623 |
|
|
can_tx_pad2 : iopad generic map (tech => padtech)
|
624 |
|
|
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
|
625 |
|
|
can_rx_pad2 : iopad generic map (tech => padtech)
|
626 |
|
|
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
|
627 |
|
|
end generate;
|
628 |
|
|
end generate;
|
629 |
|
|
|
630 |
|
|
-- standby controlled by pio(3) and pio(0)
|
631 |
|
|
|
632 |
|
|
-----------------------------------------------------------------------
|
633 |
|
|
--- SpaceWire Light --------------------------------------------------
|
634 |
|
|
-----------------------------------------------------------------------
|
635 |
|
|
|
636 |
|
|
spw0: spwamba
|
637 |
|
|
generic map (
|
638 |
|
|
tech => memtech,
|
639 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
640 |
|
|
pindex => 10,
|
641 |
|
|
paddr => 10,
|
642 |
|
|
pirq => 10,
|
643 |
|
|
sysfreq => real(CPU_FREQ) * 1000.0,
|
644 |
|
|
txclkfreq => 200.0e6,
|
645 |
|
|
rximpl => impl_fast,
|
646 |
|
|
rxchunk => 4,
|
647 |
|
|
tximpl => impl_fast,
|
648 |
|
|
timecodegen => true,
|
649 |
|
|
rxfifosize => 8,
|
650 |
|
|
txfifosize => 8,
|
651 |
|
|
desctablesize => 10,
|
652 |
|
|
maxburst => 3 )
|
653 |
|
|
port map (
|
654 |
|
|
clk => clkm,
|
655 |
|
|
rxclk => spw_clkl,
|
656 |
|
|
txclk => spw_clkl,
|
657 |
|
|
rstn => rstn,
|
658 |
|
|
apbi => apbi,
|
659 |
|
|
apbo => apbo(10),
|
660 |
|
|
ahbi => ahbmi,
|
661 |
|
|
ahbo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
|
662 |
|
|
tick_in => spw_tick_in,
|
663 |
7 |
jorisvr |
tick_out => open,
|
664 |
5 |
jorisvr |
spw_di => spw_di,
|
665 |
|
|
spw_si => spw_si,
|
666 |
|
|
spw_do => spw_do,
|
667 |
|
|
spw_so => spw_so );
|
668 |
|
|
|
669 |
|
|
spw_rxd_pad: inpad_ds
|
670 |
|
|
generic map (padtech, lvds, x25v)
|
671 |
|
|
port map (spw_rxdp(0), spw_rxdn(0), spw_di);
|
672 |
|
|
spw_rxs_pad: inpad_ds
|
673 |
|
|
generic map (padtech, lvds, x25v)
|
674 |
|
|
port map (spw_rxsp(0), spw_rxsn(0), spw_si);
|
675 |
|
|
spw_txd_pad: outpad_ds
|
676 |
|
|
generic map (padtech, lvds, x25v)
|
677 |
|
|
port map (spw_txdp(0), spw_txdn(0), spw_do, '0');
|
678 |
|
|
spw_txs_pad: outpad_ds
|
679 |
|
|
generic map (padtech, lvds, x25v)
|
680 |
|
|
port map (spw_txsp(0), spw_txsn(0), spw_so, '0');
|
681 |
|
|
|
682 |
|
|
-- Use 2nd GPTIMER unit to generate external tick_in signal.
|
683 |
|
|
spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
|
684 |
|
|
|
685 |
|
|
-- Generate 200 MHz clock for fast receiver/transmitter.
|
686 |
|
|
spwclk0: DCM
|
687 |
|
|
generic map (
|
688 |
|
|
CLKFX_DIVIDE => 1,
|
689 |
|
|
CLKFX_MULTIPLY => 4,
|
690 |
|
|
CLK_FEEDBACK => "NONE",
|
691 |
|
|
CLKIN_DIVIDE_BY_2 => false,
|
692 |
|
|
CLKIN_PERIOD => 20.0,
|
693 |
|
|
CLKOUT_PHASE_SHIFT => "NONE",
|
694 |
|
|
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
695 |
|
|
DFS_FREQUENCY_MODE => "LOW",
|
696 |
|
|
DUTY_CYCLE_CORRECTION => true,
|
697 |
|
|
STARTUP_WAIT => false )
|
698 |
|
|
port map (
|
699 |
|
|
CLKIN => lclk,
|
700 |
|
|
RST => not rstraw,
|
701 |
|
|
CLKFX => spw_clkl );
|
702 |
|
|
|
703 |
|
|
-------------------------------------------------------------------------------
|
704 |
|
|
--- USB -----------------------------------------------------------------------
|
705 |
|
|
-------------------------------------------------------------------------------
|
706 |
|
|
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
|
707 |
|
|
-- time (board has only one USB transceiver), therefore they share AHB
|
708 |
|
|
-- master/slave indexes
|
709 |
|
|
-----------------------------------------------------------------------------
|
710 |
|
|
-- Shared pads
|
711 |
|
|
-----------------------------------------------------------------------------
|
712 |
|
|
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
|
713 |
|
|
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
|
714 |
|
|
port map (usb_clkout, uclk);
|
715 |
|
|
|
716 |
|
|
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
|
717 |
|
|
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
|
718 |
|
|
|
719 |
|
|
usb_txready_pad : inpad generic map (tech => padtech)
|
720 |
|
|
port map (usb_txready,usbi.txready);
|
721 |
|
|
usb_rxvalid_pad : inpad generic map (tech => padtech)
|
722 |
|
|
port map (usb_rxvalid,usbi.rxvalid);
|
723 |
|
|
usb_rxerror_pad : inpad generic map (tech => padtech)
|
724 |
|
|
port map (usb_rxerror,usbi.rxerror);
|
725 |
|
|
usb_rxactive_pad : inpad generic map (tech => padtech)
|
726 |
|
|
port map (usb_rxactive,usbi.rxactive);
|
727 |
|
|
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
|
728 |
|
|
port map (usb_linestate,usbi.linestate);
|
729 |
|
|
usb_vbus_pad : inpad generic map (tech => padtech)
|
730 |
|
|
port map (usb_vbus, usbi.vbusvalid);
|
731 |
|
|
|
732 |
|
|
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
|
733 |
|
|
port map (usb_reset,usbo.reset);
|
734 |
|
|
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
|
735 |
|
|
port map (usb_suspend,usbo.suspendm);
|
736 |
|
|
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
|
737 |
|
|
port map (usb_termsel,usbo.termselect);
|
738 |
|
|
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
|
739 |
|
|
port map (usb_xcvrsel,usbo.xcvrselect(0));
|
740 |
|
|
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
|
741 |
|
|
port map (usb_txvalid,usbo.txvalid);
|
742 |
|
|
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
|
743 |
|
|
port map (usb_opmode,usbo.opmode);
|
744 |
|
|
|
745 |
|
|
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
|
746 |
|
|
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
|
747 |
|
|
|
748 |
|
|
end generate;
|
749 |
|
|
|
750 |
|
|
-----------------------------------------------------------------------------
|
751 |
|
|
-- USB 2.0 Device Controller
|
752 |
|
|
-----------------------------------------------------------------------------
|
753 |
|
|
usbdc0: if CFG_GRUSBDC = 1 generate
|
754 |
|
|
usbdc0: grusbdc
|
755 |
|
|
generic map(
|
756 |
|
|
hsindex => 5, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
|
757 |
|
|
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
|
758 |
|
|
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
|
759 |
|
|
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
|
760 |
|
|
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
|
761 |
|
|
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
|
762 |
|
|
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
|
763 |
|
|
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
|
764 |
|
|
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
|
765 |
|
|
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
|
766 |
|
|
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
|
767 |
|
|
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
|
768 |
|
|
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
|
769 |
|
|
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
|
770 |
|
|
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
|
771 |
|
|
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
|
772 |
|
|
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
|
773 |
|
|
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
|
774 |
|
|
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
|
775 |
|
|
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
|
776 |
|
|
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
|
777 |
|
|
memtech => memtech)
|
778 |
|
|
port map(
|
779 |
|
|
uclk => uclk,
|
780 |
|
|
usbi => usbi,
|
781 |
|
|
usbo => usbo,
|
782 |
|
|
hclk => clkm,
|
783 |
|
|
hrst => rstn,
|
784 |
|
|
ahbmi => ahbmi,
|
785 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
|
786 |
|
|
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
|
787 |
|
|
ahbsi => ahbsi,
|
788 |
|
|
ahbso => ahbso(5)
|
789 |
|
|
);
|
790 |
|
|
end generate usbdc0;
|
791 |
|
|
|
792 |
|
|
-----------------------------------------------------------------------------
|
793 |
|
|
-- USB DCL
|
794 |
|
|
-----------------------------------------------------------------------------
|
795 |
|
|
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
|
796 |
|
|
usb_dcl0: grusb_dcl
|
797 |
|
|
generic map (
|
798 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
|
799 |
|
|
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
|
800 |
|
|
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
|
801 |
|
|
port map (
|
802 |
|
|
uclk, usbi, usbo, clkm, rstn, ahbmi,
|
803 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
|
804 |
|
|
CFG_SPW_NUM*CFG_SPW_EN));
|
805 |
|
|
end generate usb_dcl0;
|
806 |
|
|
|
807 |
|
|
-----------------------------------------------------------------------
|
808 |
|
|
--- Drive unused bus elements ---------------------------------------
|
809 |
|
|
-----------------------------------------------------------------------
|
810 |
|
|
|
811 |
|
|
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
|
812 |
|
|
-- ahbmo(i) <= ahbm_none;
|
813 |
|
|
-- end generate;
|
814 |
|
|
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
815 |
|
|
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
816 |
|
|
|
817 |
|
|
-----------------------------------------------------------------------
|
818 |
|
|
--- Boot message ----------------------------------------------------
|
819 |
|
|
-----------------------------------------------------------------------
|
820 |
|
|
|
821 |
|
|
-- pragma translate_off
|
822 |
|
|
x : report_version
|
823 |
|
|
generic map (
|
824 |
|
|
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
|
825 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
826 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
827 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
828 |
|
|
mdel => 1
|
829 |
|
|
);
|
830 |
|
|
-- pragma translate_on
|
831 |
|
|
end;
|